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201ASP Mid-Range Family PIC16F887 Peripheral Configuration and Assembly Programming

2006 Microchip Technology Incorporated. All Rights Reserved.

201ASP

Slide 1

Objectives

At the end of this class you will: Understand the basic PICmicro peripherals and their associated registers Have HANDS ON experience initializing MidRange peripherals Be able to implement peripherals not covered here Understand interrupts and polling Write your own application code from scratch

2006 Microchip Technology Incorporated. All Rights Reserved.

201ASP

Slide 2

To get the most from this Class

Ideally you should be familiar with the following:

Assembler programming Basic Mid-Range family Instruction set Data and Program memory organization MPLAB Integrated Development Environment Microchip ICD2 debugger

2006 Microchip Technology Incorporated. All Rights Reserved.

201ASP

Slide 3

201ASP Agenda

Brief review of Mid-Range Architecture, Instruction Set and MCHP Tools Interrupts on the Mid-Range PICmicro Basic Interrupts Lab Peripheral discussion: Input/Output Ports Timers Timer0 Timer1 Timer1 Lab Timer2 Timer2 Lab
201ASP Slide 4

2006 Microchip Technology Incorporated. All Rights Reserved.

201ASP Agenda

Enhanced Capture / Compare/ PWM Module (ECCP) PWM and Output Compare Labs Analog Comparator Analog to Digital Converters (ADC) ADC Lab Enhanced Universal Asynchronous/Synchronous Receiver/Transmitter (EUSART) I2C and SPI (Master Synchronous Serial Port) Multiple Interrupt Lab Wrap-Up and additional questions
201ASP Slide 5

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Mid-Range Family Basic Architecture and Development Tools

2006 Microchip Technology Incorporated. All Rights Reserved.

201ASP

Slide 6

Mid-Range PIC Block Diagram


Pages of Program Memory STATUS REGISTER

PROGRAM COUNTER

8-bit value from instruction

MUX

Banks of Data Memory

ADC

ALU
TIMER0
14-bits

INSTRUCTION REGISTER

WORKING REGISTER

EUSART

MSSP
PERIPHERALS
2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 7

Program Memory

Maximum 8K words:

Reset Vector

0000h

(8K x 14-bits/word)/1 byte = 14Kbytes of memory Interrupt Vector 0004h Page 0


0005h 07FFh 0800h 0FFFh 1000h 17FFh 1800h 1FFFh

Reset Vector at 0000h

PC will go to this address upon any reset

Page 1

Interrupt Vector at 0004h

PC will go to this address upon any Interrupt

Page 2

Page 3

2006 Microchip Technology Incorporated. All Rights Reserved.

201ASP

Slide 8

Program Counter (PC) and Stack

13-bit PC

PCLATH

PCL ALU result (8-bits) or OPCODE(11-bits) PCH Paging bits


PCH<12:8>
CALL, RETURN, RETFIE, RETLW

PCL

PC<12:0>

Updated from PCLATH Specifies page in program memory

Stack Level 1

8 Level Deep Stack

Stores the contents of the PC

Stack Level 8

PUSHES

CALL/Interrupt RETURN, RETFIE,RETLW


201ASP

POPS

Program Memory

2006 Microchip Technology Incorporated. All Rights Reserved.

Slide 9

Data Memory Map


000h 080h 100h 10Fh 110h 180h 18Fh 190h

Special Function Registers 01Fh


020h

Special Function Registers

SFR
09Fh 0A0h

SFR

128 Bytes

General Purpose Registers

General Purpose Registers


0EFh

General Purpose Registers


16Fh

General Purpose Registers


1EFh

07Fh

Shared Bank1

0FFh

Shared Bank2

17Fh

Shared Bank3

1FFh

Bank 0

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201ASP

Slide 10

Special Function Registers (SFRs )

Register File Concept

Accessed like any other register Some registers carry across all banks (PCLATH, INTCON, etc.)

PORTB PORTC PORTD PORTE PCLATH INTCON PIR1 PIR2

06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh

TRISB TRISC TRISD TRISE PCLATH INTCON PIE1 PIE2

86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh

Bank0

Bank1

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201ASP

Slide 11

Status Register

IRP

RP1 RP0

TO

PD

DC(1)

C(1)

Contains:

Arithmetic status of the ALU The RESET status Bank select bits for data memory

RP1 Bank RP0 Register Select bit: (used for indirect addressing) RP1 0 RP0 0 1 = Bank 0 2,3 1 1 0,1 0 0 = Bank 1 1 BANK0 BANK1 BANK2 BANK3

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201ASP

Slide 12

Instruction Set Overview


35 single word instructions All are single cycle except for program branches Three categories of operations:
BIT-ORIENTED

BYTE-ORIENTED

LITERAL and CONTROL ORIENTED

All on one slide!!!


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PICmicro Development Tools

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201ASP

Slide 14

PICmicro : Development Tools

MPLAB IDE

MPLAB IDE: Integrated Development Environment It integrates different Microchip and third party tools

Code Editor Cross Compilers Assemblers Simulators, In-Circuit Debuggers, Emulators Programmers

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201ASP

Slide 15

ICD-2 (In Circuit Debugger)

MPLAB ICD 2 is a low cost, real-time debugger and programmer. It offers the following features.

Real time background debugging Reading/Writing memory space and EEDATA areas of target microcontroller Programs configuration bits Erase of program memory space with verification

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201ASP

Slide 16

RS-232 DC 9V Input MAX232.

APP001 Board
A/D VR CAN & RS-485

ICD2 Connecter

J6 (RS-232)

Reset Button

PIC16F887

SPI EEPROM 25LCxxx

I2C EEPROM 24LCxx

16MHz Crystal

J2 (32768Hz)

LCD Bright

PORTD LED

2 X 16 LCD Module
201ASP

J9 (LED)

Button
Slide 17

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Interrupts

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201ASP

Slide 18

Polling and Interrupts Often we would like the processor to perform a task if a specific event occurs Two methods to check if this event has occurred:

Polling:

Continuously check for event at various points in the code INTERRUPTS normal code execution only when event occurs

Interrupts:

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201ASP

Slide 19

Polling
bsf PORTA,1 ;Set bit 1 of ;PORTA RA<1> = 1

btfss

INTCON, T0IF ;Check Timer0 ;interrupt flag in ;INTCON and ;skip the next ;instruction if it ;is set $-1 ;Go back to ;previous ;instruction ;Clear bit 0 of ;PORTA
201ASP

NO

T0IF = 1 ??

goto

YES
RA<1> = 0

bcf

PORTA,1

2006 Microchip Technology Incorporated. All Rights Reserved.

Slide 20

Interrupts
Reset code goto 000h Start
no interrupt

;========================= int_vector code 004h


Interrupt Service Routine (ISR)

Main program execution


retfie instruction interrupt flag set

retfie

;return from ;interrupt ;========================= main_prog Start code

Execute ISR at address 004h

;start label for main code


Main program code

end
2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 21

Enabling Interrupts

Processor must be told that interrupts will be used in the code

A number of registers with enable bits are used:


Interrupt Control Register (INTCON) Peripheral Interrupt Enable Register 1 (PIE1) Peripheral Interrupt Enable Register 2 (PIE2)

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201ASP

Slide 22

INTCON (Core Interrupts)


ENABLE BITS GIE: Global Interrupt Enable *Must be set to use ANY interrupts on the PICmicro PEIE: Peripheral Interrupt Enable *Must be set to use Peripheral Interrupts TOIE: Timer0 Overflow Interrupt Enable INTE: RB0/INT External Interrupt Enable RBIE: PORTB Change on Interrupt Enable

GIE

PEIE TOIE INTE RBIE TOIF INTF RBIF

*Flags will set even if interrupts arent enabled!


2006 Microchip Technology Incorporated. All Rights Reserved.

FLAG BITS TOIF: Timer0 Overflow Interrupt Flag INTF: RB0/INT External Interrupt Flag RBIF: PORTB Change Interrupt Flag
201ASP Slide 23

Enabling a Core Interrupt


Int_vect CODE 004h ;clear INTF to enable ;further interrupts bcf INTCON, INTF <ISR code> retfie

PROGRAM COUNTER goto $ address

goto $ address

STACK

Main Start

CODE <code to set up PORTB > ; initialize INTCON clrf INTCON ;enable an external ;interrupt on the INT pin bsf INTCON, INTE ;enable global interrupts bsf INTCON, GIE

INTCON 0 0 0 1
GIE

0 1
INTE

0 1
INTF

INT Interrupt!!

goto

; sit here and loop forever


201ASP Slide 24

2006 Microchip Technology Incorporated. All Rights Reserved.

Peripheral Interrupts

Two registers to enable interrupts on specific peripherals:

*Flags will set even if interrupts are not enabled

Peripheral Interrupt Enable Register 1 (PIE1) Peripheral Interrupt Enable Register 2 (PIE2)

Two registers containing the specific peripheral interrupt flag:


Peripheral Interrupt Request Register 1 (PIR1)

Flags for peripheral interrupts enabled in PIE1

Peripheral Interrupt Request Register 2 (PIR2)

Flags for peripheral interrupts enabled in PIE2

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201ASP

Slide 25

PIE1 and PIR1 Registers*


PIE1 Register (Interrupt Enables)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE

PIR1 Register (Interrupt Flags)


ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF

Enable
ADIE
RCIE TXIE SSPIE

Flag
ADIF
RCIF TXIF SSPIF

Condition
ADC conversion complete
EUSART receive buffer is full EUSART transmit buffer is full I2C or SPI Interrupt

CCP1IE

CCP1IF

Timer1 register capture or compare match


Timer2 value and PR2 period value match Timer1 register has overflowed

TMR2IE TMR2IF TMR1IE TMR1IF

*Check

individual datasheets
201ASP Slide 26

2006 Microchip Technology Incorporated. All Rights Reserved.

PIE2 and PIR2 Registers


PIE2 Register (Interrupt Enables)
OSCFIE C2IE C1IE EEIE BCLIE ULPWUIE CCP2IE

PIR2 Register (Interrupt Flags)


OSCFIF C2IF C1IF EEIF BCLIF ULPWUIF CCP2IF

Enable
OSCFIE C2IE C1IE EEIE BCLIE

Flag
OSCFIF C2IF C1IF EEIF BCLIF

Condition
System Oscillator Failed Comparator2 output has changed Comparator1 output has changed Write operation has completed Bus collision has occurred in MSSP I2C mode

ULPWUIE
CCP2IE

ULPWUIF
CCP2IF

Wake-up condition has occurred


A timer1 Capture or Compare match has occurred
201ASP Slide 27

2006 Microchip Technology Incorporated. All Rights Reserved.

Enabling a Peripheral Interrupt


Int_vect CODE banksel bcf 004h PIR1 PIR1, TMR1IF

PROGRAM COUNTER goto $ address

<ISR code> retfie

goto $ address

STACK

Main Start

CODE banksel bcf banksel bsf bsf bsf PIR1 PIR1, TMR1IF PIE1 PIE, TMR1E INTCON, PEIE INTCON, GIE

INTCON 1 1 0
GIE PEIE

PIE1 1 PIR1
TMR1IE

<code to set up Timer1>

0 1

goto

; sit here and loop forever

Timer1 Overflow!

TMR1IF

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201ASP

Slide 28

Interrupt Logic
TMR0IE TMR0IF RBIE RBIF

Interrupt

TMR2IE TMR2IF ADIE ADIF


Other peripherals
2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP

GIE

PEIE
Slide 29

Interrupt Latency

Interrupt Latency:

time from interrupt event to execution of instruction at address 0004h synchronous interrupts (typically internal)

latency is 3Tcy. latency is 3 3.75Tcy

asynchronous interrupts (typically external)

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201ASP

Slide 30

Context Saving

During an interrupt:

Only the PC value is saved (on the stack) Registers augmented in the ISR are permanently changed

Key registers the user may want saved:

Working register Status PCLath User defined registers

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201ASP

Slide 31

Interrupt Priority

Mid-Range PIC microcontrollers treat all Interrupts with the same priority The user must do the following:

Determine source of interrupt Determine the order in which the interrupts are serviced.

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201ASP

Slide 32

Interrupt Priority Example


INT_VECTOR movwf movf movwf btfsc call btfsc call btfsc call Restore_context: movf movwf movf retfie
2006 Microchip Technology Incorporated. All Rights Reserved.

CODE 0x004 temp_w STATUS,w temp_status

; interrupt vector location ; save WREG

; save STATUS register

INTCON,RBIF ; PORTB change? PORTB_ISR PIR1,TMR2IF ; Timer 2 interrupt ? Timer2_ISR PIR2,TMR1IF ; Timer 1 interrupt ? Timer2 ISR

temp_status,w STATUS ; restore STATUS reg. temp_w,w ; restore WREG ; return from interrupt
201ASP Slide 33

Basic Interrupt Hands on Lab

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201ASP

Slide 34

Basic Interrupts

The objective of this is to:

Learn how to set up the System Oscillator


Learn how to set up and enable an internal interrupt on the Mid-Range PIC Become more familiar with the MPLAB IDE, the APP001Board and the ICD2

Building a Project Using the ICD to set a break point


201ASP Slide 35

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PIC16F887 Oscillator Diagram


Oscillator requests 4Mhz with Internal RC

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201ASP

Slide 36

Basic Interrupt Lab Overview


Interrupt Vector Call debounce delay function Increment Count variable Main Program Clear Variables

Initial PORTB for S3 input


Enable Interrupts No Operation NOP

Clear IF retfie

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201ASP

Slide 37

Lab Specifics (cont.)


Code is located in C:\RTC\201_ASP\Lab1-INT Use MPLAB and the ICD to program the PIC16F887 then run the program to view the LEDs increment.

2006 Microchip Technology Incorporated. All Rights Reserved.

201ASP

Slide 38

What you need to know

The function of the INTCON register bits

A subroutine called debounce is given that delays processing and prevents the mechanical bouncing of SW2 to generate multiple interrupts ( more on this in later labs) How to setup break points and a Watch Window in MPLAB
201ASP Slide 39

2006 Microchip Technology Incorporated. All Rights Reserved.

Basic Interrupt Lab Solution

bcf bsf bsf

INTCON,INTF INTCON,INTE INTCON,GIE

; ### Enable INT0 Interrupt ; ### Enable Global Interrupt

; Loop nop goto Loop : : Int_Service_Routine call Debounce incf PORTD,F

bcf INTCON,INTF retfie

; Delay until switch stops bouncing ; increments number of time button has ;been pushed ; ### clears the INT0 Interrupt Flag
201ASP Slide 40

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Peripherals

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201ASP

Slide 41

Mid-Range Family Peripherals

Digital I/O Ports Timers (0, 1, 2) Enhanced Capture/Compare/PWM Comparators Analog-to-Digital Converter EUSART I2C and SPI Serial Interface

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201ASP

Slide 42

Digital I/O Overview

Up to 35 bi-directional I/O pins, some multiplexed with peripheral functions High drive capability Direct, single cycle bit manipulation Most I/Os have ESD Multiplexed I/O pins default to ANALOG inputs on startup (high impedance state)

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201ASP

Slide 43

PORTx and TRISx Registers

Every PORT (A, B, C, D, E) will have a corresponding direction register TRISx


PORTB Register
RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0

Configures Data Data Direction


PORTB Tri-State Register TRISB
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0

1 = corresponding PORTB pin is input 0 = corresponding PORTB pin is output


2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 44

ANSEL and ANSELH Registers

Two registers used to configure I/O to digital

I/Os multiplexed with analog peripherals default to analog on start-up


Analog Select Register (ANSEL)
ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0

Analog Select High Register(ANSELH)


ANS13 ANS12 ANS11 ANS10 ANS9 ANS8

1 = Pin assigned as analog input 0 = Digital I/O

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201ASP

Slide 45

Initializing Digital I/O

Example:

Initializing PORTB for RB<7:4> as inputs and RB<3:0> as outputs

;------------configure PORTB for digital ---------------------------------------banksel PORTB ;Go to bank containing PORTB ;register clrf PORTB ;Clear PORTB banksel ANSELH ;Go to bank containing ANSELH ;register clrf ANSELH ;Set as all digital clrf ANSEL ;-----------Set up direction of each PORTB pin------------------------------banksel TRISB ;Go to bank containing TRISB ;register movlw b11110000 ;Value to set TRISB<7:4> high ;and TRISB<3:0> low move into ;W register movwf TRISB ;Move value in W into TRISB
2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 46

PORTB Interrupt-On-Change

On PIC16F887 all PORTB pins have Interrupt-onChange and Weak Pull-Up options

Weak Pull-Up PORTB PORTB Register (WPUB)(IOCB) Interrupt-On-Change Register


WPUB7 IOCB6 WPUB6 IOCB5 WPUB5 IOCB4 WPUB4 WPUB3 WPUB2 IOCB1 WPUB1 IOCB0 WPUB0 IOCB7 1 ICOB3 1 IOCB2

1 = Pull-up Interrupt-on-change enabled enabled 0 = Pull-up Interrupt-on-change disabled disabled

RB3

HIGH LOW

RB4

Interrupt Control Register (INTCON) GIE PEIE TOIE INTE RBIE TOIF INTF RBIF RBIF

*PORTB must first be read/written and then RBIF can be cleared in software
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Timers

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201ASP

Slide 48

Timers

Timers are used for many functions:


timing reference to generate an event count the number of events waveform generation etc... Timer0 Timer1 Timer2

PIC16F887 has 3 timers


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201ASP

Slide 49

PIC16F887 Timer Comparison TIMER0


SIZE OF REGISTER CLOCK SOURCE (Internal) CLOCK SOURCE (External ) CLOCK SCALING AVAILABLE (Resolution) INTERRUPT EVENT and FLAG LOCATION CAN WAKE PIC FROM SLEEP?
2006 Microchip Technology Incorporated. All Rights Reserved.

TIMER1
16-bits (TMR1H:TMR1L) Fosc/4 T1CKI pin or Timer 1 oscillator (T1OSC) Prescaler 3-bits (1,2,4,8)

TIMER2
8-bits (TMR2) Fosc/4 None

8-bits (TMR0) Fosc/4 T0CKI pin

Prescaler 8-bits (1:21:256)

Prescaler (1:1,1:4,1:8) Postscaler (1:11:16) TMR2 matches PR2 (TMR2F in PIR2) NO

On overflow FFh00h (T0IF in INTCON) NO

On overflow FFFFh0000h (TMR1F in PIR1) YES

201ASP

Slide 50

Timer 0 Block Diagram


DATA BUS
Fosc/4

8
synchronize

T0CKI pin

scaled clock

TMR0

Watchdog Timer

prescaler
PS2 WDT out 0 0 0 1 1 0 0 1 0 1 0 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
Slide 51

PS1

PS0

TMR0 RATE

OPTION register
RBPU INTEDG TOCS TOSE

PSA

PS2

PS1

PS0

0 0

Prescaler Rate Select Bits

Prescaler Assignment 1 0 1 prescaler Source1= Edge Selectassigned to1WDT 1 0 0= Source prescaler assigned to Timer 0 TMR0 1 = Clock increment TMR0 Select on high-to-low transition 1 1 1 1 =0 TOCK1, = increment 0 = Fosc/4 TMR0 on low-to-high transition
2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP

Timer 0 Block Diagram


DATA BUS
Fosc/4

8
synchronize

T0CKI pin

scaled clock

INTCON register TOIF

TMR0

Watchdog Timer

prescaler
WDT out

Timer If TOCK1 used as the clock source, prescaler is first 0 is is readable or writeable from the data bus sampled then synchronized with Writes and will inhibit increment for 2 x the TCYinternal clock TOIF in INTCON register is set with Timer 0 roll-over FFh 00h
2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 52

Timer0 Initialization (Internal Clock Source)


;Make sure the TMR0 register is clear banksel TMR0 clrf TMR0 ; Clear T0IF bcf

TMR0

0 0 0 0 0 0 0 0
INTCON

INTCON,T0IF

0 0 0 0 0 1 0 0 0
T0IF

;Setup the following in the OPTION_REG ;Timer0 increment from internal clock ;with a prescaler of 1:16 banksel OPTION_REG movlw b00000011 movwf OPTION_REG ;The TMR0 interrupt is disabled, do polling ;on the T0IF overflow bit

This interrupt flag will set on Timer0 overflow even if all interrupts are disabled OPTION_REG T0IF = 0?

NO

0 0 0 0 0 0 1 1
TOCS PSA PS<2:0> YES

btfss goto
<continue>

INTCON, T0IF $-1

ASSIGNS SELECTS SELECTS PRESCALER TO 1:16 TIMER0 INTERNAL TIMER0 RATE CLOCK

CONTINUE

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201ASP

Slide 53

Timer1 Block Diagram

T1OSI T1OS0

T1 OSC

TMR1ON

prescaler
Fosc/4

synchronize

T1CKI pin

TMR1H

TMR1L
Enable

Timer1 Control Register (T1CON)


T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON T1CKPS1 1 T1CKPS0 1

scale

LP Oscillator Enable 1 = T1OSC selected 0 = T1CKI can be used


2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP

Clock Source Select 1 0 1 = Enables 1:4 1 = External (T1CKI on risingTimer1 edge) 0 1 1:2 0 = Internal FOSC/4
0 0 1:1
Slide 54

Timer1 1:8 On

Timer1 Block Diagram


T1GINV
T1G COMPARATOR 2 output T1OSI T1OS0
T1 OSC

TMR1GE

TMR1ON synchronize

Determined by Will Timer1 time High T1GSS in CM2CON1 prescaler or Low transitions (comparator 2 control Fosc/4 register 1)
TMR1H

T1CKI pin

TMR1L
Enable

Timer1 Control Register (T1CON)


T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

Timer1 Gate invert Timer1 External Clock Input Synchronization 1 =Timer1 counts gate is HIGH Timer1 Gate when Enable If TMR1ON is 0, ignore TMR1GE 1 = do not synchronize external clock input 0 = Timer1 counts gate is is not LOW 1 = Timer1 is when on if gate active bit 0 = synchronize external clock input 0 = Timer1 is on
2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 55

Timer1 Interrupt TMR1H TMR1L


1 0 1 0 1 0 0 1 1 0 1 0 0 1

Main Code 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 1 0 Start ;Start by clearing the Timer1 interrupt flag banksel PIR1 bcf PIR1, TMR1IF ;Enable Timer1 interrupt banksel PIE1 bsf PIE1, TMR1IE

PIR1
0 1
TMR1IF

OVERFLOWPIE1
1
TMR1IE

;Enable Global and Peripheral Interrupts bsf INTCON, GIE bsf INTCON, PEIE ;
2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP

INTCON
1 1
GIE PEIE
Slide 56

Timer1 Initialization (Internal Clock Source)


;Make sure the TMR1 registers are clear banksel TMR1H clrf TMR1H clrf TMR1L ;Make sure the TMR1IF flag in PIR1 ; is cleared banksel PIR1 bcf PIR1,TMRIF

TMR1H

0 0 0 0 0 0 0 0
TMR1L
TMR1H:TMR1L 0 0 0 0 INCREMENTING 0 0 0 0 OVERFLOW!!

INTCON

0 0 0 0 0 0 0 0
PIR1

;Setup T1CON register for internal clock with ;1:8 prescaler, Timer1 is stopped and T1 osc ;is disabled movlw b00110000 movwf T1CON ;Start Timer1 incrementing bsf T1CON, TMR1ON ;The TMR1 interrupt is disabled, do polling ;on the TMR1IF overflow bit btfss PIR1, TMR1IF goto $-1

0 0 0 0 0 0 0 0 1
PIE1

TMR1IF
TMR1IE

0 0 0 0 0 0 0 0
T1CON

0 0 1 1 0 0 0 1 0
TMR1CSTMR1ON T1SYNC

T1CKPS<1:0>

Scale input clock to 1:8


2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP

Select Synchronize external clock internal clock (Fosc/4) output


Slide 57

Timer 1 Lab (Lab2)

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201ASP

Slide 58

Lab2 Timer 1 Objective of this lab is to become familiar with the operation of Timer1
AND

To gain experience enabling Peripheral Interrupts

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201ASP

Slide 59

Lab2 Overview
Interrupt Vector
Save Context Clear IF Reload Timer1 Toggle LED 0 5th

MAIN Program Initialize PORTB

Initialize Timer1 clock source and pre-scaler: Timer1 interrupts every 100,000 Instruction cycles
Enable Timer1, Global and Peripheral Interrupts NOP Main Loop

Int. ?
YES NO

Toggle LED 3 Restore Context Retfie


2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP

Slide 60

Lab2 Specifics

The code for the lab is in


C:\RTC\201_ASP\Lab2-TMR1

Within lab2.asm complete the following


Set Timer 1 clock source to Fosc/4 Set Timer 1 pre-scaler to 2 Load Timer 1 with 0x3CB0 (65,356 50,000) Start Timer 1 Enable Timer 1, Global and Peripheral Interrupts

2006 Microchip Technology Incorporated. All Rights Reserved.

201ASP

Slide 61

What you need to know Register Operations of INTCON, T1CON, TMR1H, TMR1L and PIE1 With a value of 0x3CB0 and a pre-scaler of 2, Timer1 will overflow every 100,000 cycles The interrupt vector code to toggle the LEDs has been provided

2006 Microchip Technology Incorporated. All Rights Reserved.

201ASP

Slide 62

Lab2 Solution
; ; ********************************************************************************** ; Set code to Select clock source, Set pre-scaler to 2, load hex 3CB0 into Timer1 ; and turn on Timer1 ; ********************************************************************************** movlw (.65536-.50000) / .256 ; initialize TMR1L and TMR1H movwf TMR1H movlw (.65536-.50000) % .256 movwf TMR1L bsf T1CON,T1CKPS0 ; set pre-scaler to 2 bcf T1CON,TMR1CS ; set Clock source to Fosc/4 bsf T1CON,TMR1ON ; turn Timer1 on ; ;************************************************************************************ ; Enable Timer1 interrupts, Peripheral Interrupts and Global Interrupts ;************************************************************************************ ; bsf STATUS,RP0 ; go to bank1 bsf PIE1,TMR1IE bsf INTCON,GIE bsf INTCON,PEIE bcf STATUS,RP0 ; return to bank0
2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 63

Lab2 Questions
Question: Was Timer 1 still running during the time it took to service the Interrupt? Answer: Yes Question: What effect did this have on the value to be placed to reload TMR1L and TMR1H? Answer: Everything to be precise the latency of reloading Timer1 should be considered

2006 Microchip Technology Incorporated. All Rights Reserved.

201ASP

Slide 64

Timer2 Block Diagram


TOUTPS3 0 TOUTPS2 0 TOUTPS1 0 TOUTPS0 0 SCALE 1:1

0
0

0
0 0 1 1 1 1 0

0
1 1 0 0 1 1 0 0 1 1 0 0 1 1

1
0 1 0 1 0 1

Fosc/4

Prescaler 1:1, 1:4, 1:16

TMR2

0 0 0 0 0 1

TMR2 1:3 OUTPUT 1:4


1:5 1:6 1:7 1:8

1:2

COMPARATOR 1 0
1 0 0 1 1 1 1

0 1:9 Postscaler 1 1:10 1:1 1:16 0 1 0 1 0 1 1:11 1:12 1:13 1:14 1:15 1:16

PR2

1 1 1 1 1

Timer2 Control Register (T2CON)


TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

T2CKPS1 0 0 1

T2CKPS2 0 1 X

Scale 1:1 1:4 1:16


201ASP Slide 65

Timer2 ON 1 = Timer2 enabled

2006 Microchip Technology Incorporated. All Rights Reserved.

Timer2 Block Diagram


TMR2 OUTPUT

Fosc/4

Prescaler 1:1, 1:4, 1:16

TMR2 1 1 1 1 0 1 1 0 0 1 1 0 COMPARATOR
Postscaler 1:1 1:16

PR2 1 1 1 1 1 0 0 0
Timer2 Control Register (T2CON)
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

PIR1 1
TMR2IF

2006 Microchip Technology Incorporated. All Rights Reserved.

201ASP

Slide 66

Timer2 Initialization
TOUTPS3 TOUTPS1 ;DisableTOUTPS2 TMR1 interrupts

in TOUTPS0 the PIE1 SCALE ;register that holds the TMR2IE bit. 0 0 flag in PIR1 0 1:1 ;Make sure0 the TMR2IF is cleared banksel 0 0 0PIE1 1 1:2 bcf PIE1, TMR2IE 0 0 1PIR1 0 1:3 banksel bcf PIR1, TMR2IF 0 0 1 1 1:4 ;Setup T2CON register for: ;0 Postscaler 1 = 1:15 0 0 1:5 ; Prescaler = 1:16 0 1 0 1 1:6 ;Timer2 is off movlw b01110010 0 1 1 0 1:7 movwf T2CON ;Make sure1 the TMR21register is 0 1 clear 1:8 banksel TMR2 1 0 0 0 1:9 clrf TMR2 ;Load the PR2 1 0 register 0 with a predetermined 1 1:10 ;value banksel 1 0 1PR2 0 1:11 movlw b10000000 1 0 1 1 1:12 movwf PR2 ;Start Timer2 1 1 incrementing 0 0 1:13 banksel T2CON 1 1 0T2CON, TMR2ON 1 1:14 bsf ;The TMR2 interrupt is disabled, do polling 1 the TMR2IF 1 0 1:15 ;on flag 1 btfss 1 1 1PIR1, TMR2IF 1 1:16 goto $-1

TMR2

INCREMENTING 0TMR2 0 TMR2 0 0 = 0 PR2 0 0 0


PIE1

0
PIR1 TMR2IE

1 0
TMR2IF T2CON

0 1 1 1 0 0 1 1 0
TOUTPS<3:0> T2CKPS<1:0>

Postscaler set to 1:15

TMR2ON

PR2

Timer2 is OFF

Prescaler set to 1:16

1 0 0 0 0 0 0 0
Slide 67

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201ASP

Timer 2 Lab (Lab3)

2006 Microchip Technology Incorporated. All Rights Reserved.

201ASP

Slide 68

Timer 2 Lab

The Goal of Lab3 is to become familiar with the following :


Timer2 Clock Source Pre scaler value Post scaler value Turning on Timer2 Setting all the enable bits needed for Timer2 to successfully generate an interrupt

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201ASP

Slide 69

Lab3 Overview
Interrupt Vector
Save Context

Main Program
Initialize PORT B Set up Timer2 PR2, Pre scaler, Post Scaler, clock source for 10mS

Increment counter the number of times Timer2 has interrupted

Increase the LED count Enable interrupts

Restore context
NOP retfie

2006 Microchip Technology Incorporated. All Rights Reserved.

201ASP

Slide 70

Lab3 Specifics

Code for this lab is in


C:\RTC\201_ASP\Lab3-TMR2

Complete the following sections of code

Set Timer 2 pre-scaler to a value of 4 Set Timer 2 post-scaler to a value of 10 Turn Timer 2 on Configure the GIE, PEIE and Timer 2 Interrupt Enable bit

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201ASP

Slide 71

What you need to know Special Function Registers (SFRs) needed for the lab3 are INTCON , PIE1, PR2 , and T2CON

With PR2 set to 250, the pre-scaler at 4, and the post-scaler at 10, Timer 2 will interrupt at an every 10 ms (about 1/100 second) with a 4Mhz oscillator ( Fosc/4 = 1Mhz)

2006 Microchip Technology Incorporated. All Rights Reserved.

201ASP

Slide 72

Timer 2 Lab Solution


; ;************************************************************************* ; configure Timer2 Prescaler of 4, PR2 of 250 and a postscaler of 13 ; and turn timer2 on. ;************************************************************************* ; banksel 0 ; set bank to 0 movlw b01001000 ; set 10 as postscaler movwf T2CON bsf T2CON,T2CKPS0 ; set prescaler to 4 bsf T2CON,TMR2ON ; turn on Timer2 ;************************************************************************ ; Enable Timer2 interrupts, Peripheral Interrupts and Global Interrupts ;************************************************************************ ; bsf STATUS,RP0 ; go to bank1 bsf PIE1,TMR2IE bsf INTCON,GIE bsf INTCON,PEIE bcf STATUS,RP0 ; return to bank0
2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 73

Lab3 Questions
Question: Like Timer1 does Timer2 keep running during Interrupt latency?

Answer: Yes it does !


Question: Does the user have to account for the free running Timer2 in order to ensure a precise interrupt period?

Answer: No, Interrupt occurs on match not overflow


2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 74

Enhanced Capture/Compare/PWM Module

2006 Microchip Technology Incorporated. All Rights Reserved.

201ASP

Slide 75

ECCP Overview

Capture Capabilities

Times the duration of an event

ECCP MODE Compare

Timer Resource

Triggers a specific event when a determined Capture Timer 1 amount of time has passed

Compare Pulse Width Modulation (PWM) Timer 1 PWM Timer 2 creates reconfigurable, steady duty-cycle, square

wave output at defined frequency Provides enhanced features for various bridge connectivity

* Module interfaces with Timers 1 and 2


2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 76

ECCP Control Registers


CCPxM3 CCPxM2 Enhanced CCP1 CCPxM1 Control

P1M1
0 0 0 0 0

P1M0
0 0 0

CCPxM0(CCP1CON) EECP Mode Selected Register DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0
0 0 1 0 1 0 Capture/Compare/PWM off (resets ECCP module) Unused (reserved) FUNCTION Compare mode, toggle output on match

BIT

CCP1M<3:0> 0 1
0 0 0 1 1 1 1 1 1 1 0 0 0 0

(i) ECCP Mode Select Bits 1 1 Unused (reserved) Configure the of modes including Trigger 0 0 module for variety Capture mode, every falling edge Special Event and edge detection (ii) Output Configuration Bits Capture mode, every 4th rising edge Capture/Compare Modes = notevery used 00 1 1 Capture mode, 16th rising edge Enhanced PWM = Provides Half-Bridge or Full-Bridge output 0 0 Compare mode, set output on match Steering Control 0 1 Compare mode, clear output on match
1 0 1 1 0 1 Capture mode, every rising edge

These bits determine the mode of the module P1M<1:0> i.e. Use Capture, Compare or PWM mode
DC1B<1:0>
1
1 0 cycle 2 LSBs Compare mode, generate software interrupt on match PWM duty (8 MSBs located in CCPR1L) 1 used in Capture Compare mode, trigger special event *Not or Compare modes

1
1

0
0

0
1

PWM mode; P1A, P1C active-high; P1B, P1D active-high


PWM mode; P1A, P1C active-high; P1B, P1D active-low

CCP2CON is similar to CCP1CON without: 1 mode toggle 1 0 PWM P1A, P1C active-low; P1B, P1D active-high i. 1 Compare on output pin inmode; the Mode Select Bits ii. Enhanced PWM configuration capabilities (Output Configuration bits)
1 1 1 1 PWM mode; P1A, P1C active-low; P1B, P1D active-low
2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 77

Capture Mode
Prescaler 1, 4, 16
CCPx
CCPxM3 0 0 CCPxM2 1 1 CCPxM1 CCPxM0

CCPxIF in PIRx

Edge Detect 0 and 0


0 1 0 1

TMR1H TMR1L MODE TMR1L TMR1H


Capture every falling edge Single Buffered Capture every rising edge Capture every 4th rising edge Capture every 16th rising edge

0 1 1 System Clock (Fosc) 0 1 1

CCPRxH CCPRxL

P1M1

P1M0

DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0

CCPxCON

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201ASP

Slide 78

Capture Initialization
;Turn off CCP module banksel CCP1CON clrf CCP1CON ;Make sure Timer1 is off bcf T1CON, TMR1ON ;Clear Timer1 result registers clrf TMR1H clrf TMR1L ;Disable all interrupts for CCP bcf PIR1, CCP1IF banksel PIE1 bcf PIE1, CCP1IE ;Set CCP1 pin for input bsf TRISC, 2 ;Initialize Capture for every 4th rising edge banksel CCP1CON movlw b00000110 movwf CCP1CON ;Start Timer1 incrementing bsf T1CON, TMR1ON ;Test the CCP1IF flag for capture btfss PIR1, CCP1IF goto $-1
2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP

TMR1H

0
TMR1L

th 04 0 Rising 0 INCREMENTING!! 0 0 Edge 0 0 0 TIMER1 Current Timer1 Value

CCPR1H
CCPR1L

Detected!!

Current Timer1 Value


PIR1

0 1
CCP1IF
CCP1CON

1 0

0 1

T1CON

1 0
TMR1ON
Slide 79

Compare Mode
TMR1H TMR1L
CCPxIF in PIRx

COMPARATOR
Does TMR1H:TMR1L = CCPxM3 CCPRxH:CCPRxL CCPxM2 CCPxM1

NO YES CCPxM0
0
1 0

1
1 1

0
0 0

??

OUTPUT MODE LOGIC

CCPx

0
0 1

Set output on match (CCPxIF is set)


Clear output on match (CCPxIF is set) Generate software interrupt on match (CCPxIF is set CCP1 pin unaffected)

CCPRxH
1
P1M1 P1M0

CCPRxL

0
DC1B1

Trigger special event Special Event Trigger (CCPxIF is set, CCP1 resets TMR1 or 1 1 TMR2 and starts an A/D conversion if enabled) DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0

2006 Microchip Technology Incorporated. All Rights Reserved.

201ASP

Slide 80

Compare Initialization
;Turn off the CCP module banksel CCP1CON clrf CCP1CON ;Turn off Timer1 bcf T1CON, TMR1ON ;Clear Timer1 result registers clrf TMR1H clrf TMR1L ;Disable CCP1 interrupt and make sure ;its flag is clear banksel PIE1 bcf PIE1, CCP1IE banksel PIR1 bcf PIR1, CCP1IF ;Make CCP1 pin output banksel TRISC bcf TRISC, 2 ;Initialize Compare to set output on match banksel CCP1CON movlw b00001000 movwf CCP1CON ;Load half of Timer1 full scale value into ;CCPR1H:CCPR1L banksel CCPR1H movlw b10000000 movwf CCPR1H clrf CCPR1L ;Start Timer1 incrementing bsf T1CON, TMR1ON ;Test CCP1IF for Timer1 match with CCPRx btfss PIR1, CCP1IF goto $-1
2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP

TMR1H

TMR1L TMR1H:TMR1L = 1000 0000 0000 0000 0 0 0 INCREMENTING!! 0 0 0 0 0 TIMER1 (CCPR1H:CCPR1L Value) CCPR1H

1 0

0 0

0 0

0 0

0 0

0 0

0 0

0 0

CCPR1L

T1CON

0 1
TMR1ON
CCP1CON

0
PIR1

1 0

0 1
CCP1IF
Slide 81

PWM Mode

Generates a Pulse-Width Modulated (PWM) signal on the CCPx pin Duty cycle, period and resolution determined by the following registers

PR2 T2CON CCPRxL CCPxCON

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201ASP

Slide 82

PWM Block Diagram


DCxB<1:0> DUTY CYCLE VALUE CCPRxL

DOUBLE BUFFER

10

CCPx OUTPUT

CCPRxH
10

LATCH

TMR2 = CCPRxH COMPARATOR 10


TMR2 incrementing
(1)

R
Latch

8 COMPARATOR TMR2 = PR2

CCPx pin

8
PR2
2006 Microchip Technology Incorporated. All Rights Reserved.

Note 1: TMR2 is concatenated with the 2-bit FOSC, or 2-bits from Prescaler to create 10-bit time base
201ASP Slide 83

Setup for PWM Operation


;Turn off CCPx pin by setting TRISC bit HIGH banksel TRISC bsf TRISC, 2 ;Clear Timer2 banksel TMR2 clrf TMR2 ;Set up Period and Duty Cycle using an 8MHz oscillator movlw b01111111 ; movwf PR2 ;Load a 64uS Period Value movlw b00011111 ; movwf CCPR1L ;Load Duty Cycle Value ; (25%) of PWM period

TMR2

0 0 0 0
PR2

0 0 0 0

0 1 1 1 1 1 1 1
CCPR1L

0 0 0 1 1 1 1 1
CCP1CON

0 0 1 0 1 1 0 0
duty cycle LSBs DC1B<1:0> PWM Mode CCP1M <3:0>

;Configure ECCP module for single PWM ; with P1A active HIGH and ;LSBs of Duty Cycle are 10 movlw b00101100 ; movwf CCP1CON ;ECCP module is configured ;for PWM and Duty Cycle ;LSBs loaded ;Turn CCPx pin back on banksel TRISC bcf TRISC, 2 ;Make CCP1 output ;Timer2 starts when TMR2ON is set beginning PWM movlw b00000100 ;incrementing movwf T2CON ;Prescaler and Postscaler ;are both 1:1
2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP

T2CON

0 0 0

0 0 1 0 0
Prescaler bits T2CKPS<1:0>
TMR2ON

Prescaler bits TOUTPS<3:0>

Slide 84

Pulse Width Modulation (PWM) Lab4

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201ASP

Slide 85

PWM Lab4

Objective of this Lab is to become familiar with the ECCP module configuration and operation in PWM mode AND

To gain additional exposure to Timer2 configuration

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201ASP

Slide 86

PWM Lab4 Overview

The PWM waveform is output on the CCP1 pin (RC2) that will emit a tone on the APP001 on board buzzer. When the lab is completed, a 50% duty cycle at a period of 256/(Fosc/4) will drive the buzzer (3.8KHz)

2006 Microchip Technology Incorporated. All Rights Reserved.

201ASP

Slide 87

PWM Lab4 Overview


Main Code
Load PR2 value

Set up RC2 as output pin

Load CCPR1L for 50% duty cycle

Configure CCP as 8-bit PWM Turn on Timer2 w/ 1:1 pre scaler

NOP

2006 Microchip Technology Incorporated. All Rights Reserved.

201ASP

Slide 88

Lab4 Specifics

Code for the lab is in C:\RTC\201_ASP\Lab4-PWM Complete the following sections

Configure PORTC pin 2 ( CCP1) as an output Set CCP in PWM mode Clear DCB1 and DCB0 (8-bit PWM) Configure Timer2 with 1:1 pre-scaler

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201ASP

Slide 89

What you need to know

The code to load PR2 (Timer2) and to set a 50% duty cycle has been provided. These values can be seen in the code The CCP1 pin is RC2 (Pin 2 of PORTC) on the PIC16F887 Registers needed to complete this lab are TRISC, T2CON, and CCP1CON

2006 Microchip Technology Incorporated. All Rights Reserved.

201ASP

Slide 90

Lab4 Solution
;***************************************************************** ; Set CCPx as an output ;***************************************************************** bcf TRISC,2 ; set CCP1 pin as output pin ; ; set duty cycle for 50% ; bcf STATUS,RP0 ; go to bank 0 movlw 0x80 movwf CCPR1L ; set duty cycle ;***************************************************************** ; Put CCP1 module in PWM mode. ; Configure CCP to clear DCB1 and DCB0 ( 8-bit PWM) ;***************************************************************** movlw 0x0C movwf CCP1CON ;***************************************************************** ; Configure Timer2 Pre and post scale of 1:1 ; and turn Timer2 on ;***************************************************************** bsf T2CON,TMR2ON ; turn on Timer2
2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 91

Lab4 Questions
Question: Why didnt we have to enable the interrupts for the PWM to work? Answer: PWM will run concurrently with the PICmicro MCU without slowing the processor down

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201ASP

Slide 92

Output Compare Lab

(Lab5)

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201ASP

Slide 93

Output Compare Lab5

Goals of the lab are to gain experience with the following:


Setting up the ECCP for Output Compare Configure the Special Event Flag to reset Timer1 Configure the ECCP to generate an Interrupt on Timer1 overflow Using an Interrupt Vector to modify the interval between Interrupts

2006 Microchip Technology Incorporated. All Rights Reserved.

201ASP

Slide 94

Lab5 Overview
Interrupt Vector
Save Context
Clear IF Toggle CCP Output Pin Decrement CCPR1L

Main Program
Configure CCP as Output Compare Initialize Timer1

Initialize PORT C
Turn on timer1

NOP

RETFIE

2006 Microchip Technology Incorporated. All Rights Reserved.

201ASP

Slide 95

CCP Lab5 Specifics

The code for the is in C:\RTC\201_ASP\Lab5-CCP Complete the following sections:


Configure the CCP as an Output Compare that sets the Special Event Flag and CCP1IF Configure Timer1 with a clock source of Fosc/4 and a pre-scaler of 1:8 Enable all Special Function Registers need to allow the CCP interrupt to occur
201ASP Slide 96

2006 Microchip Technology Incorporated. All Rights Reserved.

What you need to know

The registers needed to complete this lab are


INTCON, T1CON, CCP1CON.

The Interrupt Vector has been provided The Value of CCPR1L will rollover from 0 to 0xFF and continue to decrement

2006 Microchip Technology Incorporated. All Rights Reserved.

201ASP

Slide 97

CCP Lab5 Solution


; ; Set CCP1COM to Output Compare mode with Special Event Trigger ; to clear the Timer 1 register pair on a match ;******************************************************************** movlw 0x0B movwf CCP1CON ; set value in CCP1CON ; ; Configure Timer 1 for Fosc/4 operation. 8:1 Pre-scaler ; ;******************************************************************* movlw 0x30 movwf T1CON ;

; ; Enable Timer 1 interrupts, Peripheral Interrupts and Global Interrupts ; ;******************************************************************** bsf PIE1,CCP1IE bsf INTCON,GIE bsf INTCON,PEIE

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201ASP

Slide 98

Lab5 Question
Question: The PWM did not require an interrupt in order to work. Do we need an interrupt to operate in output compare mode? Answer: Not necessarily

We did require an interrupt in this Lab because our task on an Output Compare was not one of the options

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201ASP

Slide 99

Comparators

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201ASP

Slide 100

Comparator Overview

Comparator Module:

Compares analog input voltage to a reference and outputs a digital result PIC16F887 has 2 Comparators (C1 and C2)
Vref
Analog Input (Vin) Reference Voltage (Vref)

Vin
Output (Vout) Comp

Vout

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201ASP

Slide 101

Comparator Module Registers

Each comparator (C1 and C2) has its own control register

CM1CON0 and CM2CON0 Comparator 2 additionally has CM2CON1 for interface with Timer1 CMxCON0 registers control the following

Enable Input selection Reference selection Output selection Output polarity


201ASP Slide 102

2006 Microchip Technology Incorporated. All Rights Reserved.

Simplified Comparator Block Diagram


CxCH1 CxCH0 0 0
CHANNEL

CxON C12IN0 C12IN1

0 1

C12IN0C12IN2-

0 1 C12IN11 = OUTPUT INVERTED

C12IN2
C12IN3 CxIN+ CxVref

_
comparator

C12IN3-

+
CxR = 0 CxR = 1

CxOE

CxOUT pin

CxOUT
CxR CxPOL

CxON

CxOUT

CxOE

CxPOL

---

CxR

CxCH1

CxCH2

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201ASP

Slide 103

Comparator Module Register CM2CON1


MC1OUT MC2OUT C1RSEL C2RSEL ----T1GSS C2SYNC

BIT
MC1OUT MC2OUT C1RSEL C2RSEL T1GSS Mirror copy of C1OUT bit Mirror copy of C2OUT bit

FUNCTION

simultaneous read of both comparators

1 = CVREF routed to C1VREF input of comparator C1 0 = 0.6V absolute voltage reference is routed to C1VREF 1 = CVREF routed to C2VREF input of comparator C2 0 = 0.6V absolute voltage reference is routed to C2VREF 0 = Timer1 will increment on comparator output, 1 = Timer gate will increment with source on external pin 1 = comparator 2 output is synchronized to falling edge of Timer1 clock 0 = comparator output is asynchronous

C2SYNC

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201ASP

Slide 104

Comparator Interrupts

Comparator interrupt flags (C1IF/C2IF in PIR2 register)


Set with any change on associated comparator C1IE/C2IE in PIE2, PEIE and GIE in INTCON must be set Interrupt flags must be cleared in software to enable further comparator interrupts

Must read comparator to clear flags before clearing C1IF or C2IF.

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201ASP

Slide 105

Comparators and Sleep Mode


Comparators remain active in Sleep if enabled prior to Sleep instruction Change on comparator output will wake-up PICmicro C1IE/C2IE (PIE2) and PEIE (INTCON) must be enabled

Next instruction following SLEEP instruction is executed on wake-up or the ISR (Interrupts enabled) Enable GIE (INTCON) to perform an ISR instead

Any reset turns comparators off returning all registers to default


201ASP Slide 106

2006 Microchip Technology Incorporated. All Rights Reserved.

Comparator Voltage Reference

Voltage Reference Module:


Independent from Comparator operation VRR VRSS = 1 8R R R R R FVREN Provides two 16-level voltage ranges VRSS = 0 Sleep Output clamped to Vss HFINTOSC V 8R 15 enable EN FixedRef 0.6V a ratio of Vdd CV Provides Fixed Voltage To Comparators V To Comparators Reference and ADC Module and ADC Module Fixed reference (0.6V) 0 VRSS = 1
VREF+
DD REF REF-

CVREF VROE

4 VR<3:0>
VRSS = 0

VREN

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201ASP

Slide 107

Voltage Reference Control Register (VRCON)


VREN VROE VRR VRSS VR3 VR2 VR1 VR0

BIT

FUNCTION

Comparator1 Vref enable, 1 = enabled If VREN VRR = 1 or Low Range is selected: Comparator2 Vref enable 1 = CVref voltage level is also output on the RA2/AN2/V /C2IN+ CVref = (VR<3:0>/24) x Vdd VROE pin
REF

0 = CVref voltage is disconnected from the RA2/AN2/VREF/C2IN+ pin


CVref Range Selection or VRR 1 = Low Range 0 = High Range

If VRSS VRR = 0 or High Range is selected CVref = Vdd/4 + (VR<3:0>/32) x Vdd VR<3:0> CVref Value Selection bits
2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 108

Range Select Bit 1 = Comparator reference source, CVrsrc = (Vref+) (Vref-) 0 = Comparator reference source, CVrsrc = Vdd - Vss

Analog-to-Digital Converter (ADC)

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201ASP

Slide 109

ADC Overview

Analog-to-Digital Converter Module


Converts analog input signal into 8 or 10-bit binary value Selectable internal or external reference voltage Interrupt can be generated after conversion is completed Interrupt can be used to wake the PICmicro from SLEEP

ADC Analog Input Signal


2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP

ADC Output
Slide 110

ADC Registers

The ADC implements two control registers

ADCON0 and ADCON1


ADCS2 CHS3 CHS2 CHS1 CHS0
GO/DONE ADON

ADCON0 ADCS1

BIT
ADCSx bits

FUNCTION
A/D Conversion Clock Select bits 00 = Fosc/2, 01 = Fosc/8, 10 = Fosc/32, 11 = FRC (Internal Oscillator)

CHSx bits Analog Channel Select bits GO/DONE 1 = A/D Conversion in progress 0 = A/D Conversion is completed ADON Enables the ADC module

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201ASP

Slide 111

ADC Registers
ADCON1 ADFM --VCFG1 VCFG0 -------

---

BIT
ADFM

FUNCTION
Result registers justification bit 1 = Right Justified, 0 = Left Justified

VCFG1
VCFG0

Negative voltage reference 1 = external source on Vref- pin, 0 = Vss


Positive voltage reference 1 = external source on Vref+ pin, 0 = Vdd

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201ASP

Slide 112

ADC Registers

Following conversion, ADC result in is placed into two result registers ADRESH and ADRESL 10-bit ADC result can either be Left or Right Justified
Left Justified
MSB

LSB

10-bit Result

Right Justified
MSB

LSB
10-bit Result

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201ASP

Slide 113

A/D Module Diagram


CHS3 CHS2 CHS1 CHS0 CHANNEL
ADCS2

0
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12

Fosc
0 0 0 0 0 0 1 1 1 1 1 1

0 0 Conversion 0 0 clock scaler 0 1


0 1 1 1 1 0 0 1 0 0 1 1 0

0
1 0 1 0 0

ADCS1 0 0 1

AN0
AN1 0 AN2 1
0 AN3

Vref+ Conversion Clockpin Fosc/2 Fosc/8 Fosc/32

1 AN4

1 Vref+ 1 ADC 0 0 1 0 1

AN5 AN6 AN7 AN8

FRC Vdd (dedicated Internal Oscillator)

0 Vref- 1

AN9 ADRESH AN10 AN11 AN12 AN13

ADRESL

AN13

0 1 Holding Capacitor 0 1 1 1 0 0
GO/DONE

ADCON0
ADCS1 ADCS2 CHS3 CHS2 CHS1

Vrefpin

CHS0

ADON

Vss

2006 Microchip Technology Incorporated. All Rights Reserved.

201ASP

Slide 114

A/D Module Diagram


VCFG0 = 0 1
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 ADRESH ADRESL Vdd Vref+ pin

Fosc

Conversion clock scaler

Vref+

ADC

Holding Capacitor

AN13

VCFG1 = 0 1
ADCON1
ADFM 0 1 VCFG1 VCFG0

Vrefpin

Vss

2006 Microchip Technology Incorporated. All Rights Reserved.

201ASP

Slide 115

Timing Considerations for ADC

When an A-to-D channel is selected time must be taken for the holding capacitor to charge All 10 bit conversion take 11 cycles to complete

User must select the appropriate ADC clocking based on the system clock frequency
201ASP Slide 116

2006 Microchip Technology Incorporated. All Rights Reserved.

Analog-to-Digital Conversion LAB (Lab6)

2006 Microchip Technology Incorporated. All Rights Reserved.

201ASP

Slide 117

Analog-to-Digital Converter lab6

This Lab will familiarize you with the following:

Setting up the ADC module Operating a Peripheral from the main program and not an interrupt vector Using the value read from one peripheral (ADC) and using it to drive another Peripheral (ECCP in PWM mode)

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201ASP

Slide 118

ADC lab6 Overview


Main Program
Configure Timer 2 Configure PORT C Configure CCP for PWM

Configure and Turn on ADC

Disable interrupts
Continued on next page
2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 119

Lab6 Overview ( cont.) Main Loop


Continued from Previous Page

Start ADC

ADC done? YES Put ADC value in PR2 & CCPR1L Output ADC value to LEDs NO

2006 Microchip Technology Incorporated. All Rights Reserved.

201ASP

Slide 120

Lab6 Specifics

Complete the following sections of code in the project C:\RTC\201_ASP\Lab6-ADC

Configure the ADC to return a left Justified value into ADRESH Set Tad to Tosc*8 Turn on ADC unit Complete the code to start an ADC and wait for the conversion to finish in the main control loop

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201ASP

Slide 121

What you need to know

This lab does not do the ADC conversion in an interrupt routine. This lab uses a polling method.

Writing the value of the ADC conversion into CCPR1L will change the duty cycle of the buzzer
ADCON1 and ADCON0 special function registers are used to complete this lab
201ASP Slide 122

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ADC Lab6 Solution


;******************************************************************************** ; Configure ADC , Channel 0, left justified, Tad=8 * Tosc, turn on ADC ;********************************************************************************

clrf bsf bsf bsf movlw movwf

ADCON0 ADCON0,ADCS0 ADCON0,ADON STATUS,RP0 0x0E ADCON1

; esnure default Channel is set to channel 0 ; set Tad = 8 Tosc ; turn on ADC unit ; go to bank1 ; Left Justify and set configuration

; ; Enable Timer 2 interrupts, Peripheral Interrupts and Global Interrupts ; bcf INTCON,PEIE bcf STATUS,RP0 ; return to bank 0 loop ; ;********************************************************************************* ; add three lines of code to start the ADC conversion and wait for the conversion ; to complete ;********************************************************************************

bsf btfsc goto

ADCON0,GO ADCON0,GO $-1

; start A-to-D conversion on channel 0 ; Is the conversion done? ; No: Check again

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201ASP

Slide 123

ADC Lab6 Question


Question: Instead of waiting for AD Done bit to be set in the main program, could we start the ADC from within an interrupt routing? Answer: YES

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201ASP

Slide 124

ENHANCED Universal Synchronous Asynchronous Receiver Transmitter (EUSART)

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201ASP

Slide 125

EUSART Overview

Serial I/O communications peripheral

Sometimes called Serial Communications Interface or SCI Can be synchronous or asynchronous Can receive and transmit

Main Functions:

Full-duplex asynchronous transmit and receive Half-duplex synchronous master and slave

Most common use

RS-232 communications to a PC serial port

Needs driver for RS-232 level shifter

Enhanced features allow interface with a Local Interconnect Network (LIN) bus system
201ASP Slide 126

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EUSART Registers

There are several registers used with the EUSART

Baud rate generator registers:

SPBRG and SPBRGH

Transmit status and control (TXSTA) Receive status and control (RCSTA) Receive and transmit data registers

Transmit data register (TXREG) Receive data register (RCREG)

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201ASP

Slide 127

TXSTA Register
CSRC TX9 TXEN SYNC SENB BRGH TRMT TX9D

Bit CSRC

Function Clock Source Select 1 = Master Mode (clock generated internally from BRG) 0 = Slave Mode (clock from external source) Ninth bit transmission enable 1 = Transmit enabled EUSART Mode , 1 = Synchronous Mode, 0 = Asynchronous Mode 1 = Send sync break character bit 0 = Sync break transmission is completed Baud Rate Select, 1 = High Speed, 0 = Low Speed 1 = Transmit Shift Register (TSR) is empty, 0 = TSR is full Indicates when last bit is shifted out Ninth bit of transmit data
201ASP Slide 128

TX9 TXEN SYNC SENB BRGH TRMT TX9D


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RCSTA Register
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D

Bit SPEN

Function Serial Port Enable


1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset)

RX9
SREN CREN ADDEN FERR OERR RX9D
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1 = Enable 9-bit data reception, 0 = 8-bit data


Synchronous mode Master, 1 = enable, 0 = disable single receive Continuous Receive Enable 1 = enables address bit detection (enable interrupt and load the receive buffer when RSR<9> is set 1 = framing error occurred (Stop bit not detected) 1 = Overrun error occurred (FIFO was still full when other data was loaded) Ninth bit of received data
201ASP Slide 129

Baud Rate Control Register (BAUDCTL)


ABDOVF RCIDL
Bit ABDOVF

----

SCKP

BRG16
Function

----

WUE

ABDEN

Auto-Baud Detect Overflow bit (Asynchronous mode only) 1 = Auto-baud timer has overflowed Receiver Idle Flag, 1 = Receiver is idle, 0 = Start bit has been received and the receiver is receiving Synchronous Clock Polarity bit Asynchronous mode: 1 = transmit inverted data to the RB7/TX/CK pin Synchronous mode: 1 = data is clocked on rising edge of the clock 0 = data is clocked on falling edge of the clock 16-bit Baud Rate Generator bit 1 = selects 16-bit BRG, 0 = selects 8-bit BRG Wake-Up Enable bit (Asynchronous Mode only) Auto-Baud Rate Detect Enable bit, 1 = enabled In SLEEP, detects when 9th bit is set
201ASP Slide 130

RCIDL SCKP

BRG16 WUE ABDEN


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Baud Rate Formulas


Configuration bits
SYNC BRG16 (TXSTA) (BAUDCTL) 0 0 0 0 BRGH (TXSTA) 0 1

BRG/EUSART Mode
8-bit/Asynchronous 8-bit/Asynchronous

Baud Rate Formula


Fosc/[64 (n+1)] Fosc/[16 (n+1)]

0
0 1

1
1 0

0
1 X

16-bit/Asynchronous
16-bit/Synchronous 8-bit/Synchronous Fosc/[4 (n+1)]

16-bit/Synchronous

*n = value of SPBRGH:SPBRG register pair


2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 131

Transmit Block Diagram

DATA BUS

TXIE

TXREG
TXIF

Interrupt

Set TXIF Clear TXIF


TXEN
MSB LSB

Pin Buffer and Control SPEN

Transmit Shift Register (TSR) Baud Rate Generator TX9D TX9

TX/DT pin

Enables Serial Port


TRMT

Ninth data bit

Clear TMRT bit Set TRMT bit TSR has data it Indicates shiftin register is empty

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201ASP

Slide 132

Receive Block Diagram


Enable Serial Port
SPEN

RX/DT pin

Receive Shift Register (RSR) Pin Buffer and Control Data Recovery
RX9
STOP START

Baud Rate Generator

FIFO

Clear Set RCIF flag


RCIE

RCREG
RCIF
RX9D

Interrupt

Data Bus

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201ASP

Slide 133

EUSART Receive & Transmit LAB (Lab7)

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201ASP

Slide 134

EUSART lab7

This Lab will familiarize you with the following:

Setting up the EUSART module with 9600,N,8,1


Operating receiver of EUSART in the interrupt service routine from the RS-232 Main program is waiting the receiving flag for send out the data through EUSART

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201ASP

Slide 135

USART lab7 Overview


Main Program
Configure EUSART Configure PORT C RxD_FG=0

Configure LEDs

Enable RxD interrupts

Send Data Out

RxD_FG=1 NO

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201ASP

Slide 136

Lab7 Overview ( cont.)

Receive Interrupt
Interrupt Routine

Get RxD to RxD_Buffer YES Output RxD value to LEDs

RCIF = 0

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201ASP

Slide 137

Lab7 Specifics

Complete the following sections of code in the project C:\RTC\201_ASP\Lab7-EUSART

Configure the USART for the Asynchronous Mode


9600 bps, None Parity Check, 8-bit Data, 1 Stop bit 4MHz/16/(25+1) =9615 bps , SPBRG = 25

Set PORTC for TxD & RxD Set PORTD for LEDs output Turn on USART module Received a data through RS-232 in interrupt routine then send out the data through main program
201ASP Slide 138

2006 Microchip Technology Incorporated. All Rights Reserved.

What you need to know Receiver use the interrupt method for the realtime receiving instead of the polling method. Use a real-time flag to inform main program Setting the RS-232 communication protocol Using the Hyper-Terminal on COMx of PC
201ASP Slide 139

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USART Lab7 Solution


;*********************************************************************** ;**** Initial USART as 9600,N,8,1 ;*********************************************************************** Init_USART banksel BAUDCTL ; Bank 3 movlw b'00000000' ; disable Auto-Baud Detect, TxD is RC6, BRG = 8-bit movwf BAUDCTL banksel movlw movwf ; movlw movwf .25 SPBRG ; ### Set baud rate at 9600 with High Speed mode ; ### System Clock are 4MHz using internal RC TXSTA b'00100100' TXSTA ; ### Bank 1 ; ### 8-bit data mode , ASYNC ; ### High Speed mode, Enable TxD

bcf bsf
bsf bcf banksel movlw movwf ; bcf bcf ; bsf bsf

PIE1,TXIE PIE1,RCIE
TRISC,7 TRISC,6 0 b'10010000' RCSTA PIR1,TXIF PIR1,RCIF

; ### Disable TxD interrupt ; ### Enable RxD interrupt


; ### set input for RC7, RxD receiving pin ; ### set output for RC6, TxD pin

; ### Enable Serial Port, 8-bit receive ; ### Continuous Receive, Disable Address Detection ; Clear TxD interrupt flag; ; Clear RxD interrupt flag

INTCON,PEIE INTCON,GIE
201ASP Slide 140

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USART Lab7 Question


Question: Send the transmitter data in the main program, could we send the data through an interrupt routing? Answer: YES

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201ASP

Slide 141

MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE

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201ASP

Slide 142

Overview

The MSSP module can operate in one of two modes:


Serial Peripheral Interface (SPI) Inter-Integrated Circuit(I2CTM)


Full Master mode Slave mode (with general address call).

The I2C interface supports the following modes in hardware:


Master mode Multi-Master mode Slave mode.

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201ASP

Slide 143

I2C Conditions

Conditions :

START (S) STOP (P)

SDA SCL
SDA pulled released LOW while SCL is still HIGH

Recipient Stop SDA condition goes does LOW quickly not drive during followed SDA th clock by a9Start LOW condition pulse of SCL

ACKNOWLEDGE (A)
RESTART (R) NEGATIVE or NOT-ACKNOWLEDGE (N)
201ASP Slide 144

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External IC EEPROM Read MASTER

+5V

SCL

SDA
READ WRITE STOP GOTO DATA MODE ADDRESS
BUSY BUSY

PIC

LISTEN
EEPROM SLAVE START RESTART MEMORY STOP ACK NACK ADDRESS ADDRESS

LISTEN

LISTEN
EEPROM

SLAVES

ACK DATA

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201ASP

Slide 145

MSSP Control Registers

There are 3 associated control registers


1.

MSSP Status Register (SSPSTAT)


SMP CKE D/A P S R/W UA BF

CONTROL BITS

DETECTION BITS (FLAGS)

BIT SMP CKE D/A P S R/W UA BF

FUNCTION Slew Rate Control bit Not used in I2C mode Last byte Rx/Tx was data or address Stop Condition Detected Start Condition Detected Slave :READ/WRITE or Master = transmit in progress Address needs to be updated The SSPBUF register is full

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201ASP

Slide 146

MSSP Control Registers


SSPM3 0 0 0 0 0 0 0 SSPM2 0 0 0 1 1 SSPM1 SSPM0 Mode

2.

0 Control 0 SPI Master mode, clock = FOSC/4 MSSP 0Register 0 1 SPI Master mode, clock = FOSC/16 1 (SSPCON) 1 0 SPI Master mode, clock = FOSC/64 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 1 0 1 1 1 0 0 1 0 1 0 1 0 1 SPI Master mode, clock = TMR2 output/2 SPI Slave mode, clock = SCK pin, SS pin control disabled, FUNCTION SS can be used as I/O pin I2C Slave mode, 7-bit address Write Collision Detected I2C Master mode, clock = FOSC / (4 * (SSPADD+1)) Reserved Reserved Reserved Reserved

CONTROL BITS SPI Slave mode, ERROR DETECTION BITS (FLAGS) 0 0 clock = SCK pin, SS pin control enabled

BIT

1 WCOL

0
1 1 1 1 1 1 1 1

1 SSPOV

1
0 0 1 1 0 0 1 1

Slave mode, 10-bit address A1 write to I2C the SSPBUF before previous value processed

SSPEN
0

Enables MSSP module Enables clock

CKP 0
0 SSPM3 1 SSPM2 1 1 1

I2C firmware controlled Master mode (Slave idle) Mode Select Bit

SSPM1 SSPM0

Mode Select bits


201ASP Slide 147

I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled

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MSSP Control Registers


3.
GCEN

MSSP Control Register 2 (SSPCON2)


ACKSTAT ACKDT
CONTROL BITS

ACKEN

RCEN

PEN

RSEN

SEN

DETECTION BITS (FLAGS)

BIT GCEN

FUNCTION Generates an interrupt when a call is received (slave mode)

ACKSTAT
ACKDT ACKEN RCEN PEN RSEN SEN

0 = Acknowledge received from slave (transmit mode)


0 = ACK 1 = NACK (receive mode) Initiate ACK/NACK condition (Transmits ACKDT bit) Enables receive mode Initiates a STOP condition Initiates a RESTART condition Initates a Initiates a START START condition condition

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201ASP

Slide 148

Registers Associated with I2C


4.

MSSP Receive/Transmit Buffer (SSPBUF)

Holds the data to be transmitted or the data that has been received by the MSSP module When full, the BF (Buffer Full) bit in the SSPSTAT register is set Any write to the SSPBUF register during transmission/reception of data will be ignored, and the write collision detect bit WCOL of the SSPCON register will be set

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201ASP

Slide 149

Registers Associated with I2C


5.

Serial Port Address (SSPADD):

Slave mode:

contains the slave address of the PIC Compared against the received value Used to calculate the clock speed (BAUD rate) of the I2C system.

Master mode:

BAUD RATE =

Fosc 4 ( SPADD 1)

*NOTE: FOSC is the frequency of the oscillator not the Instruction Clock TCY
2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 150

MSSP Interrupts

The SSPIF interrupt flag is set in the PIR1 register with the following events

START condition STOP condition Data transfer byte transmitted/received Acknowledge transmit RESTART condition
SSP interrupts will only occur if the SSPIE in the PIE1 register is enabled as well as the GIE and PEIE in the INTCON.

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201ASP

Slide 151

MSSP Module I2C Lab (Lab8)

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201ASP

Slide 152

EUSART Lab 8

This Lab will familiarize you with the following:

Setting the MSSP module as 7-bit I2C Master mode with 100KHz bus rate Know the I2C command and step by step
Read the I2C temperature sensor TC74 then show on LEDs

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201ASP

Slide 153

TC74 Command
Read Temperature I2C command for the TC74-A7
s TC74 Addr 1001111 Wr Ack Read Temp. Command 00000000 Ack S TC74 Addr 1001111 Rd Ack Temp. Data 00010011 NAck P

TC74 Package

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201ASP

Slide 154

Lab8 Specifics

Complete the following sections of code in the project C:\RTC\201_ASP\Lab8-I2C

Configure the MSSP for the 7-bit I2C Master Mode Set both SCL & SDA pin are input mode Send a Read Temperature command to read current temperature from TC74-A7 Show the temperature result on the LEDs

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201ASP

Slide 155

What you need to know The read temperature command is similar the Random Read a byte data from I2C EEPROM Check the SSPIF for each step machine Who will return the Ack/NAck signal Bus Collision interrupt bit (BCLIF) handling
201ASP Slide 156

2006 Microchip Technology Incorporated. All Rights Reserved.

USART Lab8 Solution


Init_I2C_Master BANKSEL TRISC bsf SCL nop bsf SDA ; BANKSEL 0 movlw b'00101000' movwf SSPCON ; banksel SSPADD movlw .9 movwf SSPADD ; movlw b'10000000' movwf SSPSTAT ; movlw b'00000000' movwf SSPCON2 ; return ; Initial PortC,bit 3 & 4 as Input ; RC3 = SCL , RC4 = SDA

; ### I2C Master Mode, Clock Rate: FOSC/(4*SSPADD+1) ; ###

; ### This gives 100KHz I2C clock @ 4MHz ; ### (4MHz/4) / (9+1)= 100KHz ; ### Disable slew rate control, ; ### and clear status bits ; Set SCL,SDA into Ready status

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201ASP

Slide 157

Appendix A. Multiple Interrupt Lab 9

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201ASP

Slide 158

Lab 9 on Multiple Interrupts

This Lab involves:

Dealing with 2 ( or more) concurrent interrupts


Determining the source of an interrupt Deciding which interrupt request will be serviced first

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201ASP

Slide 159

Lab 9 Overview Main Program


Set up CCP as Output Compare just as in Lab 5 Enable Timer1 and PORTC as In Lab 5 Setup PORTB and enable INT0 interrupts on Sw2as in Lab 1 NOP

Continued on next slide

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201ASP

Slide 160

Lab 9 Overview
INT0_ISR Call debounce Delay routine CCP_ISR Clear IF Put -2 in WREG Toggle variable Called push_flag

push_fla g Set ?

yes

Clear IF

Put 0 in WREG

retfie

Add WREG to CCPR1L retfie

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201ASP

Slide 161

Lab 9 Overview (cont.)


Save context

Interrupt Handler
NO

Did CCP generate the interrupt ?

YES

Did INT0 generate the interrupt ?

Go to CCP service routing

YES
Service INT0

NO
retfie
Slide 162

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201ASP

Lab 9 Specifics

Lab is found in:

C:\RTC\201_ASP\Lab9-MXINT

The two interrupt Service routine are provided


(INT0_ISR and CCP_ISR)

Complete the following sections of code


When an interrupt occurs, determine the cause and transfer control to the appropriate ISR Set the SFRs to enable INT0 and CCP1 Interrupt to occur
201ASP Slide 163

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What you need to know for Lab

INTCON, and PIR Special Function Registers are used in this lab

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201ASP

Slide 164

Lab 9 Solution
Vector Parsing Section

NT_VECTOR CODE 0x004 ; interrupt vector location ; ; Save Wreg, STATUS, and PCLATH during Interrupt Service ; call save_regs; btfsc goto btfsc goto ; INTCON,INTF INT0_ISR PIR1,CCP1IF CCP_ISR ; ### test for INT0 interrupt ; ### test for CCP Interrupt request

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201ASP

Slide 165

Lab 9 Questions
Question: Why is there a noticeable silence shortly when SW2 is released? Answer: Since debounce is called during an interrupt and the GIE bit is cleared, the CCP1 interrupt that toggles the buzzer is not allowed to operate. Therefore, the buzzer goes quiet

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201ASP

Slide 166

Lab 9 Questions (cont.) Question: How can this silence be eliminated and the buzzer continue to run ? Answers: 1. Capture SW2 in the main and call debounce while GIE is set 2. User a timer to accomplish the delay 3. Re-enable interrupts during the INT0 interrupt service
2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 167

Lab 9 Questions (cont.)


Question: Which of these three methods is better?

Answer: It depends !!

Each has their own advantages and disadvantages

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201ASP

Slide 168

Appendix B. Lab10 Access Internal EEPROM Project Name : Lab10-EEPROM.mcp Content in the Lab10

Defined the EEPROM data in the program Write a byte data to the EEPROM Read a byte data feom EEPROM

Request to use the MPLAB SIM for this project Open EEPROM window in the view manual

2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 169

Appendix C. Lab11 LCD Display Module

Provided the LCD routine for the LCD Module of APP001 Use the global & extern directive instruction for LCD routine access

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201ASP

Slide 170

201ASP Wrap-Up

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201ASP

Slide 171

201ASP Wrap-up

Today we covered the following peripherals on the Mid-Range family

I/O ports Interrupt structure and processing Timers (timer0, timer1, timer2) ECCP ( Output Compare, Input Capture, PWM) Comparators and Analog-to-Digital Converters

Voltage Reference

EUSART Serial Port I2C using the MSSP module


201ASP Slide 172

2006 Microchip Technology Incorporated. All Rights Reserved.

Final Word

This discussion has followed standard MCHP datasheet flow:


Overview of peripheral Use these sections to: Develop logic flow charts or pseudo-code (Avoid Spaghetti Programming!!) Other Tips: Comment your code thoroughly Choose descriptive names for user defined registers

Register Description and Configuration Enhanced or Special Features

*Packaging and Electrical Specifications are at the end of the datasheet


2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 173

Resources

Visit www.microchip.com and follow the links for:

24/7 technical support Application Notes Web Seminars Code examples Datasheets and Much More!

Visit www.microchip.com.tw for the Tradition Chinese technical forum

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201ASP

Slide 174

Thank You!!

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201ASP

Slide 175