EFFICIENT DESIGN & IMPLEMENTATION OF

COMPACT CORE AES

Guided By: Mr. B Srinivas Sr. Asst Professor, E&C Dept, Aditya Engineering College

Shashi Ranjan 10A91D5510 M.Tech,Embedded System Aditya Engineering College

CONTENTS
ABSTRACT INTRODUCTION PROBLEM STATEMENT LITERATURE SURVEY EXISTING SYSTEM

STEPS IN AES ALGORITHM IMPLEMENTATION

PROPOSED COMPACT AES CORE ADVANTAGES AND DISADVANTAGE

TOOLS USED
RESULTS REFERENCES
COMPACT AES CORE 2

ABSTRACT
This project presents an Advanced Encryption Standard

(AES) Algorithm For Field Programmable Gate Array

(FPGA).
We have designed an efficient and compact, iterative

architecture with input and key, both of 128 bits.

The aim is to provide encryption /decryption core for

small size and low cost applications.

COMPACT AES CORE

What is Encryption?
Transform information such that its true meaning is

hidden
Requires special knowledge to retrieve the information

Examples: AES, DES .

COMPACT AES CORE

Symmetric Cipher Model

COMPACT AES CORE

INTRODUCTION
AES is a symmetric block cipher algorithm and can process data blocks of 128

bits, using cipher keys with lengths of 128,192, and 256 bits. AES algorithm has four basic transformations: SubBytes, ShiftRows, MixColumns, and AddRoundKey. Initial Round: Key is XORed with plane text.

Where:
Nb Number of columns in the State Nk Number of 32-bit words in the Key Nr Number of rounds (function of Nb and Nk)
COMPACT AES CORE 6

PROBLEM STATEMENT
The main objective is to reduce the power consumption,

hardware complexity and area. The large area of AES with sixteen S-box architectures may not be suitable for practical low-end embedded applications, such as smart cards, PDAs, cell phones, and other mobile devices. These small embedded applications do not require high speed or throughput, but are area critical

COMPACT AES CORE

LITERATURE SURVEY
1.Yang Xiao, Hsiao-Hwa Chen, Bo Sun, Ruhai Wang, Sakshi Sethi, MAC Security and Security Overhead Analysis in the IEEE 802.15.4 Wireless Sensor Networks, EURASIP Journal on Wireless Communications and Networking, May 2006.

Highlights
Goals of cryptography Confidentiality

Authenticity Integrity Security attacks Passive attacks Passive attacks 2. Cheng Wang and Howard M. Heys Using a Pipelined S-Box in Compact AES Hardware Implementations This AES core implementation is called as FOLDED AES.
This AES core consists of 128-bit data block is divided into four 32-bit data blocks and each block is processed independently.

COMPACT AES CORE

3. An Efficient Design of Security Accelerator for Wireless Senor Networks .Ohyoung Song and Jiho Kim School of Electrical and Electronic Engineering, Chung-Ang University,221, HukSuk-Dong, DongJak-Gu, Seoul, KoreaI.EEE CCNC 2010 proceedings Block-wide AES core Compact AES core 4. FIPS 197, Advanced Encryption Standard (AES), November 26, 2001 http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf Block-wide AES structure and the steps involved in AES algorithm.

COMPACT AES CORE

AES Structure

COMPACT AES CORE

10

EXISTING SYSTEM

COMPACT AES CORE

11

Pseudo Code for encryption

COMPACT AES CORE

12

Substitute Bytes
Uses one table of 16x16 bytes containing a permutation of all 256

8-bit values Each byte of state is replaced by byte indexed by row (left 4-bits) & column (right 4-bits) Eg: byte {95} is replaced by byte in row 9 column 5 which has value {2A}

COMPACT AES CORE

13

Substitute Bytes(cont)

COMPACT AES CORE

14

Substitute Bytes Example

COMPACT AES CORE

15

Shift Rows
1st row is unchanged 2nd row does 1 byte circular shift to left 3rd row does 2 byte circular shift to left 4th row does 3 byte circular shift to left

COMPACT AES CORE

16

Shift Rows(cont)

COMPACT AES CORE

17

Mix Columns
Each byte is replaced by a value dependent on all 4 bytes in the column Multiplication by 2 in GF(28) takes some work:

.. If multiplying by a value 0x80 shift left by 1 and XOR with 0x1b

COMPACT AES CORE

18

Mix Columns

COMPACT AES CORE

19

Mix Columns Example

COMPACT AES CORE

20

Add Round Key

In the AddRoundKey () transformation, a Round Key is added

to the State by a simple bitwise XOR operation

COMPACT AES CORE

21

AES Key Expansion

The AES algorithm takes the Cipher Key(K), and performs a

Key Expansion routine to generate a key schedule.

The Key Expansion generates a total of Nb (Nr + 1) words

COMPACT AES CORE

22

AES Key Expansion: Pseudo Code

COMPACT AES CORE

23

AES Key Expansion

COMPACT AES CORE

24

Rcon Constants

COMPACT AES CORE

25

AES Key Expansion:Example

COMPACT AES CORE

26

Example(cont)

COMPACT AES CORE

27

AES encryption:example

COMPACT AES CORE

28

Example(cont)

COMPACT AES CORE

29

AES Decryption

COMPACT AES CORE

30

Pseudo Code for decryption

COMPACT AES CORE

31

InvShiftRows() Transformation

COMPACT AES CORE

32

InvSubBytes() Transformation

COMPACT AES CORE

33

InvMixColumns() Transformation

b1 = (b1 * E) XOR (b2*B) XOR (b3*D) XOR (b4*9) b2 = (b1 * 9) XOR (b2*E) XOR (b3*B) XOR (b4*D) b3 = (b1 * D) XOR (b2*9) XOR (b3*E) XOR (b4*B) b4 = (b1 * B) XOR (b2*D) XOR (b3*9) XOR (b4*E)

COMPACT AES CORE

34

PROPOSED COMPACT AES CORE

COMPACT AES CORE

35

REQUIREMENTS
Five 4:1 MUX ONE S-box

Four 32-bit registers

Four 8-bit registers One 32-bit mix column One addroundkey operation(xor)

COMPACT AES CORE

36

AES DECRYPTION

COMPACT AES CORE

37

ADVANTAGES
LOW COST SMALLER AREA

DISADVANTAGE
LOW SPEED

COMPACT AES CORE

38

TOOLS USED
Software: Step by step simulation: Matlab Simulation & Synthesis results Xilinx ISE Hardware: Spartan 3E

COMPACT AES CORE

39

MATLAB OUTPUT: ENCRYPTION

Plaintext[127:0]: 32 43 f6 a8 88 5a 30 8d 31 31 98 a2 e0 37 07 34; Keygive [127:0] : 2b 7e 15 16 28 ae d2 a6 ab f7 15 88 09 cf 4f 3c;

COMPACT AES CORE

40

ENCRYPTION OUTPUT

COMPACT AES CORE

41

Device Utilization for Encryption

Compact AES core encryption

Block-wide AES encryption

COMPACT AES CORE

42

Timing analysis for encryption

Delay of compact AES core for encryption

Delay of block-wide AES for encryption

COMPACT AES CORE

43

MATLAB OUTPUT: DECRYPTION

Plaintext[127:0]: de 52 29 4e 5d 09 66 79 1a bf 06 15 30 4e 83 bc; Keygive [127:0] : 2b 7e 15 16 28 ae d2 a6 ab f7 15 88 09 cf 4f 3c;

COMPACT AES CORE

44

DECRYPTION OUTPUT

COMPACT AES CORE

45

Device Utilization for Decryption

Compact AES core decryption

Block-wide AES decryption

COMPACT AES CORE

46

Timing analysis for Decryption

Delay of compact AES core for Decryption

Delay of block-wide AES for encryption

COMPACT AES CORE

47

CONCLUSION
By using proposed compact low cost AES design we can

reduce the logic usage by reducing the AES S-Boxes which occupies much area. Although the new circuit has a small size, but the speed of this implementation is also reduced.

COMPACT AES CORE

48

REFERENCE
1. An Efficient Design of Security Accelerator for Wireless Senor Networks .Ohyoung Song and Jiho Kim School of Electrical and Electronic Engineering, Chung-Ang University,221, HukSuk-Dong, DongJak-Gu, Seoul, KoreaI.EEE CCNC 2010 proceedings 2. H. Yang Xiao, Hsiao-Hwa Chen, Bo Sun, Ruhai Wang, Sakshi Sethi, MAC Security and Security Overhead Analysis in the IEEE 802.15.4 Wireless Sensor Networks, EURASIP Journal on Wireless Communications and Networking, May 2006. 3. Song J. Park, Analysis of AES hardware Implementations, available at http://islab.oregonstate.edu/koc/ece679/project/2003/park.pdf 4. Satoh A., Morioka S., Takano K., Munetoh S., A Compact Rijndael Hardware Architecture with S-Box Optimization, Theory and Application of Cryptology and Information Security (ASIACRYPT 2001), Gold Coast, Australia, 2001 5. Standaert F.X., Rouvroy G., Quisquater J.J., Legat J.D., A methodology to implement block ciphers in reconfigurable hardware and its application to fast and compact AES RIJNDAEL, International Symposium on Field-Programmable Gate Arrays (FPGA) 6. W. Stallings, The Advanced Encryption Standard,CRYPTOLOGIA, Volume XXVI No. 3, July 2002, pp. 165-186.
COMPACT AES CORE

49

THANK YOU

50