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Chapter 11

Logic Gate Circuitry

Basic Logic Families


TTL transistor-transistor logic based on bipolar transistors. CMOS complementary metal-oxide semiconductor logic based on metaloxide-semiconductor field effect transistors (MOSFETs). ECL emitter coupled logic based on bipolar transistors.
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General Characteristics of Basic Logic Families


CMOS consumes very little power, has excellent noise immunity, and is used with a wide range of voltages. TTL can drive more current and uses more power than CMOS. ECL is fast, with poor noise immunity and high power consumption.
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Logic Subfamilies
Both TTL and CMOS are available in a wide range of subfamilies. In subfamilies, the part designations for identical logic functions remain the same, but the electrical characteristics are different.
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Examples of TTL Subfamilies


Part Number 74LS00 TTL 74ALS00 74F00 Advanced low-power Schottky Fast TTL Logic Family Low-power Schottky TTL

Examples of CMOS Subfamilies


Part Number 74HC00 CMOS 74HCT00 74VX00 High-speed CMOS TTL compatible Low-voltage CMOS Logic Family High speed CMOS

Input/Output Voltage and Current Definitions


Values for any gate are designated with two subscripts:
The first subscript indicates an input or output value The second subscript indicates the logic level
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Input/Output Voltage Designations


VOL the logic LOW output voltage. VOH the logic HIGH output voltage. VIL the logic LOW input voltage. VIH the logic HIGH input voltage.

Input/Output Voltage Designations

Input/Output Current Designations


IOL the logic LOW output current. IOH the logic HIGH output current. IIL the logic LOW input current. IIH the logic HIGH input current.

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Input/Output Current Designations

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Part Designation
Typically 54XXYY or 74XXYY. 54 series is manufactured to military specifications. 74 series is manufactured to commercial specifications. XX is the subfamily designation. YY is the part designation.
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Data Sheets
Use the appropriate maximum or minimum parameters in design. Typical values should be considered information only. Refer to Figure 11.3 in the textbook.

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Propagation Delay
The time required for the output of a digital circuit to change states after a change at one or more of its inputs. Largely due to charging and discharging of capacitances inherent in the gate or flip-flop switching transistors.
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Propagation Delay Definitions


tpHL is the propagation delay when the device output changes from HIGH to LOW. tpLH is the propagation delay when the device output changes from LOW to HIGH.
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Propagation Delay Definitions

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Propagation Delay Definitions

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Propagation Delay Factors


Varies with operating conditions. Particularly affected by temperature and the power supply voltage.

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Propagation Delay of 74XX00 Gates


tpLH tpHL 74F00* 6nS 5.3nS 74AS00 4.5nS 4nS 74ALS00 11nS 8nS 74HC00** 74HCT00*** 15nS 22nS 15nS 22nS

* Temperature range (74F00): 0OC to 70OC. **VCC = 4.5V, TEMPERATURE RANGE (74HC00): -55OC TO 25OC. ***VCC = 5.5V, TEMPERATURE RANGE (74HCT00): 25 C.
O

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Propagation Delay in Logic Circuits


Sum of the delays in the input-to-output paths. Delays that do not affect the circuit output are ignored.

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Propagation Delay in Logic Circuits

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Input Data to Clock Timing


Setup time (tsu) the time required for the synchronous inputs of a flip-flop to be stable before the clock active edge. Hold time (th) the time that the synchronous inputs of a flip-flop must remain stable after the clock active edge.
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Input Data to Clock Timing

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Clock Timing Requirement 1


Pulse width (tw) is the minimum time required for an active-level pulse applied to a CLK, CLR, or PRE input. Values are measured from the midpoint of the leading edge of the pulse to the midpoint of the trailing edge.
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Clock Timing Requirement 1

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Clock Timing Requirement 2


Recovery time (trec) is the time from the midpoint of the trailing edge of a pulse to the midpoint of an active edge CLK edge (See Table 11.4 in the textbook). For a flip-flop, the propagation delay due to the clock is defined as the delay measured from the active edge of the clock to a corresponding change in Q.
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Clock Timing Requirement 3

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Fanout
The number of gates that a logic gate is capable of driving without possible logic error. Limited by the maximum current a gate can supply in a given logic state versus the current requirements of the load.
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Fanout Definitions
Driving gate is the gate whose output supplies current to the inputs of other gates. Load gate is a gate whose input current is supplied by the output of another gate.
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Fanout Definitions

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Current Output Definitions


Sourcing means that the current flows out of the terminal. Sinking means that the current flows into the terminal.

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Current Output Definitions

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Driving Gate Fanout


May be different for sourcing and sinking.

IOL nL IIL IOH nH IIH

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Fanout Example for 74LS00


IOL = 8 mA IIL = 0.4 mA nL = 20 IOH = 0.4 mA IIH = 20 A nH = 20
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Current Designations
Sourcing currents are designated as negative. Sinking currents are designated as positive. Sign is disregarded in fanout calculations.
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Exceeding Fanout
Output voltage VOL increases with increasing sink current. Output voltage VOH decreases with increasing source current. A greater load in either state takes the output voltage further away from its nominal value.

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Power Dissipation
The measure of energy used over time by electronic logic gates. The product of the voltage and current required for the operation of the circuit.

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Power Dissipation in TTL Devices


PD = VCCICC. VCC = power supply voltage. ICC = current used. In general, ICC = (ICCH + ICCL)/2.

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Power Dissipation in TTL Devices

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ICCL and ICCH


ICCL is the current drawn from the supply when all outputs are LOW. ICCH the current drawn form from the supply when all outputs are HIGH.

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Power Dissipation in CMOS Devices


PD = VCCIT. VCC = power supply voltage. IT = quiescent + dynamic supply current.

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CMOS Quiescent vs. Dynamic Current


Quiescent current flows when the gate is in a steady state and is usually small. Dynamic current flows when the gate is changing state. The faster a CMOS gate switches, the more current (and the more power) it requires. 42

Power Dissipation of TTL vs. CMOS


Power dissipation in TTL is independent of frequency. Power dissipation in CMOS is dependent on frequency. In slow circuits (< 1 MHz), CMOS is generally superior.
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Noise
Unwanted electrical signals. Induced by electromagnetic fields by such sources as motors, fluorescent lights, high-frequency circuits, and cosmic rays. Can cause erroneous operation of a digital circuit.
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Noise Margin
A certain amount of tolerance is built into digital devices to tolerate noise. Noise margin is required for both LOW and HIGH inputs (See Figure 11.15 in the textbook).

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Noise Margin for 74LS04


HIGH state: VNH = VOH VIH = 3.0 V 2.0 V VNH = 1.0 V. LOW state: VNL = VIL VOL = 0.8 V 0.5 V VNL = 0.3 V.
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Noise Margin for 74HC00A


HIGH state: VNH = VOH VIH = 3.98 V 3.15 V VNH = 0.63 V. LOW state: VNL = VIL VOL = 1.35 V 0.26 V VNL = 1.09 V.
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Interfacing TTL and CMOS


An extension of fanout and noise margin calculations. Requires knowledge of input and output voltages and currents for the gates in question. Refer to Table 11.5 in the textbook.
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High-Speed CMOS Driving 74LS


In general, the 74HC family satisfies the input voltage requirements of the 74LS family. In general, the 74HC family can drive the 74LS family directly, with a fanout of 10.
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74LS Driving 74HC


In general, the 74LS family satisfies the LOW-state criterion, but cannot guarantee sufficient output voltage in the HIGH state. Requires a pull-up resistor on the output to ensure sufficient HIGH-state voltage at the 74HC input.
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74LS Driving 74HCT


The 74HCT family has been designed to be compatible with TTL outputs. The 74LS family can drive the 74HCT family directly.

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74LS Driving 74HCT

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74LS Driving Low-Voltage CMOS


Low-voltage CMOS families, such as 74LVX and 74LCX, can interface directly with TTL outputs using 3.0-V to 3.3-V power supplies. TTL outputs using a 5.0-V power supply must be buffered to translate the TTL level down to an appropriate value.
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74LS Driving Low-Voltage CMOS

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TTL Gates Internal Circuitry


Uses the bipolar junction transistor. The transistors used are in one of two modes: cutoff or saturation. In cutoff mode, the transistor acts as an open switch. In saturation, the transistor acts as a closed switch. 55

TTL Gates Internal Circuitry

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Bipolar Transistor Characteristics


IC V CE V BE Cutoff 0 Open cct. <0.6 V Active

I B

Saturation

I B

>0.8 V 0.6 V - 0.7 V

0.2 V - 0.7 V

0.7v

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Open-Collector Outputs
A circuit that has LOW-state output circuitry, but no HIGH-state output circuitry. Requires an external pull-up resistor to enable the output to produce a HIGHstate.
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Advantages of Open-Collector Outputs


Allows the outputs of multiple gates to be directly connected.
Called wired-AND.

Can produce voltage levels in excess of 5 V. Can drive high-input current devices.
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Advantages of Open-Collector Outputs

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Open-Collector Applications
Wired-AND the outputs of logic gates are wired together. The wired-AND logical equivalent of combining the outputs in an AND function.

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Open-Collector Applications

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Open-Collector Applications

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TTL Inputs
LOW inputs allow current to flow from the gate VCC to the input. HIGH inputs cause current to flow to the phase splitter transistor. Open (floating) inputs act as a logic HIGH, but are unstable and vulnerable to noise. 64

Totem Pole Outputs


The standard TTL output configuration with a HIGH output and a LOW output transistor, only one of which is active at any time. A phase splitter transistor controls which transistor is active.
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Totem Pole Outputs

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Advantages of Totem Pole Configuration


Changes state faster than opencollector outputs. No external components are required.

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Totem Pole Switching Noise


Caused by one output transistor turning off slower than the other turns on. Briefly shorts VCC to ground. Prevented with use of decoupling capacitors.

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Decoupling Capacitors
Usually about 0.1 F placed between VCC and ground on the chips to be decoupled. Acts as a low-impedance path to ground for high frequency noise. Usually require one per chip.
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Decoupling Capacitors

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Decoupling Capacitors

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Decoupling Capacitors

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Connecting Totem Pole Outputs


Outputs must never be connected together. Connecting outputs causes excessively high currents to flow. Outputs will eventually be damaged.
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Connecting Totem Pole Outputs

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Tristate Outputs
A configuration where there are three possible output states: logic HIGH, logic LOW, and a high-impedance state (Z). Created with circuitry to cut off both totem pole output transistors.

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Tristate Inverter Truth Table


G 0 0 1 1 A 0 1 0 1 Y Hi-Z Hi-Z 1 0

G
0 0 1 1

A 0 1 0 1

Y 1 0 Hi-Z Hi-Z

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Other Basic TTL Gates


NOR gates require an individual transistor for each input. AND and OR gates are based on NAND and NOR gates and require an extra inverter stage.

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MOSFET Types
Depletion-mode. Enhancement-mode:
n-channel p-channel

CMOS (complementary) constructed from both n- and p-channel transistors.


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MOSFET Types

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MOSFET BIAS Requirements


Operates in two modes: Cutoff acts as a very high impedance between the drain and the source. Ohmic equivalent of saturation. Acts like a relatively low resistance between the drain and the source.
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MOSFET BIAS Requirements

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MOSFET BIAS Requirements

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CMOS Inverter
Depends on the biasing of the complementary transistors Q1 and Q2. Q1 and Q2 are always in opposite states. When Q1 is ON, Q2 is OFF.
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CMOS Inverter

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CMOS Transmission Gate


Behaves like an analog switch. Conducts in both directions. Used to enable or inhibit time-varying analog signals.
When CONTROL = 1, conduction occurs When CONTROL = 0, conduction is inhibited

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CMOS Transmission Gate

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Schottky Family TTL


Uses a Schottky barrier diode to create a Schottky transistor. Allows transistors to avoid deep saturation and to switch faster. Uses less power than standard TTL.
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Speed-Power Product
One measure of logic circuit efficiency. Uses worst-case values of propagation delay and power dissipation per gate. Expressed in picojoules (pJ). See Table 11.15 in the textbook.
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CMOS Logic Families


Metal-Gate CMOS (rarely used). High-Speed CMOS. Advanced High-Speed CMOS. Low-Voltage CMOS. See Table 11.16 in the textbook.
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