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# Error Detection/Correction

Section 1.7 Section 3.9 Bonus Material: Hamming Code

ASCII Code

Format effector: control layout .Communication Control Characters: frame a text message.

ASCII Examples • ASCII A=1000001 • ASCII T=1010100 .

ASCII Code 1011001 (Y) 1001110 (N) If the probability of a bit flipping event is 1%. what is the likely hood that 4 bits are flipped simultaneously? .

.Parity Bit • ASCII characters are stored one per byte (8 bits) • The leftmost bit is called the parity bit • A parity bit is an extra bit included with a message to make the total number of 1’s either even or odd.

Examples of Parity Bit • Even Parity – ASCII A=01000001 – ASCII T=11010100 • Odd Parity – ASCII A=11000001 – ASCII T=01010100 .

Signal Transmission Algorithm • (Even Parity System) • A parity bit is generated and attached to the raw data • An eight-bit sequence including the parity bit are sent. . • The parity of each character is checked at the receiving end. then at least one bit has changed value during transmission. • If the parity of the received character is not even. The sender must retransmit the signal.

(Truth Table) .Parity Generator • The circuit that generates the parity bit in the transmitter is called a parity generator.

Parity Checker • The Circuit that checks the parity in the receiver is called a parity checker. .

Limitation of Parity Checking (1) (1) .

Hardware implementation • Review of two-terminal XOR/XNOR • Three terminal XOR/XNOR • Hardware Implementation .

Two-terminal XOR • x ⊕ 𝑦 = 𝑥𝑦 ′ + 𝑥 ′ 𝑦 – Equal to 1 if x and y differ in value – Alternative description: equal to 1 if an odd number of variables equal to 1 – Characteristics: • x ⊕ 0 = 𝑥 • x ⊕ 𝑦 ′ = 𝑥𝑦 ′ + 𝑥 ′ 𝑦 ′ = 𝑥𝑦 ′ ′ 𝑥 ′ 𝑦 = 𝑥 ′ + 𝑦 𝑥 + 𝑦 ′ = 𝑥 ′ 𝑦 ′ + 𝑥𝑦 ′ .

Gate Level Implementation of XOR x ⊕ 𝑦 = 𝑥𝑦 ′ + 𝑥 ′ 𝑦 .

Alternative Implementation of XOR • x ⊕ 𝑦 = 𝑥𝑦 ′ + 𝑥 ′ 𝑦 = 𝑥 ′ 𝑥 + 𝑦 ′ 𝑥 + 𝑥 ′ 𝑦 + 𝑦 ′ 𝑦 • 𝑥 𝑥 ′ + 𝑦 ′ + 𝑥 ′ + 𝑦 ′ 𝑦 = 𝑥 𝑥𝑦 ′ + 𝑦(𝑥𝑦)′ • (A’B’)’=A+B .

(Truth Table) .Parity Generator • The circuit that generates the parity bit in the transmitter is called a parity generator.

Three-Terminal XOR • 𝐴 ⊕ B ⊕ 𝐶 equal to 1 if there is an odd number of variables equal to 1 .

Four-Input Odd Function .

the same circuit can be used as a 3-bit even parity generator. if P=0. .Parity Error Check 𝐶 = 𝑥 ⊕ y ⊕z ⊕P Since z ⊕ 0 = 𝑧.

Error Correction • Hamming Code • Use check bits to correct error .

bit 3) 000 001 010 011 100 101 110 111 . bit 2.Raw Data Notation: (bit 1.

bit 5. bit 4. bit 6) CC0C00 CC0C01 CC0C10 CC0C11 CC1C00 CC1C01 CC1C10 CC1C11 . bit 3.Add Check Bits Notation: (bit 1. bit 2.

Check bit 1= Bit 3 ⊕ 𝐵𝑖𝑡 5 .Generate the First Check Bit 0C0C00 0C0C01 1C0C10 1C0C11 1C1C00 1C1C01 0C1C10 0C1C11 Check bit 1 looks at bit 3 and bit 5.

Generate the Second Check Bit 000C00 010C01 100C10 110C11 111C00 101C01 011C10 001C11 Check bit 2 looks at bit 3 and bit 6. Check bit 2= Bit 3 ⊕ 𝐵𝑖𝑡 6 .

Check bit 4= Bit 5 ⊕ 𝐵𝑖𝑡 6 .Generate the third Check Bit 000000 010101 100110 110011 111000 101101 011110 001011 Check bit 4 looks at bit 6 and bit 5.

Hamming Code 000000 010101 100110 110011 111000 101101 011110 001011 Blue: Check bits Black: Data bits .

Problem! • The bad bit is 2+4=6! . we get 111001 instead. • Expected check bit 1:1 ⊕ 0 = 1. OK • Expected check bit 2:1 ⊕ 1 = 0. Problem! • Expected check bit 4:0 ⊕ 1 = 0.Error in a Data Bit • Data Bit: 100 • 111000 • Error occurs in the 6th bit.

Problem! • Expected check bit 2:1 ⊕ 0 = 1. • Expected check bit 1:1 ⊕ 0 = 1. OK • Expected check bit 4:0 ⊕ 0 = 0. we get 011000 instead.Error in the Check Bit • Data Bit: 100. . Check Bit: 110 • 111000 (No error) • Error occurs in the 1th bit. OK • The bad bit is bit number 1.