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# 강의노트 09 Logic Design with ASM Charts

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Based on Digital Systems Design Using VHDL, Chapter 5, by Charles H. Roth, Jr.
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ASM Charts
• Three equivalent terms
 State Machine (SM) chart  State Machine Flowchart  Algorithmic State Machine (ASM) chart

• Advantages of ASM charts over FSM
 Easier to understand the operation of a system  Can be converted into several equivalent forms, and each forms lead directly to a HW realization

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ASM Chart components
• Three principal components:
 State box: contains
• state name or code • output list (or RTL Statements)

 Decision box (Condition check box): contains condition  Conditional output box: contains conditional output list (or RTL Statements)

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ASM Chart blocks
• An ASM chart is constructed from ASM blocks. • Each ASM block contains exactly one state box, together with other boxes. • An ASM block has one entrance path and one or more exit paths. • Each SM block describes the system within one state. • A path through the entrance to exit is link path.

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Equivalent ASM Chart blocks
• A given ASM block can be drawn in several forms.

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then the link paths with dashed lines are active. 6 . • Parallel form and Serial form can be equivalent.Equivalent ASM Chart blocks – cont. • If X1=X2=1 and X3=0.

Incorrect correct 7 .ASM block construction rule • For every valid combination of inputs. • No internal feedback within an ASM block is allowed. there must be exactly one exit path.

ASM Chart example Could we replace this with a conditional output object? Is there any difference in operation? 8 .

the state will transit to either T2. T3 or T4. An ASM chart considers the entire block as one unit.Clock in an ASM block • The operations within a ASM block are executed with a common clock pulse while the system is in a single state T1. This is the major difference from a flow chart. • At the next clock. 9 .

• The equivalent ASM chart has three blocks(for each states).Conversion of an FSM to an ASM chart • The FSM in the example has both Mealy and Moore outputs. 10 . • The Mealy outputs are placed in conditional output boxes.

M=1) after addition after shift (skip add: M=0) 1101 011011011 001101101 1101 100111101 010011110 M after shift (add multiplicand. M=1) after addition after shift (add multiplicand.Example 1: Design of a binary multiplier • A multiplier for unsigned binary numbers • Requires:     A 4-bit multiplicand register A 4-bit multiplier register A 4-bit full adder An 8-bit register for the product (Accumulator) Multiplicand Multiplier 1101 (13) 1011 (11) 1101 1101 100111 0000 100111 1101 10001111 (143) Initial contents of register 0 0 0 0 0 1 0 1 1 (11) (add multiplicand. M=1) after addition after shift 001001111 1101 100011111 0 1 0 0 0 1 1 1 1 (143) 11 .

Example 1: Continued • This type of multiplier is called serial-parallel multiplier. Initial contents of register 0 0 0 0 0 1 0 1 1 (11) (add multiplicand. after shift (add multiplicand. M=1) after addition after shift (add multiplicand. but the addition takes place in parallel) • The lower four bits in the accumulator is initially used for storing multiplicand. M=1) after addition after shift 001001111 1101 100011111 0 1 0 0 0 1 1 1 1 (143) 12 . M=1) after addition after shift (skip add: M=0) 1101 011011011 001101101 1101 100111101 010011110 Shift the contents of the register to the right each time. (multiplier bits are processed serially.

• Inputs  St (Start)  M  K (# of shifts=4) • Output signals:     Load Sh (Shift) Ad (Add) Done 13 . • A external counter is needed for counting the number of shifts.Example 1: Continued • ASM Chart for the control unit.

 CASE statement for each state.Example 1: Continued • Conversion of an ASM chart to a VHDL code is straightforward.  Condition box corresponds to an IF statement. 14 .

the sum P obtained on the first roll is referred to as a point.  On the second or subsequent roll of the dice. and P must roll again. and loses if the sum is 7.Example 2: Dice Game • Rule: (There are 2 dice to roll. P wins if the sum equals the point. Otherwise. 15 .)  After the first roll of the dice. the player (P) wins if the sum is 7 or 11. Otherwise. or 12. P loses if the sum is 2. P must roll again until finally wins or loses. 3.

Store sum Flowchart 16 . the dice counters count at a high speed.Example 2: Dice Game . and the game proceeds.  when released.continued • Reset: to initiate a new game • Rb (Roll button):  if Rb is pushed. the values in the two counters are displayed.

Example 2: Dice Game .continued • Corresponding ASM chart • Input:  Rb  Reset • Conditions:  D7  D711 (Sum is 7 or 11)  D2312  Eq (Sum = Point) • Outputs:  Roll  Sp (Sum to be stored)  Win  Lose 17 .

elsif Sum = 2 or Sum = 3 or Sum =12 then Nextstate <= 3. architecture DiceBehave of DiceGame is signal State. signal Sp: bit. end if.Example 2: Dice Game – VHDL code (1/2) entity DiceGame is port (Rb. elsif Sum = 7 or Sum = 11 then Nextstate <= 2. Roll. Lose: out bit). Sum. Reset. Nextstate: integer range 0 to 5. Sum: in integer range 2 to 12. else Sp <= '1'.bit_pack. library BITLIB. case State is when 0 => if Rb = '1' then Nextstate <= 1. Roll <= '0'. Win. signal Point: integer range 2 to 12. Reset. 18 . when 1 => if Rb = '1' then Roll <= '1'. begin process(Rb. end if.all. State) begin Sp <= '0'. use BITLIB. CLK: in bit. end DiceGame. Win <= '0'. Nextstate <= 4. Lose <= '0'.

end process. when 3 => Lose <= '1'. if Sp = '1' then Point <= Sum. if Reset = '1' then Nextstate <= 0. when 4 => if Rb = '1' then Nextstate <= 5. elsif Sum = 7 then Nextstate <= 3. if Reset = '1' then Nextstate <= 0. end if. end if. end process.Example 2: Dice Game – VHDL code (2/2) when 2 => Win <= '1'. end case. end if. end if. process(CLK) begin if rising_edge(CLK) then State <= Nextstate. elsif Sum = Point then Nextstate <= 2. end if. end DiceBehave. 19 . else Nextstate <= 4. when 5 => if Rb = '1' then Roll <= '1'. end if.

When the DiceGame responds with a Roll signal. such as reading out from a predefined array of numbers. 20 . 1. etc. Verify the result with proper display techniques using REPORT or ASSERT. which represents the sum of the two dice. use a simple method. 4. For the generation of Sum. generate a Reset signal and start again. Initially supply the Rb signal. If no Win or Lose signal is generated by the DiceGame.Lab 7: TB for Dice Game • Draw an ASM chart for a testbench “GameTest” with the following operations. When a Win or Lose signal is detected. supply a Sum signal. 2. repeat steps 1 and 2 to roll again. Realize with a VHDL code. Performs simulation. 3.

강의노트 09 Design of Complex Sequential Logics 21 .

Contents • Manual state machine design  How to design state machines for complex synchronous sequential digital logic circuits • “Automatic” state machine design  How to convert algorithmic descriptions into HDL code that can be synthesized into working circuits  The general form of the circuit that will be synthesized from an algorithmic HDL description 22 .

all RTL statements execute concurrently • Permits systematic conversion from algorithms to H/W • Variation of State Machine Method  Algorithmic State Machine (ASM) Method • Uses a graphical notation referred to as an ASM chart 23 .State Machine Design • Used for systematic design of synchronous sequential digital logic circuits • Modification of FSM Method  FSM (Finite State Machine) method insufficient  FSM method only suitable for small sequential circuits with small numbers of external inputs • Allow more complicated checks for state transitions • Uses RTL statements within the states  Within one state.

 Effectively computable: The computing agent has ability to carry out each operation.Algorithms • Formal definition of an “algorithm”  A general step-by-step procedure for solving a problem that is CORRECT and TERMINATES.  Finite time: Each operation takes finite time and there will be a finite number of steps.  Unambiguous: Each operation is clearly understood by all intended computing agents. • Properties of an algorithm  Well-ordered: There is a clear order in which to do the operations. • Informal definition of an “algorithm”  A computer-program-like procedure for solving the problem given. • Algorithm description methods  Old (outdated) method: flowchart  Pseudocode: free-form procedural description 24 .

Structure of General Synchronous Sequential Circuit 25 .

General template for synchronous sequential circuits 26 .

 typically the “word”-sized data manipulation and storage components through which the data “flows” 27 .Partitioning of Digital Circuits • Control Logic Section  logic required to generate control signals for registers. adders. counters.  “State registers and state transition logics” • Datapath Section  all logic not included in the control logic section • registers. etc. adders. counters. etc. multiplexers.

Manual State Machine Design Method (1) Pseudocode  create an algorithm to describe desired circuit operation (2) RTL Program  convert the pseudocode into an RTL Program (HDL or ASM chart format) (3) Datapath  design the datapath based on the RTL Program (4) State Diagram  based on the RTL Program and the signals defined in the datapath (5) Control Logic Design  based on the state diagram 28 .

except that each “step” is one state of the state machine • All operations within one state execute concurrently  All operations are RTL operations • ASM Chart Format  Uses a graphical notation that resembles a flowchart  Main difference • All operations within one state execute concurrently 29 .RTL Program • HDL Format  Like a pseudocode description.

Example1: Factorial Circuits Pseudocode Step1. fact(15:0)  1. Step 2. For i=2 to n do fact  fact * i. 30 . Step 3. done  0. done  1.

end Step 3.Example1: Factorial Circuits RTL Program Step1. count  2. Step 2. fact(15:0)  1. if (count ≤ n) then begin fact  fact * count. done  1. 31 . count  count + 1. done  0. go to Step 2.

if (count ≤ n) then begin count  count + 1. end Step 3. Step 2. The RTL operations Step1. done  1. go to Step 2. fact(15:0)  1. 32 . fact  fact * count. executed concurrently. within a single “state” are done  0. count  2.Example1: Factorial Circuits Each “step” corresponds to a “state” in the control RTL Program logic.

4. adders or other components. Accepts Control signal inputs to control the operation of the various datapath components. 33 . If there is a variable that is assigned different values at different points in the RTL program.Datapath design rule of thumb 1. Shift register. then a multiplexer or a tri-state bus structure is necessary. A few optimizations may be possible by combining registers. Every unique variable that is assigned a value in the RTL program can be implemented as a register (PIPO. Produce Status signal outputs to Control logic.) 2. counter. etc. 5. 3.

5. counter. fact in our example • fact can be implemented with a simple register. 4. Produce Status signal outputs to Control logic. 34 . • fact is either initialized or have the value fact*count 3. Accepts Control signal inputs to control the operation of the various datapath components.) • count. Shift register. A few optimizations may be possible by combining registers. adders or other components. then a multiplexer or a tristate bus structure is necessary.Rule of thumb applied in our example 1. count with a counter 2. Every unique variable that is assigned a value in the RTL program can be implemented as a register (PIPO. If there is a variable that is assigned different values at different points in the RTL program. etc.

Example1: Factorial Circuits Datapath Control Signals Status Signals 35 .

a CPU with equal numbers of states for each instruction  outputs of the “counter” are the control logic “states” 36 ..g.Control Logic Design Methods • One-FF-per-state method  also referred to as “one-hot encoded” or “delay element” method  uses one FF for each state of the state machine • Binary encoded state method  uses encoded states • number of FFs used = integer_part (log (number_of_states))  results in the most compact implementation • Gray encoded state method • Sequence-counter method  for use with cyclical state transition patterns • e.

One-FF-Per-State Method • Uses one-to-one transformations from state diagram to digital logic components  Also applicable to ASM charts • Transformations  state in state diagram • transforms to a D flip-flop  transition from one state to another in state diagram • transforms to a path from the Q or Q‟ output of one state flip-flop to the D input another D flip-flop  labeled transition in state diagram • AND gate with the labeled condition • labeled (conditional) signal activation also leads to AND gate  Several transitions into a single state • OR gate with one input for each transition 37 .

One-FF-Per-State Method Example 38 .

Conversion from ASM chart to logic 39 .

40 . • The state diagram here is restrictive diagram than formal Finite State Machine (FSM). a state diagram is helpful.Example1: Factorial Circuits – Status Signals State diagram Control Signals • For the Control logic design.

Example1: Factorial Circuits – Control logic 41 .

Example1: Factorial Circuits – Control logic 42 .

clocked by different clock signals)  In large or high-performance circuits. different circuits (or subcircuits) will use different clock inputs because of clock synchronization difficulties or simply because they are independent circuits.Example2: Four-Phase Handshake Transmitter Circuit • Used to communicate between two circuits in different clock domains (i.e..  Communication of data packets between such circuits requires a handshaking protocol 43 .

Handshake protocols 44 .

go to Step 1. req  0.Example2: Four-Phase Handshake Transmitter Circuit: Pseudocode 1. 3.assert request wait until ack = 1. wait until ack = 0. req  1.data ready 2. wait until ready = 1. 45 . -. -. DATA  data_to_be_sent. 5. 4. req  0.

Example2: Four-Phase Handshake Transmitter Circuit: ASM Chart 46 .

• There is only one variable in the pseudocode: DATA 47 . ready and ack are inputs.Example2: ASM Chart to Datapath • req is output. • data_to_be_sent.

Example2: Four-Phase Handshake Transmitter Circuit: ASM Chart to Logic 48 .

Overall Manual State Machine Design Approach • Write down a pseudocode solution  test it out using a short computer program • Convert the pseudocode to an RTL program  try to “optimize” ASM chart. so it uses a small number of states  can use HDL format or ASM chart format • Derive the datapath from the RTL program  figure out the datapath components and signals needed • Form a state diagram with states and control signal activations • Derive the control logic design  one-hot or PLD-based approach 49 .

Contents • Manual state machine design  How to design state machines for complex synchronous sequential digital logic circuits • “Automatic” state machine design  How to convert algorithmic descriptions into HDL code that can be synthesized into working circuits  The general form of the circuit that will be synthesized from an algorithmic HDL description 50 .

Describe the desired circuit using pseudocode.  Implement for the target hardware architecture. Use a synthesis tool to convert the HDL code into a working hardware circuit.  Conversion from an ASM chart into a synthesizable VHDL code can be done through special EDA tools. Convert the pseudocode into an HDL program. 51 .  Inherently concurrent nature of hardware must be kept in mind when writing an HDL code.Automatic State Machine Design 1. 2. 3.  Many engineers adopt C itself as the language for pseudocode in order to simulate and to verify the algorithm.

Recommended Pseudocode Format for HDL code conversion (0) initialize variables. (m) call to function FUNCTION... (k) for (i = 0. . i++) … . … (n) n‟th step of algorithm endwhile 52 . (2) second step of algorithm. while (true) do (1) first step of algorithm... i < max.

Recommended Pseudocode Format for HDL code conversion • Initialization is followed by an infinite while loop. • Loops can be either with operations that can be performed  concurrently  or as a series of sequential steps with delay between the steps. • Operation in while loop can include  assignment to variables  arithmetic/logic operations  conditional actions  calls to subroutines/functions  for/while loops. 53 .

Pseudocode to HDL conversion 54 .

55 . state <= FUNCTION_1. clk) is begin if (reset_n = „0‟) then state <= (others => „0‟).auto-increment state case (state) is when “0000” => -. end case. -. when “0011” => … when FUNCTION_1 => … -.1st step of function … when FUNCTION_1+k => state <= ret_state.Corresponding Synthesizable VHDL Code alg: process (reset_n.of elsif rising_edge(clk) end process alg. (other initialization operations). end if. -.second step of algorithm when “0010” => ret_state <= “0011”. elsif rising_edge(clk) then state <= state + 1.first step of algorithm when “0001” => … -.return from function when others => report “Unknown state!”. -.

Example: Two-Phase Handshake Transmitter Circuit • Used to communicate between two circuits in different clock domains (i.2 56 .. clocked by different clock signals)  In large or high-performance circuits. different circuits (or subcircuits) will use different clock inputs because of clock synchronization difficulties or simply because they are independent circuits  Communication of data packets between such circuits requires a handshaking protocol • Solution implemented using the automatic synthesis-based method instead of the manual state machine design method used in Example 5.e.

while (TRUE) do 2. req  0. 57 . end while. -. 4.invert req value 5.data ready 3. wait until (ready = 1). req  not req. wait until (ack = req). data  data_to_be_sent.Pseudocode 1. -.

-. 58 . -. -.stay in this state until (ack = req) end if. -.send request signal when others => if (ack /= req) then -. state <= “00”.repeat until ready end if.assume data_in is data to be sent when “10” => req <= not req. -. -.state should be a 2-bit unsigned signal elsif rising_edge(clk) then -.on posedge clk state <= state + 1.case “11” state <= “10”.auto-increment current state case (state) is when “00” => if (ready = „0‟) then state <= “00”.Synthesizable VHDL Code • proc1: process (reset_n. -. clk) is begin if (reset_n = „0‟) then req <= „0‟. end if. when “01” => data <= data_in.of elsif rising_edge(clk) end process proc1. end case.