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Chapter #8: Finite State Machine Design

No. 8-1

Motivation Counters: Sequential Circuits where State = Output Generalizes to Finite State Machines: Outputs are Function of State (and Inputs) Next States are Functions of State and Inputs Used to implement circuits that control other circuits "Decision Making" logic Application of Sequential Logic Design Techniques Word Problems Mapping into formal representations of FSM behavior Case Studies

No. 8-2

Chapter Overview Concept of the State Machine Partitioning into Datapath and Control

When Inputs are Sampled and Outputs Asserted
Basic Design Approach Six Step Design Process Alternative State Machine Representations State Diagram, ASM Notation, VHDL, ABEL Description Language Moore and Mealy Machines Definitions, Implementation Examples Word Problems Case Studies
No. 8-3

Concept of the State Machine Example: Odd Parity Checker Assert output whenever input bit stream has odd # of 1's

Re set 0

Ev e n [0] 1 Odd [1] 1

Present State Even Even Odd Odd

Input 0 1 0 1

Next State Even Odd Odd Even

Output 0 0 1 1

Symbolic State Transition Table
Present State 0 0 1 1 Input 0 1 0 1 Next State Output 0 0 1 0 1 1 0 1

0

State Diagram

Encoded State Transition Table

No. 8-5

Concept of the State Machine Example: Odd Parity Checker Next State/Output Functions NS = PS xor PI; OUT = PS
NS Inpu t CLK R \Reset Q D Q PS/Outpu t

Inpu t CL K

T R

Q Q

Outpu t

\Reset
T FF Implementation

D FF Implementation
Input Clk 1 0 0 1 1 0 1 0

1

1

1

0

Output

1

1

1

0

1

1

0

0

1

0

1

1

Timing Behavior: Input 1 0 0 1 1 0 1 0 1 1 1 0
No. 8-6

Next State entered.Concept of State Machine Timing: When are inputs sampled.g. tri-state enable: effective immediately sync. 8-7 . outputs asserted? State Time: Time between clocking events Clocking event causes state/outputs to transition. based on inputs For set-up/hold time considerations: Inputs should be stable before clocking event After propagation delay. next state computed. Outputs are stable NOTE: Asynchronous signals take effect immediately Synchronous signals take effect at the next clocking event E.. counter clear: effective at next clock event No.

next state computed After propagation delay. inputs sampled outputs. outputs and next state become stable Cloc k Inputs Immediate Outputs: affect datapath immediately could cause inputs from datapath to change Delayed Outputs: take effect on next clock edge propagation delays must exceed hold times Outputs No.Concept of State Machine Example: Positive Edge Triggered Synchronous System State T ime On rising edge. 8-8 .

Concept of the State Machine Communicating State Machines One machine's output is another machine's input X FS M 1 Y FS M 2 CLK FSM1 X A A B Y=0 Y=0 A [1] Y=1 X=0 C [0] X=0 FSM2 Y C D D X=1 X=1 Y=0. Y = 0 No.1 B [0] X=0 D [1] Fragment state diagrams Initial inputs/outputs: X = 0. 8-9 .

3~6 covered later (Chap. 5 and 6 generalized from the counter design procedure No. Obtain an abstract specification of the FSM 3. Understand the statement of the Specification 2. Perform a state minimization 4. 9). Perform state assignment (or encoding) 5. Implement the FSM 1.Basic Design Approach Six Step Process 1. 8-10 . 2 covered now. Choose FF types to implement FSM state register 6.

nickels (5 cents) no change Step 1. 8-11 . Understand the problem: Draw a picture! Block Diagram N Coin Sensor D Res et Clk Vending Machine FSM Open Gum Release Mechanism No.Basic Design Approach Example: Vending Machine FSM General Machine Concept: deliver package of gum after 15 cents deposited single coin slot for dimes (10 cents).

dime dime. reset Output: open S3 N Re set S0 N S1 D S2 D S4 [ope n] N S5 [ope n] D S6 [ope n] N S7 [ope n] D S8 [ope n] No. Map into more suitable abstract representation Tabulate typical input sequences: three nickels nickel. 8-12 .Vending Machine Example Step 2. D. dime Draw state diagram: Inputs: N. nickel two dimes two nickels.

Vending Machine Example Step 3: State Minimization Reset 0¢ Pres ent State 0¢ Inputs D N 0 0 1 1 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 0 1 0 1 X Next State 0¢ 5¢ 10¢ X 5¢ 10¢ 15¢ X 10¢ 15¢ 15¢ X 15¢ Output Open 0 0 0 X 0 0 0 X 0 0 0 X 1 N 5¢ D 5¢ N 10¢ D N. 8-13 . D 15¢ [open] 10¢ 15¢ reuse states whenever possible Symbolic State Table No.

8-14 .Vending Machine Example Step 4: State Encoding Pres ent State Inputs Q1 Q0 D N 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Next State D1 D0 0 0 0 1 1 0 X X 0 1 1 0 1 1 X X 1 0 1 1 1 1 X X 1 1 1 1 1 1 X X Output Open 0 0 0 X 0 0 0 X 0 0 0 X 1 1 1 X 0 1 1 0 1 1 No.

Parity Checker Example Step 5. 8-15 . Choose FFs for implementation D FF easiest to use D1 D0 Open Q1 D Q0 N N \ Q0 Q0 \N Q1 N Q1 D D1 D CLK R \reset Q Q Q1 \ Q1 D1 = Q1 + D + Q0 N OPEN D0 = N Q0 + Q0 N + Q1 N + Q1 D D0 D CLK R \reset Q Q0 Q \ Q0 OPEN = Q1 Q0 8 Gates No.

8-16 . Choosing FF for Implementation J-K FF Pres ent State Inputs Q1 Q0 D N 0 0 0 0 0 1 1 0 1 1 0 1 0 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 1 1 1 1 0 0 0 1 1 0 1 1 Next State J1 D 1 D0 0 0 1 X 0 1 1 X 1 1 1 X 1 1 1 X 0 1 0 X 1 0 1 X 0 1 1 X 1 1 1 X 0 0 1 X 0 1 1 X X X X X X X X X K1 X X X X X X X X 0 0 0 X 0 0 0 X J0 K 0 0 1 0 X X X X X 0 1 1 X X X X X X X X X 0 1 0 X X X X X 0 0 0 X Remapped encoded state transition table No.Parity Checker Example Step 5.

Vending Machine Example Implementation: J1 = D + Q0 N K1 = 0 J0 = Q0 N + Q1 D K0 = Q1 N N Q0 D \ Q0 N Q1 D \ Q1 N \reset J CLK Q Q1 \ Q1 K RQ OPEN Q0 \ Q0 CLK J Q KR Q 7 Gates No. 8-17 .

VHDL) No.Alternative State Machine Representations Why State Diagrams Are Not Enough Not flexible enough for describing very complex finite state machines Not suitable for gradual refinement of finite state machine Do not obviously describe an algorithm: that is.. well specified sequence of actions based on input data algorithm = sequencing + data manipulation separation of control and data Gradual shift towards program-like representations: Algorithmic State Machine (ASM) Notation Hardware Description Languages (e. 8-18 .g.

Alternative State Machine Representations Algorithmic State Machine (ASM) Notation Three Primitive Elements: State Box Decision Box Output Box State Entry Path State Code * State Na me State Output List T *** State Box State Machine in one state block per state time Single Entry Point Unambiguous Exit Path for each combination of inputs Outputs asserted high (.L).H) or low (. Immediate (I) or delayed til next clock Condition F ASM Bloc k Condition Box Conditional Output List Output Box Ex its to othe r ASM Block s No. 8-19 .

8-20 .Alternative State Machine Representations ASM Notation Condition Boxes: Ordering has no effect on final outcome Equivalent ASM charts: A exits to B on (I0 & I1 = 1) else exit to C A 010 A 010 I0 T I1 T B F T I1 F F F I0 T C B C No.

Z F T 1 F Symbolic State Table: Present Next Input State State Output F Even Even T Even Odd F A Odd Odd T A Odd Even Encoded State Table: X Trace paths to derive state transition tables Present Next Input State State Output 0 0 0 0 1 0 0 1 0 1 1 1 1 1 1 0 No. 8-21 . Output Z Ev en 0 Nothing in output list implies Z not asserted Z asserted in State Odd X T Odd H.Alternative State Machine Representations Example: Parity Checker Input X.

8-22 .Open 11 N F F D T Reset T F T 0¢ No.Alternative State Machine Representations ASM Chart for Vending Machine 0¢ 00 10¢ 10 D F F N T T T D F F N T 5¢ 01 15¢ H.

Moore and Mealy Machine Design Procedure Definitions State Re giste r Xi Inputs Combinational Logic for Ne xt State (Flip-flop Inputs ) Cloc k Comb. Logic for Outputs Zk Outputs Moore Machine Outputs are function solely of the current state Outputs change synchronously with state changes state feedbac k Xi Inputs Combinational Logic for Outputs a nd Ne xt State Zk Outputs Mealy Machine Outputs depend on state AND inputs Input change causes an immediate output change Asynchronous outputs No. 8-23 State Regis te r Clock State Fe edback .

8-24 .Moore and Mealy Machines State Diagram Equivalents Moore Machine N D + Reset Reset 0¢ [0] Reset 5¢ ND [0] N 10¢ D [0] N+ D 15¢ [1] Reset ND D N Reset/0 0¢ (N D + Reset)/0 Mealy Machine Reset/0 5¢ N D/0 N/0 10¢ D/1 N/0 D/0 N D/0 N+ D/1 15¢ Reset/1 Outputs are associated with State Outputs are associated with Transitions No.

Transitions Mealy Machine typically has fewer states than Moore Machine for same output sequence 0 Asserts its output whenever at least two 1’s in sequence 0 [0] 0 1 [0] 1 0 0/0 0 0/0 1/0 1 1/1 Same I/O behavior Different # of states 1 2 [1] 1 F T F T T F T T F F Equivalent ASM Charts No.Moore and Mealy Machines States vs. 8-25 .

Moore and Mealy Machines Timing Behavior of Moore Machines Reverse engineer the following: why Moore ??? X X \B J Q C KR Q FFa Clk X X \A J Q C KR Q FFb \Reset Z \B \Reset A \A Input X Output Z State A. 8-26 . B (= Z) Two Techniques for Reverse Engineering: Ad Hoc: Try input combinations to derive transition table Formal: Derive next state/output functions by analyzing the circuit No.

Moore and Mealy Machines Ad Hoc Reverse Engineering Behavior in response to input sequence 1 0 1 0 1 0: 100 X Clk A Z \Res et Reset X = 1 X = 0 X = 1 X=0 X =1 X=0 X=0 AB = 00 AB = 00 AB = 11 AB = 11 AB = 10 AB = 10 AB = 01 AB = 00 A B 0 0 X 0 1 0 1 0 1 0 1 A+ ? 1 0 ? 1 0 1 1 B+ ? 1 0 ? 0 1 1 0 Z 0 0 1 1 0 0 1 1 No. 8-27 Partially Derived State Transition Table 0 1 1 0 1 1 .

8-28 .Moore and Mealy Machines Formal Reverse Engineering Derive transition table from next state and output combinational functions presented to the flipflops! Ja = X Jb = X Ka = X B Kb = X xor A Z=B FF excitation equations for J-K flipflop: Q+ = J \Q +\K Q A+ = Ja A + Ka A = X A + (X + B) A B+ = Jb B + Kb B = X B + (X A + X A) B Next State K-Maps: State 00. Input 0  State 00 State 01. Input 1  State 11 No.

Z 11 0 X S1 H. Intrinsic in Moore Machines No. 8-29 .Z 01 1 1 S2 X 10 0 0 X 1 1 X 0 Note: All Outputs Associated With State Boxes No Separate Output Boxes.Moore and Mealy Machines Complete ASM Chart for the Mystery Moore Machine S0 00 S3 H.

State A.Moore and Mealy Machines Reverse Engineering a Mealy Machine Clk A \A R Q \Res et \A X J C K Q R Q \Res et B \B D DA C Q \X A X B \X DA \X B Z X A Input X. 8-30 . B State register consists of D FF and J-K FF No. Output Z.

Moore and Mealy Machine Ad Hoc Method Signal Trace of Input Sequence 101011: 100 X Clk A B Z \Res et Reset AB =00 Z =0 X =1 AB =00 Z =0 X =0 AB =00 Z =0 X =1 AB =01 Z =0 X =0 AB =1 1 Z=1 X =1 AB =10 Z =1 X =1 AB =01 Z =0 Note glitches in Z! Outputs valid at following falling clock edge A B 0 0 Partially completed state transition table based on the signal trace 0 1 1 0 1 1 X 0 1 0 1 0 1 0 1 A+ 0 0 ? 1 ? 0 1 ? B+ 1 0 ? 1 ? 1 0 ? Z 0 0 ? 0 ? 1 1 ? No. 8-31 .

Input 0 -> State 00. Output 1 A+ B+ Z No. Output 1 State 10.Moore and Mealy Machines Formal Method A+ = B (A + X) = A B + B X B+ = Jb B + Kb B = (A xor X) B + X B =ABX + ABX + BX Z =AX + BX Missing Transitions and Outputs: State 01. Input 1 -> State 11. Output 0 State 11. Input 0 -> State 00. 8-32 .

S1 = 01. S2 = 10. 8-33 . S3 = 11 S0 00 S2 10 1 0 X 0 H.Moore and Mealy Machines ASM Chart for Mystery Mealy Machine S0 = 00.Z 11 0 X 1 X 0 1 NOTE: Some Outputs in Output Boxes as well as State Boxes This is intrinsic in Mealy Machine implementation No. Z X 1 H. Z S1 01 S3 H.

Moore and Mealy Machines Synchronous Mealy Machine Clock Xi Inputs Zk Outputs Com binational Logic for Outputs and Next State State Registe r Clock state feedback latched state AND outputs avoids glitchy outputs! No. 8-34 .

8-35 .Finite State Machine Word Problems Mapping English Language Description to Formal Specifications Four Case Studies: Finite String Pattern Recognizer Complex Counter with Decision Making Traffic Light Controller Digital Combination Lock We will use state diagrams and ASM Charts No.

8-36 .Finite State Machine Word Problems Finite String Pattern Recognizer A finite string recognizer has one input (X) and one output (Z). The output is asserted whenever the input sequence …010… has been observed. Understanding the problem statement Sample input/output behavior: X: 00101010010 Z: 00010101000 X: 11011010010 Z: 00000001000 No. as long as the sequence 100 has never been seen. Step 1.

I. Moore State Diagram Reset signal places FSM in S0 Outputs 1 Loops in State No. 010 and 100. Draw State Diagrams/ASM Charts for the strings that must be recognized.e. 8-37 .Finite State Machine Word Problems Finite String Recognizer Step 2..

8-38 .Finite State Machine Word Problems Finite String Recognizer Exit conditions from state S3: if next input is 0 then have …0100 (state S6) if next input is 1 then have …0101 (state S2) No.

8-39 .Finite State Machine Word Problems Finite String Recognizer Exit conditions from S1: recognizes strings of form …0 (no 1 seen) loop back to S1 if input is 0 Exit conditions from S4: recognizes strings of form …1 (no 0 seen) loop back to S4 if input is 1 No.

If next input is 1. then string could be prefix of (10)1(0) S2 handles just this case! Final State Diagram No. S5 with incomplete transitions S2 = …01.Finite State Machine Word Problems Finite String Recognizer S2. If next input is 1. 8-40 . then string could be prefix of (01)1(00) S4 handles just this case! S5 = …10.

Finite State Machine Word Problems Finite String Recognizer Review of Process: Write down sample inputs and outputs to understand specification Write down sequences of states and transitions for the sequences to be recognized Add missing transitions. reuse states as much as possible Verify I/O behavior of your state diagram to insure it functions like the specification No. 8-41 .

011. When M = 1. 010. 3 bit counter has a mode control M. 110. the counter advances through the Gray code sequence. 101. 101. 8-42 . Binary: 000. 100. 011.Finite State Machine Word Problems Complex Counter A sync. 100 Valid I/O behavior: Mode Input M 0 0 1 1 1 0 0 Current State 000 001 010 110 111 101 110 Next State (Z2 Z1 Z0) 001 010 110 111 101 110 111 No. the counter counts up in the binary sequence. 001. 001. 010. 111 Gray: 000. 111. When M = 0. 110.

Z 1 H. 8-43 .Z 1 0 1 S3 011 H.Z 0 M 1 S6 H.Z 2 1 0 S7 H.Z 1 H.Z 0 0 111 M S5 1 0 H.Z 2 H.Z 2 H.Z 1 M 0 110 S4 100 H.Finite State Machine Word Problems Complex Counter One state for each output combination Add appropriate arcs for the mode control S0 000 S1 H.Z 2 H.Z 0 0 001 M 1 S2 010 H.Z 0 101 M M 1 No.

light remain green in highway direction. Detectors C sense the presence of cars waiting on the farmroad. highway gets at least a set interval as green. 8-44 . When these are met. allowing the farmroad lights to become green. allowing highway to return to green. TS is to be used for timing yellow lights and TL for green lights. farm lights transition from Green to Yellow to Red.Finite State Machine Word Problems Traffic Light Controller A busy highway is intersected by a little used farmroad. No. Assume you have an interval timer that generates a short time pulse (TS) and a long time pulse (TL) in response to a set (ST) signal. If vehicle on farmroad. highway lights go from Green to Yellow to Red. Even if farmroad vehicles are waiting. With no car on farmroad. These stay green only as long as a farmroad car is detected but never longer than a set interval.

Finite State Machine Word Problems Traffic Light Controller Picture of Highway/Farmroad Intersection: Fa rmroad C FL HL Highw ay Highw ay HL FL C Fa rmroad No. 8-45 .

HY. 8-46 .Finite State Machine Word Problems Traffic Light Controller Tabulation of Inputs and Outputs: Input Signal reset C TS TL Output Signal HG. FY. FR ST Description place FSM in initial state detect vehicle on farmroad short time interval expired long time interval expired Description assert green/yellow/red highway lights assert green/yellow/red farmroad lights start timing a short or long interval Tabulation of Unique States: Some light configuration imply others State S0 S1 S2 S3 Description Highway green (farmroad red) Highway yellow (farmroad red) Farmroad green (highway red) Farmroad yellow (highway red) No. HR FG.

HR H.HY H. 8-47 .Finite State Machine Word Problems Traffic Light Controller Refinement of ASM Chart: Start with basic sequencing and outputs: S0 H.HG H.FG No.HR H.FR S2 H.FY S1 H.FR S3 H.

HG H.FR 0 0 1 0 C 1 H.FR S0 H.C · TL S0 H.ST Equivalent ASM Chart Fragments No.ST S1 H. 8-48 .HG H.HY H.FR S1 H.HY H.FR C · TL TL TL •  C 1 H.Finite State Machine Word Problems Traffic Light Controller Determine Exit Conditions for S0: Car waiting and Long Time Interval Expired.

ST S2 H.Finite State Machine Word Problems Traffic Light Controller S1 to S2 Transition: Set ST on exit from S0 Stay in S1 until TS asserted Similar situation for S3 to S4 transition S1 H. 8-49 .HY H.HR H.FR 0 H.FG TS 1 No.

HG H.FR 0 H.FY 0 TL  • C  1 H.FR 0 H.FG 0 TL + C 1 TS 1 Complete ASM Chart for Traffic Light Controller No.ST S1 H.HR H. 8-50 .HY H.Finite State Machine Word Problems Traffic Light Controller S2 Exit Condition: no car waiting OR long time interval expired S0 H.HR H.ST S3 H.ST S2 H.ST 1 TS H.

Finite State Machine Word Problems Traffic Light Controller Compare with state diagram: TL + C Res et S0 TL•C/ST TS S1 TS /ST S2 TL • C S3 TS TL + C/ST TS /ST S0: HG S1: HY S2: FG S3: FY Advantages of ASM Charts: Concentrates on paths and conditions for exiting a state Exit conditions built up incrementally. later combined into single Boolean condition for exit Easier to understand the design as an algorithm No. 8-51 .

stored in internal register assert as soon as error is detected vs. Sequence is: (1) Press RESET. Inputs are RESET. (4) repeat (2) & (3) two more times. 2 position switch for bit of key data. (3) Press ENTER." Problem specification is incomplete: how do you set the internal combination? exactly when is the ERROR light asserted? Make reasonable assumptions: hardwired into next state logic vs.Finite State Machine Word Problems Digital Combination Lock "3 bit serial lock controls entry to locked room. Locks generates an UNLOCK signal when key matches internal combination. ERROR light illuminated if key does not match combination. (2) enter key bit. wait until full combination has been entered Our design: registered combination plus error after full combination No. 8-52 . ENTER.

8-53 . L2 Outputs: Unlock Error No.Finite State Machine Word Problems Digital Combination Lock Understanding the problem: draw a block diagram RESET Operator Data ENTER KEY-IN UNLOCK Combination Lock F SM ERR OR Internal Combination L0 L1 L2 Inputs: Reset Enter Key-In L0. L1.

8-54 .Finite State Machine Word Problems Digital Combination Lock Enumeration of states: what sequences lead to opening the door? error conditions on a second pass START state plus three key COMParison states START START entered on RESET Exit START when ENTER is pressed Reset 0 Enter COMP0 1 0 1 KI = L0 Y N Continue on if Key-In matches L0 No.

8-55 .Unlock N Compare Key-IN KI = L1 Y N Reset 1 STAR T 0 No.Finite State Machine Word Problems Digital Combination Lock COMP0 IDLE1 Path to unlock: N 0 KI = L 0 Y IDLE0 Enter COMP2 1 Wait for Enter Key press Enter COMP1 1 0 KI = L2 Y DON E H.

8-56 .Finite State Machine Word Problems Digital Combination Lock Now consider error paths Should follow a similar sequence as UNLOCK path.Error 0 0 Enter ER ROR1 1 Enter ER ROR2 1 0 Reset 1 STAR T COMP0 error exits to IDLE0' COMP1 error exits to IDLE1' COMP2 error exits to ERROR3 No. except asserting ERROR at the end: IDLE0' IDLE1' ER ROR3 H.

Finite State Machine Word Problems Digital Combination Lock Re set + E nter Re set Start Re set • Enter Comp0 KI = L0 Ente r Idle0 Ente r Comp1 KI = L1 Ente r Idle1 Ente r Comp2 KI = L2 Re set Done [Unloc k] Re set Start KI ° L2 KI ° L1 KI ° L0 Ente r Idle0' Ente r Error1 Equivalent State Diagram Ente r Idle1' Ente r Error2 Error3 [Error] Re set Start Re set No. 8-57 .

expand with error conditions reuse states whenever possible No. 8-58 . inputs) First Two Steps of the Six Step Procedure for FSM Design understanding the problem abstract representation of the FSM Abstract Representations of an FSM ASM Charts Word Problems understand I/O behavior. draw diagrams enumerate states for the "goal".Chapter Review Basic Timing Behavior an FSM when are inputs sampled. outputs = F(state. next state/outputs transition and stabilize Moore and Mealy (Async and Sync) machine organizations outputs = F(state) vs.