Flip-Flops & Latches

Digital Electronics

Flip-Flops & Latches
This presentation will
• Review sequential logic and the flip-flop.
• Introduce the D flip-flop and provide an excitation table and a sample timing analysis.

• Introduce the J/K flip-flop and provide an excitation table and a sample timing analysis.
• Review flip-flop clock parameters. • Introduce the transparent D-latch. • Discuss flip-flop asynchronous inputs.
2

. Combinational Logic Gates . . Outputs Clock Memory Elements (Flip-Flops) 3 .Sequential Logic & The Flip-Flop Inputs .

D Flip-Flop: Excitation Table D D Q CLK   Q 0 1 Q 1 0 0 1 CLK Q  : Rising Edge of Clock 4 .

D Flip-Flop: Example Timing Q=D=1 Q=D=0 Q=D=0 No Change Q=D=1 Q=D=1 No Change Q=D=0 Q=D=0 No Change Q D CLK 5 .

J/K Flip-Flop: Excitation Table J J CLK K Q K 0 1 0 1 CLK     Q Q0 No Change Clear Set Toggle 0 Q 0 1 1 0 1 Q0  : Rising Edge of Clock Q : Complement of Q 6 .

J/K Flip-Flop: Example Timing SET TOGGLE TOGGLE CLEAR NO CHANGE SET NO CHANGE Q J K CLK 7 .

Clock Edges Positive Edge Transition 1 0 1 0 Negative Edge Transition 8 .

POS & NEG Edge Triggered D Positive Edge Trigger D D Q CLK   Q 0 1 Q 1 0 0 1 CLK Q  : Rising Edge of Clock Negative Edge Trigger D D Q CLK   Q 0 1 Q 1 0 9 0 1 CLK Q  : Falling Edge of Clock .

POS & NEG Edge Triggered J/K Positive Edge Trigger J J CLK K Q K 0 1 0 1 CLK     Q Q0 0 0 1 1 0 1 Q0 Q  : Rising Edge of Clock Negative Edge Trigger J J CLK K Q K 0 1 0 1 CLK     Q Q0 0 0 1 1 0 1 Q0 10 Q  : Rising Edge of Clock .

or K) must be maintained. 11 . or K) 1 0 tS Setup Time Positive Edge Clock 1 0 tH Hold Time Setup Time (tS): The time interval before the active transition of the clock signal during which the data input (D.J. J. Hold Time (tH): The time interval after the active transition of the clock signal during which the data input (D. or K) must be maintained.Flip-Flop Timing Data Input (D. J.

Asynchronous Inputs Asynchronous inputs (Preset & Clear) are used to override the clock/data inputs and force the outputs to a predefined state. The Preset (PR) input forces the output to: D PR Q Q 1 & Q  0 The Clear (CLR) input forces the output to: CLK CLR Q Q  0 & Q 1 PR PRESET CLR CLEAR CLK CLOCK D DATA Q 0 1 1 0 1 Q 1 0 0 1 1 Asynchronous Preset Asynchronous Clear ILLEGAL CONDITION 12 1 1 0 1 0 1 1 1 0 0   X X X 0 1 X X X .

D Flip-Flop: PR & CLR Timing Q=D=1 Clocked Q=D=0 Clocked Q=D=0 Clocked Q=D=1 Clocked Q=D=1 Clocked Q=D=0 Clocked Q Q=1 Preset Q=1 Preset PR CLR D CLK Q=0 Clear 13 .

Transparent D-Latch EN D Q D X 0 1 Q Q0 Q Q0 0 1 0 1 1 0 EN Q 1 EN: Enable 14 .

Transparent D-Latch: Example Timing “Latched” Q=0 “Transparent” Q=D “Latched” Q=1 “Transparent” Q=D “Latched” Q=0 “Transparent” Q=D Q D EN 15 .

meaning the latch’s output changes on the level (high or low) of the EN input. meaning the flip-flop’s output changes on the edge (rising or falling) of the CLOCK input. • The flip-flop’s CLOCK input is edge sensitive. • The latch’s EN input is level sensitive.Flip-Flop Vs. Latch • The primary difference between a D flip-flop and D latch is the EN/CLOCK input. 16 .

and Complementary Outputs 74LS76 Dual Negative-Edge-Triggered J-K Flip-Flops with Preset.Flip-Flops & Latches 74LS74 Dual Positive-Edge-Triggered D Flip-Flops with Preset. and Complementary Outputs 74LS75 Quad Latch 17 . Clear. Clear.

74LS74: D Flip-Flop 18 .

74LS76: J/K Flip-Flop 19 .

74LS75: D Latch 20 .

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