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Raytheon Vision Systems
MIT Lincoln Laboratory
Scientific Detector Workshop, Sicily 2005
CMOS - 1
amplifiers (analog output) .no further circuitry (analog out) .add. charge integration & charge-to-voltage conversion Multiplexing of pixel voltages: Successively connect amplifiers to common bus Various options possible: .General CMOS Detector Concept CCD Approach Photodiode CMOS Approach Photodiode Amplifier + Pixel Charge generation & charge integration Charge generation.2 .A/D conversion (digital output) Array Readout Charge transfer from pixel to pixel Sensor Output Output amplifier performs charge-to-voltage conversion CMOS .
programmable gain. rolling shutter.) • Electronic shutter (snapshot. subsampling and binning Bias generation (DACs) Analog signal processing (e. windowing.Common CMOS Features • CMOS sensors/multiplexers utilize the same process as modern microchips – Many foundries available worldwide – Cost efficient – Latest processes available down to 0.3 .13 µm • CMOS process enables integration of many additional features – – – – – – Various pixel circuits from 3 transistors up to many 100 transistors per pixel Random pixel access. CDS.g. digital signal processing. non-destructive reads) – No mechanical shutter required • Low power consumption • Radiation tolerant (by process and by design) CMOS . noise filter) A/D conversion Logic (timing control. etc.
Astronomy Application: Guiding • Special windowing can be used to perform full-field science integration in parallel with fast window reads.4 . • Two methods possible: – Interleaved reading of full-field and window • No scanning restrictions or crosstalk issues • Overhead reduces full-field frame rate – Parallel reading of full-field and window • Requires additional output channel • Parallel read may cause crosstalk or conflict • No overhead maintains maximum full-field frame rate Full field row Window Full field row Full field row Window Full field row Full field row Window CMOS . Simultaneous guide operation and science data capture within the same detector.
Stitching Enables Large Sensor Arrays • The small feature size of modern CMOS processes limits the maximum area that can be exposed in one step (so-called reticle) to about 22 mm.5 . – Sub-blocks are exposed one after another – Some blocks are used multiple times – Ultimate limit is given by wafer size Stitched CMOS Sensor horiscan1 horiscan2 V 1 array array array Reticle horiscan2 horiscan1 22mm V 1 V V 2 3 array V 2 array array array V 3 array array array CMOS . • However. larger chips can produced by breaking up the design into smaller sub-blocks that fit into the reticle.
etc.6 .Monolithic CMOS • A monolithic CMOS image sensor combines the photodiode and the readout circuitry in one piece of silicon – Photodiode and transistors share the area => less than 100% fill factor – Small pixels and large arrays can be produced at low cost => consumer applications (digital cameras. cell phones.) 3T Pixel Reset SF PD Select Read Bus 4T Pixel Reset Pinned PD p+ photodiode transistors TG n+ p-sub SF n+ Select Read Bus CMOS .
Complete Imaging Systems-on-a-Chip • Monolithic CMOS technology has enabled highly integrated. high dynamic range. etc. complete imaging systems-on-a-chip: – Single chip cameras for video and digital still photography – Performance has significantly improved over last decade and is better or comparable to CCDs for many applications. but requires modification of CMOS process 2 Mpixel HDTV CMOS Sensor Quantum Efficiency of a CMOS sensor Si PIN NIR AR coating Si PIN UV AR coating • Microlenses increase fill factor: 3T pixel w/ microlenses photodiode CMOS .) • However. monolithic CMOS is still limited with respect to quantum efficiency: – Photodiode is relatively shallow => low red response – Metal and dielectric layers on top of the diode absorb or reflect light => low overall QE – Backside illumination possible. – Especially suited for high frame rate sensors (> Gigapixel/s) or other special features (windowing.7 .
000.000.9% interconnect yield • Also called a Focal Plane Array (FPA) or Hybrid Array CMOS .Sensor Chip Assembly (SCA) Structure: Hybrid of Detector Array and ROIC Connected by Indium Bumps Detector Array Indium bump Detector Array Silicon Readout Integrated Circuit (ROIC) Mature interconnect technique: – Over 4.000 indium bumps per SCA demonstrated – 99.8 .000 16.
9 .CMOS SCA Revolution Number of Pixels per Array 1E+09 MWIR arrays 1E+08 1E+07 1E+06 1E+05 1E+04 1E+03 1E+02 Moore's law with 18 month doubling time predicted 1980 1985 1990 1995 2000 2005 2010 Year First used in Astronomy • Large CMOS hybrids revolutionized infrared astronomy • Growth in size has followed "Moore's Law" for over 20 years – 18 month doubling time CMOS .
Three Most Common Input Circuits for CMOS ROICs Circuit SFD (Source Follower per Detector) also called "Self Integrator" • • • • Advantages Disadvantages • gain fixed by detector and ROIC input capacitance • detector bias changes during integration • some nonlinearity • more complex circuit • FET glow • higher power Comments simple low noise low FET glow low power Most common circuit in IR astronomy CTIA (Capacitance Transimpedance Amplifier) • very linear • gain determined by ROIC design (Cfb) • detector bias remains constant • large well capacity • gain determined by ROIC design (Cint) • detector bias remains constant • low FET glow • low power Very high gains demonstrated DI (Direct Injection) • poor performance at low flux Standard circuit for high flux CMOS .10 .
Temperature and Wavelengths of High Performance Detector Materials Si PIN InGaAs SWIR HgCdTe MWIR HgCdTe InSb LWIR HgCdTe Si:As IBC Approximate detector temperatures for dark currents << 1 e-/sec CMOS .11 .
7m 2.9** – 1.7 0.0 0.4 – 1.2 ~ 200 ~ 130 ~ 140 ~ 90 ~ 50 ~ 25? ~ 35 • ROICs are interchangeable among detectors (except Si:As) • HgCdTe and InGaAs require special packaging due to CTE mismatch between detector and ROIC Si:As IBC (BIB) 5 – 28 ~7 * Long wave cutoff is defined as 50% QE point ** Spectral range can be extended into visible range by removing substrate *** Approximate detector temperatures for dark currents << 1 e-/sec CMOS .2 5 – 10 0.12 .9** – 1.7 0.5 m 5.4 – 5.9** – 5.2 m 10 m InSb 0.Detector Material Choices for CMOS Hybrid Arrays Detector Material Spectral Range*.5 0.9** – 2. K General Comments • All detectors can have: – 100% optical fill factor – 100% internal QE (total QE depends on AR coat) • Exception: Si:As is 40-70% between 5 and 10 m Si PIN InGaAs HgCdTe: 1. m Operating Temp***.
13 180-nm SRAM cell Stacked via to poly . Foundry access Epi doping optimized for digital CMOS Scalable to 300mm Complex implant engineering Rapid Thermal Processing (RTP) Multiple gate dielectric thicknesses Complementarily doped polysilicon Silicided polysilicon and FET source/drain Fine-line patterning Multiple metal layers (dense routing) Highly suitable for long-term space-based applications 2m 2m 2m Four-Poly OTCCD CMOS .Process Comparison CCD > 35 years of evolution “Trailing edge” fabs High resistivity (deep depletion) substrates Controlled temperature ramps & stress control Buried channel Multiple oxidation cycles Single gate dielectric thickness Doped polysilicon (single type) Highly nonplanar surfaces Conservative design rules Vulnerable to space-radiation-induced traps CMOS Economics of scale accelerate progress Lower fabrication cost.
salicide – Transistor short channel effects OUT n+ p-well n-Well Field Oxide p+ • Substrate bounce and transient coupling effects p-epi p+ Substrate CMOS . metal.14 . and oxide layers – Surface recombination at Si/SiO2 interface – QE*FF > 60% is good. heavily doped junctions – Limited depletion depth – Absorption and reflection in poly. many < 20% RST VDD ROW VDD ROW RST OUT • High leakage – LOCOS/STI.Limitations of Standard Bulk CMOS APS • Fill factor tradeoff – Photodetector and pixel transistors share same area – PD from Drain-Substrate or Well-Substrate diode Pixel Layout photodiode • Low photoresponsivity – Shallow.
CDS.15 .Advantages of Vertical Integration Conventional Monolithic APS Addressing PD 3T pixel ROIC Processor Addressing A/D. … pixel 3-D Pixel Light PD • Pixel electronics and detectors share area • Fill factor loss • Co-optimized fabrication • Control and support electronics placed outside of imaging area • 100% fill factor detector • Fabrication optimized by layer function • Local image processing – Power and noise management • Scalable to large-area focal planes CMOS .
16 .Approaches to 3D Integration (To Scale) Tier-1 3D-Vias 3D-Vias 10 m 10 m Photo Courtesy of RTI Tier-2 10 m Bump Bond used to flip-chip interconnect two circuit layers Two-layer stack using Two-layer stack with insulated vias through Lincoln’s SOI-based vias thinned bulk Si CMOS .
Random Access. least 2 chips needed can be integrated into single chip Orthogonal Transfer. 10x lower than CCD Much less susceptible to radiation High voltage clocks. Reference Pixels. specifically for large mosaic focal plane arrays. < 10 µm demonstrated 400 – 1000 nm with Si PIN 400 – 5000 nm with InSb or HgCdTe Few electrons with multiple sampling Electronic. Binning. at Low voltage only. Guide Mode. CMOS . Large dynamic range (up the ramp) Silicon PIN hybrid detectors have become a serious alternative to CCDs providing a number of significant advantages. CCD for Astronomy Property Resolution Pixel pitch Typ. wavelength coverage Noise Shutter Power Consumption Radiation Control Electronics Special Modes > 4k x 4k 10 – 20 µm 400 – 1000 nm Few electrons Mechanical High Sensitive CCD Hybrid CMOS 2k x 2k in use. rolling shutter Typ. 4k x 4k demonstrated 18 – 40 µm.17 .Comparison CMOS vs. Adaptive Optics Windowing.