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Credits:

Slides adapted from:

J.F. Wakerly, Digital Design, 4/e, Prentice Hall, 2006 C.H. Roth, Fundamentals of Logic Design, 5/e, Thomson, 2004 A.B. Marcovitz, Intro. to Logic and Computer Design, McGraw Hill, 2008 R.H. Katz, G. Borriello, Contemporary Logic Design, 2/e, Prentice-Hall, 2005

1

**Multiplexers (Data Selectors)
**

**A multiplexer (MUX for short) is a digital switch:
**

it passes (connects) one of its data inputs to the output. the data input selected is a function of a set of control inputs called selection inputs.

A 0 1 Z I0 I1

Two alternative forms for a 2:1 Mux truth table Z = A' I0 + A I1

I1 0 0 0 0 1 1 1 1

I0 0 0 1 1 0 0 1 1

A 0 1 0 1 0 1 0 1

Z 0 0 1 0 0 1 1 1

2

Multiplexers (cont’d)

Z mk I k

k 0

2 n 1

3

**Gate level implementation of muxes
**

2:1 mux

4:1 mux

4

I5. I2. I3 and one of I4. I6. I1.Cascading multiplexers Large multiplexers can be made by cascading smaller ones I0 I1 I2 I3 I4 I5 I6 I7 4:1 mux 8:1 mux 2:1 mux Z I0 I1 I2 I3 I4 I5 B C A I6 I7 alternative implementation 2:1 mux 2:1 mux 2:1 mux 2:1 mux C A B 5 8:1 mux 4:1 mux 4:1 mux Z Control signals B and C simultaneously choose one of I0. I7 Control signal A chooses which of the upper or lower mux's output to gate to Z .

B.Multiplexers as general-purpose logic A 2n:1 multiplexer can implement any function of n variables with the variables used as control inputs and the data inputs tied to 0 or 1 1 0 1 0 0 0 1 1 0 1 2 3 4 8:1 MUX 5 6 7 S2 S1 S0 A B Example: F(A.C) = m0 + m2 + m6 + m7 = A'B'C' + A'BC' + ABC' + ABC Z F = A'B'C'(1) + A'B'C(0) + A'BC'(1) + A'BC(0) + AB'C'(0) + AB'C(0) + ABC'(1) + ABC(1) Z = A'B'C'I0 + A'B'CI1 + A'BC'I2 + A'BCI3 + AB'C'I4 + AB'CI5 + ABC'I6 + ABCI7 C 6 .

four possible configurations of truth table rows can be expressed as a function of In 0 In In' 1 7 . In-1 In .Multiplexers as general-purpose logic (cont’d) Generalization data inputs can also be tied to variables not just 0’s an 1’s I0 . . . . 0 1 0 0 0 1 F 1 0 1 1 n-1 mux control variables single mux data variable . . . I1 . . .

Activity Realize F = B’CD’ + ABC’ with a 4:1 multiplexer A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Z 0 0 1 0 0 0 0 0 0 0 1 0 1 1 0 0 0 when B’C’ D’ when B’C A when BC’ 0 D’ A 0 0 1 4:1 MUX 2 3 S1 S0 B C F 0 when BC Z = B’C’(0) + B’C(D’) + BC’(A) + BC(0) 8 .

Multiplexer with bus inputs and outputs 9 .

Demultiplexers Route a single input to one of many outputs. as a function of a set of control inputs y0 y1 y2 y3 y4 y5 y6 y7 x 1:8 demux 3 s[2:0] 10 .

B1 B2 1 ? 0 The two driving blocks fight with each other Use of tri-state logic permits the outputs of two or more gates or other logic devices to be connected together 11 (buffers are a.a.Three-State Buffers Normally.k. a logic circuit will not operate correctly if the outputs of two or more gates or other logic devices are directly connected to each other (multiple drivers conflict). drivers) .

Tri-state Buffers (cont’d) When the enable B is 1. the output C acts like an open circuit. 12 . In this case the output C is effectively disconnected from the buffer output so that no current can flow. the output C equals A. When the enable B is 0. This is often referred as Hi-Z (high-impedance) state because the circuit offers a very high impedance to the flow of current.

Tri-state Buffers application examples 13 .

Tri-state Buffers application examples (cont’d) 14 .

Tri-state buffers application examples (cont’d) 15 .

Tri-state Buffers application examples (cont’d) 16 .

Each input code word produces a different output code word (there is a one-to-one mapping between inputs and outputs) 17 .Decoders A decoder is a logic circuit that converts coded inputs into coded outputs.

Decoders (cont’d) Decimal 18 .

Binary Decoders The most common decoder circuit is an n-to-2n decoder (or binary decoder) 19 .

Binary Decoders (cont’d) 20 .

Binary Decoders (cont’d) 21 .

Gate level implementation of decoders active-high enable active-low enable O0 O1 \G O0 O1 G S 1:2 decoders G S O0 O1 O2 O3 \G active-low enable O0 O1 O2 O3 active-high enable 2:4 decoders 22 S1 S0 S1 S0 .

Decoders as general-purpose logic n-to-2n decoders can implement any function of n variables with the variables used as control inputs the appropriate minterms summed to form the function 0 1 2 3 3:8 DEC 4 5 6 7 S2 S1 S0 A B C A'B'C' A'B'C A'BC' A'BC AB'C' AB'C ABC' ABC decoder generates appropriate minterm based on control signals (it "decodes" control signals) 23 .

Decoders as general-purpose logic (cont’d) 0 1 2 3 4 5 6 4:16 7 DEC 8 9 10 11 12 13 14 15 A B C D A'B'C'D' A'B'C'D A'B'CD' A'B'CD A'BC'D' A'BC'D A'BCD' A'BCD AB'C'D' AB'C'D AB'CD' AB'CD ABC'D' ABC'D ABCD' ABCD F1 F1 = A'BC'D + A'B'CD + ABCD F2 = ABC'D' + ABC F3 = (A' + B' + C' + D') F2 F3 24 .

Encoders An encoder performs the inverse function as a decoder The simplest encoder to build is a 2n-to-n (binary encoder) 25 .

Priority Encoders I7 I6 I5 I4 I3 I2 I1 I0 A2 A1 A0 IDLE 0 1 0 0 0 x 1 0 0 x x 1 0 x x x 0 x x x 0 x x x 0 x x x 0 x x x 0 1 1 1 0 1 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 x 1 0 0 0 x x 1 0 0 x x x 1 0 x x x x 1 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 26 0 0 0 0 0 .

Priority Encoders (cont’d) 27 .

Programmable Arrays ROM (read only memories) PLA (programmable logic array) PAL (programmable array logic) CPLD (complex programmable logic devices) FPGA (field programmable gate arrays) 28 .

Read-Only Memories (ROM) A ROM consists of a two dimensional array of semiconductor devices interconnected to store an array of binary data Two-level canonical form combinational logic can be implemented using a ROM as a look-up-table (LUT) B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F0 0 1 0 0 1 1 0 0 F1 0 1 1 0 0 0 0 1 F2 1 1 0 0 1 0 0 0 F3 0 0 0 1 1 0 1 0 F0 = A' B' C + A B' C' + A B' C F1 = A' B' C + A' B C' + A B C F2 = A' B' C' + A' B' C + A B' C' F3 = A' B C + A B' C' + A B C' A 0 0 0 0 1 1 1 1 truth table 29 .

Combinational logic using a ROM 30 .

ROM Structure 2n words 31 .

The internal organization of a PLA is different from that of the ROM 32 .PLA (Programmable Logic Arrays) A PLA performs the same basic LUT task as a ROM. A PLA with n inputs and m outputs can realize m combinational functions of n variables.

PLA (cont’d) 33 .

PLA short-hand notation 34 .

Activity Map the following functions to the PLA below: W = AB + A’C’ + BC’ X = ABC + AB’ + A’B Y = ABC’ + BC + B’C’ A B C W X Y 35 .

Activity (cont’d) Manipulating logic functions so that they can use available resources is called Technology Mapping 9 terms won’t fit in a 7 term PLA can apply concensus theorem to W to simplify to: W = AB + A’C’ A B C ABC ABC’ 8 terms wont’ fit in a 7 term PLA A’C’ AB’ A’B BC observe that AB = ABC + ABC’ can rewrite W to reuse terms: W = ABC + ABC’ + A’C’ W = ABC + ABC’ + A’C’ X = ABC + AB’ + A’B Y = ABC’ + BC + B’C’ W X Y Now it fits B’C’ 36 .

PAL Segment 37 .PAL (Programmable Array Logic) The PAL is a special case of the PLA in which the AND array is programmable and the OR array is fixed Figure.

Implementation of a Full Adder Using a PAL 38 .

The macrocells are connected using a single large programmable interconnect block FPGAs contain a regular structure of programmable basic logic cells surrounded by programmable interconnect. 39 .CPLDs and FPGAs The distinction between CPLD and FPGAs is blurred. CPLDs contain a matrix of logic macrocells that usually consist of programmable array logic followed by a flip-flop or latch.

Example of CPLD Internal Structure 40 .

Example of FPGA Internal Structure 41 .

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