This action might not be possible to undo. Are you sure you want to continue?

BooksAudiobooksComicsSheet Music### Categories

### Categories

### Categories

Editors' Picks Books

Hand-picked favorites from

our editors

our editors

Editors' Picks Audiobooks

Hand-picked favorites from

our editors

our editors

Editors' Picks Comics

Hand-picked favorites from

our editors

our editors

Editors' Picks Sheet Music

Hand-picked favorites from

our editors

our editors

Top Books

What's trending, bestsellers,

award-winners & more

award-winners & more

Top Audiobooks

What's trending, bestsellers,

award-winners & more

award-winners & more

Top Comics

What's trending, bestsellers,

award-winners & more

award-winners & more

Top Sheet Music

What's trending, bestsellers,

award-winners & more

award-winners & more

Welcome to Scribd! Start your free trial and access books, documents and more.Find out more

Multioperand Addition

Required Reading

Behrooz Parhami, Computer Arithmetic: Algorithms and Hardware Design

**Chapter 8, Multioperand Addition
**

Note errata at:

http://www.ece.ucsb.edu/~parhami/text_comp_arit_1ed.htm#errors

Recommended Reading

J-P. Deschamps, G. Bioul, G. Sutter, Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems Chapter 11.1.12 Multioperand Adders

Applications of multioperand addition Multiplication p=a·x s= Inner product x(i) y(i) = p(i) i=0 i=0 n-1 n-1 .

Number of bits of the result S= x(i) i=0 n-1 x(i) [0..2k-1] Smin = 0 Smax = n (2k-1) = # of bits of S = log2 (Smax + 1) = log2 (n (2k-1) + 1) = k + log2 n log2 n 2k = .

Serial implementation of multioperand addition .

Adding 7 numbers in the binary tree of adders .

Ripple-carry adders at levels i and i+1 .

Example: Adding 8 3-bit numbers .

.. c3 a2 b2 FA a1 b1 c2 FA a0 b0 c1 FA c0 sn-1 s2 s1 s0 .Ripple-Carry Carry Propagate Adder (CPA) an-1 bn-1 cn FA cn-1 .

Carry Save Adder (CSA) an-1 bn-1 cn-1 FA . a2 b2 c2 FA a1 b1 c1 FA a0 b0 c0 FA cn sn-1 cn-1 s3 c3 s2 c2 s1 c1 s0 ...

A Ripple-Carry vs. Carry-Save Adder .

Operation of a Carry Save Adder (CSA) Example 24 23 22 21 20 x y z 0 1 0 1 0 1 1 0 1 1 1 0 1 1 1 0 0 1 1 0 s c 1 1 0 1 1 x+y+z = s + c .

Carry propagate and carry-save adders in dot notation .

Specifying full.and half-adder blocks in dot notation .

Carry-save adder for four operands x3 x2 x1 x 0 y3 y2 y1 y 0 z3 z2 z1 z 0 w3 w2 w1 w0 s3 s2 s1 s 0 c4 c3 c2 c1 w3 w2 w1 w0 c4 s’ 3 s’ 2 s’ 1 s’ 0 c4 ’ c’ 3 c’ 2 c’ 1 S5 S4 S3 S2 S1 S0 .

Carry-save adder for four operands c4 s3 c3 s2 c2 s1 c1 s0 c4 ’ s3 ’ c3 ’ ’ s2 c’2 s’1 c1 ’ s’ 0 .

Carry-save adder for four operands x 4 y 4 4 z 4 w CSA c s CSA c’ CPA S s’ .

Carry-save adder for six operands CSA tree Implementation of one-bit slice .

Tree of carry save adders reducing seven numbers to two .

Addition of seven six-bit numbers in dot notation .

Adding seven k-bit numbers: block diagram .

Relationship Between Number of Inputs and Tree Height .

n) Tree height for n operands Component Adders CSA CPA Widths k . k + log2 n k + log2 n typically close to k bits .Parameters of tree carry-save adders (1) Latency LatencyCSA = h(n) TFA + LatencyCPA(k..

n(h) n(0) = 2 3 n(h) = n(h-1) 2 n(1) = 3 n(2) = 4 n(3) = 6 n(4) = 9 n(5) = 13 n(6) = 19 2 ( ) 3 h-1 < n(h) 2 2 ( ) 3 h 2 .Parameters of tree carry-save adders (2) Maximum number of inputs that can be reduced to two by an h-level tree.

h(n) h(n) = 1 + h h(2) = 0 ( 2 n 3 ) h(n) log 3 2 ( ) n 2 .Parameters of tree carry-save adders (3) Smallest height of the tree carry save adder for n operands.

.

Dadda Trees (1) Wallace trees • Reduce the size of the final Carry Propagate Adder (CPA) • Optimum from the point of view of speed Dadda trees • Reduce the cost of the carry save tree • Optimum (among the CSA trees) from the point of view of area .Wallace vs.

sometimes having a few bits longer CPA adder does not affect the propagation delay significantly (i. Dadda Trees (2) • Wallace reduces number of operands at earliest opportunity – Goal of this is to have smallest number of bits for CPA adder – However. carry-lookahead) • Dadda seeks to reduce the number of FA and HA units – May be at the cost of a slightly larger final CPA .e.Wallace vs.

Wallace Tree .

Dadda Tree .

5-to-3 Parallel Counter 24 23 22 21 20 a b c d e 0 1 1 1 1 1 1 0 0 1 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 0 1 1 1 0 s0 0 1 1 0 0 s1 s2 1 0 0 1 1 a+b+c+d+e = s0+s1+s2 .

Implementation of 1-bit of 5-to-3 parallel counter using single CLB slice of a Virtex FPGA S2 d c b a LUT G ‘0’ S1 d c b a LUT F S0 e .

5-to-3 Parallel Counter a w w b w c d e w w a b c d e w w w w w CSA s2 PC s1 s0 CSA CSA CPA w CSA CPA w y=a+b+c+d+e mod 2w y=a+b+c+d+e mod 2w .Carry Save Adder vs.

. 3. . 4)-counter Unequal columns Fig.17 Dot notation for a (5. 8. 3)-counter .Generalized Parallel Counters Multicolumn reduction . Generalized parallel counter = Parallel compressor (2. 4)-counter and the use of such counters for reducing five numbers to two numbers. (5. 5. 5.

Are you sure?

This action might not be possible to undo. Are you sure you want to continue?

We've moved you to where you read on your other device.

Get the full title to continue

Get the full title to continue listening from where you left off, or restart the preview.

scribd