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EECS 465: Digital Systems Design Lecture Notes #3

Logic Design Using Compound Components: Multiplexers

SHANTANU DUTT
Department of Electrical and Computer Science University of Illinois, Chicago Phone: (312) 355-1314; e-mail: dutt@eecs.uic.edu URL: http://www.eecs.uic.edu/~dutt
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The World of Integrated Circuits (LSI/VLSI)


Full-Custom ASICs Semi-Custom ASICs User Programmable PLA/PAL
(layout aspect; not prog. aspect)

Simple Complex gates (nand/ gates nor/xor/xnor..)

Muxes

PLD PLA/PAL CPLDs

FPGA

Logic Design Using Multiplexers A Transmission Gate ( T-Gate )

A
Out In=B Steering gate.

A When A=1, In is Steered to Out. [I.e., the T-gate conducts] Thus Out = B when A=1 A Out = AB In Out Symbolic for T-gate: A A is the control input (CI) T-gate conducts Normal CI connected to A Bubbled CI connected to A when A=1.

Reversing the connection of A: A A A In Out

bubble CI normal CI

A T-gate conducts when A=0.


Multiplexer (MUX) Design: S I0
S S

A 2:1 MUX. I0

Out Z Out

2:1 I1
MUX

I1
S

Z= I0 when S=0 Z= I1 when S=1


Z S I 0 SI1
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Generalization of the TT: S Z


Z S 1 S 1 1

S Z

0 1

1 1

0 1 1 0

Z S 1 S 0 S

S Z 1 1 0 0 S Z 0 I0 1 I1

Z S 1 S 0

=S
Z S I 0 SI1 is the function
implemented by the above 2:1 MUX. Such a TT in general provides a decomposition of the final function Z into constituent functions I0 & I1

Thus, the 2:1 MUX can also be implemented by logic gates: I0

2:1 MUX : S
I1

I0 I1

2:1
MUX

A 2:1 MUX selects input Ii if S0 = I [If S0 = 0, Z = I0 S0 = 1, Z = I1]

S0

I0 I1 I2 I3

4:1
MUX

The same can be said about a 4:1 MUX: Input Ii is selected (Z=Ii) if S1S0 combination represents the number i in binary.

S1 S0

In general, # of data inputs (Iis) is 2n # of control I/Ps = n

[If S1S0 = 00 (#0), Z = Io S1S0 = 01 (#1), Z = I1 S1S0 = 10 (#2), Z = I2 S1S0 = 11 (#3), Z = I3] S1 S0
0 0 1 1 0 1 0 1

Z
I0 I1 I2 I3
Z S1S 0 I 0 S1S 0 I1 S1S 0 I 2 S1S 0 I 3

I0

I1

2n

:1

I 2 n 1
Sn-1 S1 S0

In general for a 2n:1 MUX with control signals/inputs Sn-1 S1S0 & data inputs I0, , I 2 n 1, Z = Ii when Sn-1 S1S0 combination represents #i in binary.
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Design of MUXes using Divide-&-Conquer


Saw the design of a 2:1 MUX using T-gates, as well as logic gates Messy and expensive to design larger MUXes using a flat TT based approach A 4:1 MUX can be hierarchically constructed using 2:1 MUXes Idea: Divide the selection problem by bits of the select/control variables
These inputs should have different lsb or S0 values, since their sel. is based on S0. All other bits should be equal.

I0 I1

2:1
MUX

Inputs selected are those w/ the same lsb or S0 values. So further selection needs to be based on the non-lsb bits.

S0

2:1
MUX

I2 I3
These inputs should have different lsb or S0 values, since their sel. is based on S0. All other bits should be equal.

2:1
MUX

S1
MSB

I0 I1 I2 I3

4:1
MUX

S0

S0 S1
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LSB of control variables

When S0=0, I0, I2 get selected at the 1st level, i.e., Input w/ 0 in LSB. When S0=1, I1, I3 (LSB=1) get selected at the 1st level. If S0 = 0, I0, I2, become the 0th & 1st inputs to the next level. At the next level, the I/P order # is determined by the rest of the bits of their index after stripping off the LSB. Thus I0 I0 At level 2 I2 I1 0 0 1 0 (# 0) (# 2) strip away for the 2nd level inputs.
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I0 I2 S0=0
01

I0 From level 1 I1
strip

Level 2

Z= I0 of level 2 (I0 of level 1), S1=0. = I1 of level 2 (I2 of level1) if S1=1. Z= I0 of Level 2 (I1 of Level1) if S1=0 = I1 of level 2 (I3 of level 1) if S1=1

I1 I3
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Level 1
strip

I0 I1

2:1
MUX

S0=1

S1

Thus the design works as a 4:1 MUX.

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An 8:1 MUX is designed similarly.


I0

Selected when S0 = 0

2:1
MUX
S0

I0

I1
I2
I0 I1 I2 I3 I4 I5 I6 I7

2:1
MUX
S0

I2

I1 I3 I5 4:1
MUX Z

8:1 MUX Z

I3
I4

I5
S2 S1 S0
These inputs should have different lsb or S0 values, since their sel. is based on S0 (all other remaining, i.e., unselected bit values should be the same). Similarly for other i/p pairs at 2:1 Muxes at this level.

2:1 MUX S0

I4

S2 S1
I6 I7

I6 I7

2:1
MUX

S0
Selected when S0 = 1
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Opening up the 8:1 MUXs hierarchical design


Selected when S0 = 0

I0

2:1
MUX
S0

I0
Selected when S0 = 0, S1 = 1, S2=1

I1
I0 I1 I2 I3 I4 I5 I6 I7

I2

8:1 MUX Z

2:1
MUX
S0

I2

I3
I4

2:1 MUX S1 2:1 MUX S1

I2
2:1 MUX

I6

I6

S2 S1 S0
These inputs should have different lsb or S0 values, since their sel. is based on S0 (all other remaining, i.e., unselected bit values should be the same). Similarly for other i/p pairs at 2:1 Muxes at this level.

I5
I6 I7

2:1 MUX S0

I4

S2

2:1
MUX

I6

S0

Selected when S0 = 0, S1 = 1. These i/ps should differ in S2 These inputs should have different S1 values, since their sel. is based on S1 (all other remaining, i.e., unselected bit values should be the same). Similarly for other i/p pairs at 2:1 Muxes at this level. 13

8:1 MUXs: Input groupings for a different control variable order


Selected when S2 = 1

I0 I4
I0 I1 I2 I3 I4 I5 I6 I7

2:1
MUX
S2

Ix
Selected when S0 = 0, S1 = 1, S2=1

I1

8:1 MUX Z

2:1
MUX
S2

Ix

I5 I2 I6

2:1 MUX S0 2:1 MUX S0

Ix
2:1 MUX

I6

Ix

S2 S1 S0
These inputs should have different lsb or S2 values, since their sel. is based on S2 (all other remaining, i.e., unselected bit values should be the same). Similarly for other i/p pairs at 2:1 Muxes at this level.

2:1 MUX S2

Ix

S1

I3 I7

2:1
MUX

Ix

S2

Selected when S2 = 1, S0 = 0. These i/ps should differ in S1 These inputs should have different S0 values, since their sel. is based on S0 (all other remaining, i.e., unselected bit values should be the same). Similarly for other i/p pairs at 2:1 Muxes at this level. 14

General D&C/Hierarchical Design of a 2n :1 MUX


2:1
S0

I0

2n:1 MUX
I 2 n 1
Sn-1 S0

2:1
S0

2n-1 2:1 MUXes

2n-1 :1 MUX

2:1
S0

Sn-1 S1

Design Strategy:
First select inputs based on S0, using 2n-1 2:1 Muxes; 2n-1 inputs get selected on 2n-1 lines The problem now reduces to that of a 2n-1:1 Mux Continue recursively (to a 2n-2:1, 2n-3:1, ., 4:1, 2:1 Mux design problems) until the final output is designed.
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Using MUXes to Realize Logic Circuits


Example:
f ( A, B, C) m(0,2,6,7)

-- Use A,B,C as control inputs to an 8:1 MUX.


-- Treat the data inputs I0, , I7 as possible minterms of f:

Input Ii is a minterm if #i appears in the m notation of f.


If Ii is a minterm of f, it should be connected to a 1, otherwise it should be connected to a 0.
1 0 1 0 0 0 1 1
I0 I1 I2 I3 I4 I5 I6 I7

8:1 MUX
S2 S1 S0 B C

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A 3-variable function can always be implemented by only an 8:1 MUX. Interestingly, a 3-var. function can also always be implemented by only a 4:1 MUX (assuming vars & their complements are avail.) Example f(A,B,C) = m(0,2,6,7) Select any 2 variables, say, A,B, for the 2 control inputs In a 3-var. K-map, group together squares into 2-squares in which the other variable C varies, but A,B remains AB constant. 00 01 11 10 C Form implicants 2-square 0 1 1 1 only within 2-squares and write out the 1 1 function
ABC
A BC
AB

f ( A B )C ( A B)C ( AB ) 0 ( AB ) 1

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The function now is in terms of combinations of A, B ( A B , A B, etc.) ANDed with either C, C , 1, or 0


Note: 0 is ANDed with an A,B combination (e.g., AB above) when the 2-square corresponding to that combination does not have any 1s, i.e., when none of the product terms obtained from the K-map in the above manner has that combination of A, B in them.

Connect either C, C , 1, 0 to the appropriate data input corresponding to the A,B combination they are ANDed with in the expression for f. Thus f ( A B )C ( A B)C ( AB ) 0 ( AB ) 1 Note that a 4:1 MUX implements the function
f ( A B ) I 0 ( A B ) I1 ( AB ) I 2 ( AB ) I 3 ;

Thus for the above f, I 0 C , I1 C I 2 0, and I 3 1

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C C 0 1

0 1 2 3

4:1 MUX
S1 S0 A B

A B 0 0 1 1 0 1 0 1

f
C C

0 1

-- A general n-variable function f(An-1, An-2, , A0)


Implementation possible using a 2n: 1 MUX (w/o requiring any extra gates)? Yes. Implementation possible using a 2n-1: 1 MUX (w/o requiring any extra gates) ? Yes.
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E.g.: A 4-var. function f(A,B,C,D) Choose A, B, C as the control inputs


AB CD 00
00 01 11 10

ABC D
01 11 10

AB C

1
1 1 1
A BC

D D

A B CD

1 1 0 0 0

0 1 2 3 4 5 6 7

A B

f ( A B C ) D ( A B C ) D ( A BC ) 0 ( A BC) 1 ( AB C ) 1 ( AB C ) 0 ( ABC ) 0 ( ABC) 0


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-- In general, a 2i : 1 MUX, where i < n-1, can be used to implement an n-var. function f(An-1, ,A0) by choosing any i variables, say, Ai-1, , A0 ( This is just an example of i variables; you can choose any i of the n variables) as the control inputs of the MUX. However, for i < n-1, extra logic gates may be required.

-- Then express f in terms of all combinations of Ai-1, , A0 as


f ( Ai 1 Ai 2 A0 ) g0 ( An 1 , , Ai ) ( Ai 1 Ai 2 A0 ) g1 ( An 1 , , Ai ) ( Ai 1 Ai 2 A0 ) g2i 1 ( An1, , Ai )

Where gk ( An1, , Ai ) is a function of An-1,,Ai that ANDs with the kth product term of variables Ai-1, , A0 that represents the binary # k, 0 k 2i 1
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-- Thus we get the implementation:


g0(An-1,, Ai+1)
I0

2i:1 MUX
g 2i 1 ( An 1 , , Ai 1 )

I 2 i 1
Ai-1 A0

Where each gk may need extra logic gates for its implementation.

-- The trick is to choose the right i variables so that the total # of logic gates needed for the gks is minimum.

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E.g.:

4-var. function f(A,B,C,D) ; n=4. Let i=2


AB CD 00
00

AB C
01 11 10

1 1 1

ABD

01 11 10

4-squares where A,B=constant.

1
A BC

-- For i=2 (2 control variables from A,B,C,D for a 4:1 MUX), the K-map needs to be partitioned into groups of 4-squares, such that within each 4-square the 2 control variables are constant.
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-- Note that PIs can only be formed within each 4-square, i.e., groups

of squares in which the control vars. are constant (constant areas). -- To min. # of gates, choose the 2 control vars such that the largest-size implicants & the smallest # of them can be formed in its set const. areas. -- A study of the 1s in the above K-map tells us that this is achieved by the set of 4-squares that are the columns of the K-map, i.e., for control variables A, B. -- Then, in each constant-area, form the SOP sub-expression for all the MTs in that area, just like in a full K-Map (i.e., for all PIs in each area determine and select all EPIs in that area, cover remaining MTs in tha area by the least-cost set of the remaining PIs). -- Grouping 1s only within the constant areas (4-squares in this ex.) we get over all constant areas, i.e., all combinations of A, B, the expression:
f ( A B )( D ) ( A B)(C ) ( AB )(C ) ( AB )( 0) D
0 1 2 3

Implementation: C No logic gates needed! C (NOTE: This will not 0 always be the case)

4:1 MUX
S 1 S0
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A B

-- If we had chosen A,C as the control variables, then the 4-squares would have looked as follows
AB CD 00
00

AB C
01 11 10

ABC D

01 11 10

1
1 1 1
A BC

A CD

-- Grouping 1s only within the 4-squares, we get 4 terms A B C D , A CD , A BC , and AB C: all are essential (within their constant areas)

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-- We thus obtain f in terms of all combinations of A, C as


f A B C D A CD A BC AB C
( A C )( B D ) ( A C )( D B) ( AC )( B ) ( AC )( 0)

I0

I1
0 1

I2

I3

B
D B D

B 0

2 3

4:1 MUX
S1 S0 A C

-- Thus choosing A,C as control variables, results in 2 extra gates compared to choosing A, B.
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