module module_name (port_list); port declarations 

data type 

declarations circuit functionality 

timing specifications 

endmodule 

Functional 
Functional 

nets 
Block: 
nets 
Block: 
nets 
FA1 
FA2 

(nets) 
(nets) 
reg [7 : 0]






examples : 
(decimal 15) 
’h15 
(decimal 21, hex 15) 
Arithmetic 
Pair of operands 
word 
Bitwise 
Pair of operands 
word 
Reduction 
Single operand 
bit 
Logical 
Pair of operands 
bit 
Relational 
Pair of operands 
bit 
Shift 
Single operand 
word 
+ 
Arithmetic + 
C = A + B 
 
Arithmetic  
C = A  B 
* 
Arithmetic * 
C = A * B 
/ 
Arithmetic / 
C = A / 
% 
Modulus 
C = A % B 
Operator 
Argument 
Result 
Arithmetic 
Pair of operands 
word 
OperatorOperation 
Example 

& 
Reduction And 
C = &(A) 
~& 
Reduction Nand 
C = ~&(A) 
 
Or 
C = (A) 
~ 
Reduction Nor 
C = ~(A) 
^ 
Reduction ExclusiveOr 
C = ^(A) 
~^ or ^~ Reduction ExclusiveNor 
C = ~^(A) 

OperatorArgument 
Result 

ReductionSingle operand 
bit 
! 
Logical negation 
if(!A) 
&& 
Logical and 
if((A) && (B)) 
 
Logical or 
if((A)  (B)) 
== 
Logical equality 
if (A == B) 
!= 
Logical inequalityif (A != B) 

OperatorArgument 
Result 

LogicalPair of operands 
bit 
OperatorOperation 
Example 

> 
Greater Than 
if (A > B) 
< 
Less Than 
if (A < B) 
>= 
Greater Than or Equal if (A >= B) 

<= 
Less Than or Equalif (A <= B) 

OperatorArgument 
Result 

RelationalPair of operands 
bit 
<< 
Left Shift 
A = A << 1 
>> 
Right Shift 
A = A >> 3 
?: 
Conditional 
Y = A? C:D; 
or 
Event Or 
always @ (clk or sel) 

B = A; 

C 
= B; 

D 
= C; //A=B=C=D 


B <= A; 

C 
<= B; 

D 
<= C; //shift 
Level 
Description 
0 
Logic value 0 
1 
Logic value 1 
z 
Tristate (high impedance) 
x 
Unknown value 
Radix 
Description 

d 
decimal 

b 
binary 

h 
hexadecimal 

o 
octal 

0 
the number 0 

10 
the decimal number 10 

′b10 
the binary number 10 

′h10 
the hex number 10 

4′ b100 
the binary number 0100 

8′b1000_0011 
underscore _ can be inserted for readability 

8′hfx 
equivalent to 8′b1111_xxxx 
Time 
Input 
Output 

(ns) 
A B C 
y e x 

<0 
0 0 0 
1 
0 1 

0 
1 
1 
0 1 



0 
0 1 



0 
0 1 



0 
1 0 



0 
1 0 



0 
1 
1 
input 
a, b; 
output 
sum, c_out; 
Add_half 
M1 ( w1, w2, a, b ); 

Add_half 
M2 ( sum, w3, w1, c_in ); 
// child module 
or ( c_out, w2, w3 ); 
// primitive instantiation 
module adder4 (in1, in2, sum, c_out); input [3:0] in1, in2; output [3:0] sum; output c_out; 
wire c0 , c1 , c2; fulladd u1 (in1[0],in2[0], 0,sum[0],c0); fulladd u2 (in1[1],in2[1],c0,sum[1],c1); fulladd u3 (in1[2],in2[2],c1,sum[2],c2); fulladd u4 (in1[3],in2[3],c2,sum[3],c_out); 
endmodule 
module fulladd (in1, in2, carryin, sum, carryout); input in1, in2, carryin; output sum, carryout; 
assign {carryout, sum} = in1 + in2 + carryin; 
endmodule 
In1[0] 

In2[0] 

In1[1] 

In2[1] 

In1[2] 

In2[2] 

In1[3] 

In2[3] 

c_in = 0 



adder 

sum[0] 
adder 

sum[1] 
adder 

sum[2] 
adder 

sum[3] 
C_out