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prim

• #  The notation

A =
1’b0;
means signal A is one bit with value zero.

# Verilog Module

• ##  Communicate with outside through ports

### xor (sum, a, b); nand (c_out_bar, a, b); not (c_out, c_out_bar); endmodule

Port list is optional
a
Achieve hardware
encapsulation
sum
b
c_out_bar
c_out

a
sum
b
c_out

• # Design a Full Adder

## sum FA= (a  b)  c_in c_out FA= (a  b) • c_in + a • b

c_in
(a  b)  c_in
a
ab
(ab)•c_in
b
a•b

# (a  b) • c_in + a • b

sum
c_in
(a  b)  c_in
w1
w3
a
ab
(ab)•c_in
c_out
w2
b
a•b

• 4 bit Ripple
Full
Full
Full
Full
XOR
AND
OR
XOR
AND
OR
XOR
AND
OR
XOR
AND
OR

# Hierarchical Modeling Example

## endmodule

 In1[0] In2[0] In1[1] In2[1] In1[2] In2[2] In1[3] In2[3]

C_out

• # Behavioral Modeling

• ##  No specific hardware intent

For the purpose of synthesis, as well as simulation
output1,
..
,
outputn
input1,
..
,
inputn
if (input1)
for (j=0, j<8, j=j+2)
#5 output1 = 1’b0;
else
for (j=1, j<8, j=j+2)
#5 output1 = 1’b1;

• #  For the purpose of synthesis

Higher-level Component
output1
input1
Lower-level
Component1
Lower-level
Component1
inputn
outputn