Computer Organization and Architecture + Networks

Lecture 2 Computer Architecture Basics
• • • • • Computer Components Computer Function Interconnection Structures Bus Interconnection PCI

Learning Objectives
• Understand the basic elements of an instruction cycle and the role of interrupts. • Describe the concept of interconnection within a computer system • Understand the difference between synchronous and asynchronous bus timing • Present an overview of PCI

Computer Components
• ‗Hardwired Program‘ – hardware program constructed by connecting various logic components to store binary data and perform arithmetic and logical operations • Concept of ‗Hardwired Program‘
—Hardwired systems are inflexible — General purpose hardware can do different tasks, given correct control signals — Instead of re-wiring, programmer supplies a new set of control signals

a different set of control signals is needed Data Sequence of Arithmetic and Logic Functions Results Programming in Hardware . an arithmetic or logical operation done — For each operation.Computer Components • What is a program? — A sequence of steps —For each step.

Computer Components • Software Program — With the general-purpose hardware. there is no need to rewire the hardware but only to provide a new sequence of codes — Software – a sequence of codes/instructions Instruction codes Data Instruction interpreter CPU Control signals General Purpose Arithmetic and Logic Functions Programming in Software Results .

Components of Computer (Von Neumann Machine) • The Control Unit and the Arithmetic and Logic Unit constitute the Central Processing Unit • Data and instructions need to get into the system and results out — Input/output • Temporary storage of code and results is needed — Main memory (store data and instructions) .

Computer Components: Top Level View Program Execution To store the address in memory for the next read or write To store data to be written/receives from the memory Specifies a particular I/O device Exchange data between I/O module & CPU .

Computer Function • Basic Function of Computer – executes program (a set of instructions stored in the memory) – done by the processor • Two steps for instruction processing: 1.unrecoverable error .program instruction halts computer .machine is turned off . Fetch – processor reads (fetches) the instructions from memory one at a time 2. Execute – processor executes each instruction • Instruction Cycle – the processing for a single instruction .

Computer Function – Instruction Fetch and Execute Fetch Cycle • Program Counter (PC) holds address of next instruction to fetch • Processor fetches instruction from memory location pointed to by PC • Increment PC — Unless told otherwise • Instruction loaded into Instruction Register (IR) • Processor interprets instruction and performs required actions .

jump • Combination of above .Computer Function – Instruction Fetch and Execute Execute Cycle – 4 main categories of instruction‘s execution: • Processor-memory —data transfer between CPU and main memory • Processor I/O — Data transfer between CPU and I/O module • Data processing — Some arithmetic or logical operation on data • Control —Alteration of sequence of operations — e.g.

Computer Function – Instruction Fetch and Execute Example of Program Execution • PC/IR/AC = internal CPU registers —PC – Program Counter (Address of instruction) — IR – Instruction Register (Instruction being executed) — AC – Accumulator (Temporary Storage) .

212 = 4096 (4K) words of memory (address) 0 1 15 Magnitude Integer Format Program counter (PC) = Address of instruction Instruction register (IR) = Instruction being executed Accumulator (AC) = Temporary storage 0001 = Load AC from memory 0010 = Store AC to memory 0101 = Add to AC from memory Internal CPU registers (decimal value = 1) (decimal value = 2) (decimal value = 5) Partial list of opcodes  Add the content of 940 and 941 and store results in 941 (3 fetch + 3 execute cycles = 3 instruction cycles) .Example of Instruction and Data 0 3 4 15 Opcode Address Instruction Format 4 bits  24 = 16 different opcodes.

Example of Program Execution Add the content of 940 and 941 and store results in 941 (3 fetch + 3 execute cycles = 3 instruction cycles)) PC contains address of 1st instruction (300) •Loaded into IR and the PC is incremented •Process involves the use of MAR and MBR – (but ignored) .

Example of Program Execution 1 •The first 4 bits in the IR indicate that the AC is to be loaded •The remain 12 bits specify the address (940) from which data is to be loaded into AC .

PC is incremented .Example of Program Execution •Next instruction (5941) is fetched from location 301 .

Example of Program Execution 2 •Old contents of the AC and the contents of 941 are added •Result is stored in the AC .

Example of Program Execution Next instruction (2941) is fetched from location 302 .PC is incremented .

Example of Program Execution 3 The contents of the AC are stored in location 941 .

A stores the sum of the contents of memory locations B and A into memory location A .Example of Program Execution Three instruction cycles -Each consists of a fetch cycle and an execute cycle -Execution cycle for particular instruction may involve more than one reference memory + an instruction may specify an I/O operation. Task: PDP-11 instruction – ADD B.

State Diagram • Any given instruction cycle. Data operation address fetch (of) (do) calculation ––fetch perform the (oac) operand the operation – determine from in memory/read the address of g. Operand store (os) write result into memory or via I/O a. if of os iod do iac oac oac c. Instruction b. f. Instruction fetch address (if) calculation – read instruction (iac) – determine from its memory the instruction and determine ofexecuted operation and type of the from instruction operand I/O of address location into next the instruction processortype to be operand(s) to be used . operation decoding (iod) – analyze d. some states may be null and others may be visited more than once.Instruction Cycle . e.

g.g. division by zero  Timer • Generated by internal processor timer • Used in pre-emptive multi-tasking  I/O • Generated from I/O controller (to signal completion/error)  Hardware failure • e. I/O) may interrupt normal sequence of processing • Provided to improve processing efficiency • Classes of Interrupts  Program • e.g. memory parity error/power failure .Interrupts • Mechanism by which other modules (e. overflow.

prepare for the actual I/O operation • The actual I/O command • A sequence of instruction ⑤-to complete the operation The user program is stopped at the point of the WRITE call for some considerable period of time .Program Flow Control • The user program performs a series of WRITE calls interleaved with processing • ①.sequences of instructions that do not involve I/O • WRITE calls are to an I/O program that is a system utility and that will perform the actual I/O operation • I/O program – 3 sections • A sequence of instruction ④.②.③ .

the processor can be engaged in executing other instructions while an I/O operation is in progress.Program Flow Control • With interrupts. • The WRITE calls – invoke the I/O program – return to user program • I/O module send an interrupt request signal (interrupt handler) – respond by processor and ready to service the particular I/O device • Short I/O wait – time required for the I/O operation is shorter than in the user program .

Program Flow Control • Long I/O wait – time required for the I/O operation is longer than in the user program • The user program reaches the 2nd WRITE call before the I/O operation spawned by the 1st WRITE call – user program hung up • New WRITE call is needed to start new I/O operation .

Interrupt Cycle • Added to instruction cycle • Processor checks for interrupt — Indicated by an interrupt signal • If no interrupt. fetch next instruction • If interrupt pending: — Suspend execution of current program — Save context — Set PC to start address of interrupt handler routine — Process interrupt — Restore context and continue interrupted program .

Transfer of Control via Interrupts Interrupts: an interruption of the normal sequence of execution – execution resumes when interrupts processing is completed .

Instruction Cycle with Interrupts Interrupt cycle – processor checks to see if any interrupts have occurred. No interrupt – processor proceeds to the fetch cycles and fetched the next instruction . indicated by the presence of an interrupt signal.

Program Timing Short I/O Wait The time required for the I/O operation is relatively short. less than the time to complete the execution of instructions between write operations in the user program .

Program Timing Long I/O Wait A gain in efficiency because part of the time during which I/O operation is underway overlaps with the execution of user instructions .

Instruction Cycle (with Interrupts) State Diagram .

processor returns to previous interrupt .Multiple Interrupts • Disable interrupts — Processor will ignore further interrupts whilst processing one interrupt — Interrupts remain pending and are checked after first interrupt has been processed — Interrupts handled in sequence as they occur • Define priorities — Low priority interrupts can be interrupted by higher priority interrupts —When higher priority interrupt has been processed.

Sequential Interrupts are handled in strict sequential order Drawbacks – does not take into account relative priority or time-critical needs .Sequential Multiple Interrupts .Multiple Interrupts .

Multiple Interrupts – Nested Multiple Interrupts .Nested Defines priorities for interrupts and to allow an interrupt of higher priority to cause a lower-priority interrupt handler to be itself interrupted .

info is placed on the system stack and execution continues at the printer ISR ④communication ISR is completed. and finally return to the user . printer ISR is resumed. and execution continues at the communications ISR ①begins ②Printer interrupt occurs. the printer ISR is executed. communications interrupt occurs – higher priority than printer Printer ISR is interrupted. higher-priority disk interrupt and control transfers to the disk ISR ⑤only when routine is completed.Time Sequence of Multiple Interrupts (ISR – Interrupt Service Routine) ③while executing. it state is pushed onto the stack. But.

Interconnection • All the units must be connected • Different type of connection for different type of unit — Memory — Input/Output —CPU .

Computer Modules • Types of exchanges that are needed by indicating the major forms of input and output Data can be read and written to Memory .

Computer Modules • Types of exchanges that are needed by indicating the major forms of input and output 2 operations: Read and Write. Send Interrupts .

Computer Modules • Types of exchanges that are needed by indicating the major forms of input and output Read data and instructions and writes our data. Control signal to control operation of the system . Receives and acts on interrupts.

Memory Connection • Receives and sends data • Receives addresses (of locations) • Receives control signals — Read — Write —Timing .

Input/Output Connection(1) • Similar to memory from computer‘s viewpoint • Output —Receive data from computer — Send data to peripheral • Input —Receive data from peripheral — Send data to computer .

port number to identify peripheral • Send interrupt signals (control) .g.Input/Output Connection(2) • Receive control signals from computer • Send control signals to peripherals —e.g. spin disk • Receive addresses from computer — e.

CPU Connection • • • • Reads instruction and data Writes out data (after processing) Sends control signals to other units Receives (& acts on) interrupts .

Unibus (DEC-PDP) .g.Buses Interconnection • There are a number of possible interconnection systems • Single and multiple BUS structures are most common • e.g. Control/Address/Data bus (PC) • e.

What is a Bus? • A communication pathway connecting two or more devices • Usually broadcast • Often grouped — A number of channels in one bus —e. 32 bit data bus is 32 separate single bit channels • Power lines may not be shown .g.

16. 64 bit .Data Bus • Carries data —Remember that there is no difference between ―data‖ and ―instruction‖ at this level • Width is a key determinant of performance — 8. 32.

g. CPU needs to read an instruction (data) from a given location in memory • Bus width determines maximum memory capacity of system —e.Address bus • Identify the source or destination of data • e. 8080 has 16 bit address bus giving 64k address space .g.

Control Bus • Control and timing information — Memory read/write signal —Interrupt request — Clock signals .

Bus Interconnection Scheme
Three functional group – data, address, and control lines (+ power distribution lines – supply power to the attached modules)

Path for moving data To designate the source between system or destination of the module data on the data bus

To control the access to and the use of the data and address lines

Big and Yellow?
• What do buses look like?
— Parallel lines on circuit boards —Ribbon cables — Strip connectors on mother boards
– e.g. PCI

— Sets of wires

Single Bus Problems
• Lots of devices on one bus leads to:
— Propagation delays
– Long data paths mean that co-ordination of bus use can adversely affect performance – If aggregate data transfer approaches bus capacity

• Most systems use multiple buses to overcome these problems

Traditional (ISA) (with cache) Expansion Bus – buffers data transfer between the system bus and the I/O controllers .

High Performance Bus High-Speed Bus – to compensates for loss of performance when higher performance I/O devices are attached to the expansion bus .

Elements of Bus Design .Bus Types • Dedicated — Separate data & address lines • Multiplexed — Shared lines — Address valid or data valid control line —Advantage .fewer lines — Disadvantages – More complex control – Ultimate performance .

Elements of Bus Design . CPU and DMA controller Only one module may control bus at one time Arbitration may be centralised or distributed 2 types of Arbitration —Centralised – single hardware device controlling bus access —Distributed – each module may claim the bus – Control logic access on all modules .Bus Arbitration • • • • • More than one module controlling the bus e.g.

Elements of Bus Design .Timing • Co-ordination of events on bus • Synchronous —Events determined by clock signals — Control Bus includes clock line upon which a clock transmits a regular sequence of alternating 1s and 0s of equal duration — A single 1-0 transmission is a bus cycle or clock cycle — All devices can read clock line — Usually sync on leading edge —Usually a single cycle for an event .

Synchronous Timing Diagram Occurrence of events is determined by a clock ①Processor places a memory address on the address line + various status line ④a Processor reads the data & drops the read signal ②Once address line have stabilized. processor issues an address enable signal ④Memory recognizes the address & places data on the data line ③READ operation: Processor issues a read command ⑤WRITE operation: Processor puts the data on the data lines & issues a write command after data lines have ⑤a Memory copies the info from data lines during the 3 rd clock cycle stabilized .

master (processor) removes the address info .Asynchronous Timing – Read Diagram Occurrence of one events on a bus depends on occurrence of a previous event ①Address placed by processor on the bus ②After signals (address+status) are stabilize. memory module asserts (inform) the acknowledged line that data is available ⑥Causes memory to drop the data & acknowledge lines ⑦Acknowledge line is dropped. it de-asserts (stops) the read signals ③Memory decodes the address & places the data on the data line ④Once data lines have stabilized. read command is issued ⑤Once the processor has read the data.

Asynchronous Timing – Write Diagram ①Processor places the data on the data line at the same time that us puts signals on the status and address lines ③Master drops the WRITE signal and memory module drops the acknowledge signal ②Memory module responds to the WRITE command by copying the data from the data lines and then asserting the acknowledge line .

PCI Bus • Peripheral Component Interconnection • Intel released to public domain • High bandwidth. processor independent bus that functions as a peripheral bus • Gives better performance for high-speed I/O subsystems (network interface controllers/graphic display adapters) • Current standard allows 64 data lines • Economical and needs very few chips to implement • May be configured as a 32.or 64-bit bus .

PCI Bus Lines (required) • Systems lines — Including clock and reset • Address & Data — 32 time mux lines for address/data — Interrupt & validate lines • Interface Control • Arbitration — Not shared —Direct connection to PCI bus arbiter • Error lines .

PCI Bus Lines (Optional) • Interrupt lines — Not shared • Cache support • 64-bit Bus Extension — Additional 32 lines —Time multiplexed — 2 lines to enable devices to agree to use 64-bit transfer • JTAG/Boundary Scan — For testing procedures .

PCI Commands • Transaction between initiator (master) and target • Master claims bus • Determine type of transaction — e. I/O read/write • Address phase • One or more data phases .g.

PCI Read Timing Diagram .