8085 Microprocessor:

Architecture & Support Components

Contents
Pin diagram of 8085

8085 Operations
Architecture of 8085 8085 Communication with Memory

Pinout Diagram of 8085

U7

A 40-pin IC

Six groups of signals Address Bus Data Bus Control and Status pins Power Supply & frequency signals Externally initiated Signals Serial I/O ports

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

X1 X2 RST-OT SOD SID TRAP RST 7.5 RST 6.5 RST 5.5 INTR INTA AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 VSS

VCC HOLD HLDA CLKO RST-IN READY IO/M S1 RD WR ALE S0 A15 A14 A13 A12 A11 A10 A9 A8

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

8085

Logic Pinout of 8085

U8 40 20 5 4 6 9 8 7 10 39 35 36 11 38 3 37 VCC VSS SID SOD TRAP RST 5.5 RST 6.5 RST 7.5 INTR HOLD READY RST-IN INTA HLDA RST-OT CLKO 8085

Serial I/O ports Externally initiated signals

Control & Status

ALE WR RD IO/M S0 S1

30 31 32 34 29 33

Control & Status

Address Bus

Power Supply & frequency

Data Bus

1 2

X1 X2

AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 A8 A9 A10 A11 A12 A13 A14 A15

12 13 14 15 16 17 18 19 21 22 23 24 25 26 27 28

8085 Operations
Microprocessor Initiated Operations

Internal Operations
Peripheral/Externally Initiated Operations

Microprocessor Initiated Operations

Memory Read

Memory Write
I/O Read I/O Write

Internal Operations
Store 8-bit data

Perform Arithmetic and Logic Operations

Test for conditions Sequence the execution of instructions Store/Retrieve data from stack during

execution

Peripheral/Externally Initiated Operations

Reset

Interrupt
Ready Hold

Architecture of 8085
Power Supply a +5V DC power supply

Maximum clock frequency of 3MHz

8-bit general purpose microprocessor 16-bit Address Bus

Capable of addressing 64K of memory

Architecture of 8085

Architecture 0f 8085 Cont

ALU Interrupt Control

Timing and Control Unit

General Purpose

Serial I/O Control

Address Bus Data Bus

Registers Program Status word Program Counter Stack Pointer Instruction Register and Decoder

Architecture 0f 8085 Cont

Arithmetic Logic Unit (ALU)

8085 has 8-bit ALU Performs arithmetic & Logic operations on data
Generates timing and control signals

Timing & Control Unit

General Purpose Registers

8-bit registers (B,C,D,E,H,L) 16-bit register pairs (BC, DE, HL,PSW)

Architecture 0f 8085 Cont

Program Status Word (PSW)

Accumulator and Flag Register can be combined as a register pair called PSW Instruction fetched from memory is stored in Instruction register (8-bit register) Decoder decodes the instruction and directs the Timing & Control Unit accordingly

Instruction Register and Decoder

Architecture 0f 8085 Cont

Interrupt Control

8085 has 5 interrupt signals

INTR general purpose interrupt RST 5.5 Restart Interrupts RST 6.5 RST 7.5 TRAP non-maskable interrupt

The interrupts listed above are in increasing order of priority

Architecture 0f 8085 Cont

Serial I/O Control

8085 has two signals for serial communication SID Serial Input Data SOD Serial Output Data

Architecture 0f 8085 Cont

Address Bus Used to address memory & I/O devices 8085 has a 16-bit address bus
Higher-order Address Lower-order Address

A15 A14 A13 A12 A11 A10 A9 A8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

Data Bus

Data Bus Used to transfer instructions and data 8085 has a 8-bit data bus

8085 Communication with Memory

Involves the following three steps
1.
2. 3.

Identify the memory location (with address) Generate Timing & Control signals Data transfer takes place

Example: Memory Read Operation

3 2

Timing Diagram

Demultiplexing Address/Data Bus

8085 identifies a memory location with its 16

address lines, (AD0 to AD7) & (A8 to A15) 8085 performs data transfer using its data lines, AD0 to AD7 Lower order address bus & Data bus are multiplexed on same lines i.e. AD0 to AD7. Demultiplexing refers to separating Address & Data signals for read/write operations

Need for Demultiplexing

RD

A8-A15
20H

AD0-AD7 8085
05H

Memory
4FH 2005H

Need for Demultiplexing

The 16-bit address of the memory location

must be applied to the memory chip for the whole duration of the memory read/write operation. Lower-order address needs to be saved before microprocessor uses it for data transfer

8085 Interfacing with Memory chips

Address Address

8085

Data

Memory

Data

Memory

Interface

Chip

Control

Control

8085 Interfacing with Memory chips

Data

74LS373

Memory
A0 A7

8085

AD0-AD7 ALE A8-A15

Chip

A8-A15

Control

Memory Interface

8085 Interfacing with Memory chips

Data

74LS373

Program
A0 A7

8085

AD0-AD7 ALE

Memory
CS RD

A8-A15
IO/M RD

A8-A15

Memory Interface

U3 U1 36 1 2 5 6 9 8 7 10 11 29 33 39 35 38 4 37 3 RST-IN X1 X2 SID TRAP RST 5.5 RST 6.5 RST 7.5 INTR INTA S0 S1 HOLD READY HLDA SOD CLKO RST-OT 8085 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 ALE A8 A9 A10 A11 A12 A13 A14 A15 IO/M RD 12 13 14 15 16 17 18 19 30 21 22 23 24 25 26 27 28 34 32 3 4 7 8 13 14 17 18 11 U2 D0 D1 D2 D3 D4 D5 D6 D7 G Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 OC 2 5 6 9 12 15 16 19 1 10 9 8 7 6 5 4 3 A0 A1 A2 A3 A4 A5 A6 A7 O0 O1 O2 O3 O4 O5 O6 O7 11 12 13 15 16 17 18 19

74LS373 25 24 21 23 2 26 27 1 20 22 A8 A9 A10 A11 A12 A13 A14 A15 CE OE/VPP

31

WR

27C512A

Memory Mapping
8085 has 16-bit Address Bus

The complete address space is thus given by

the range of addresses 0000H FFFFH The range of addresses allocated to a memory device is known as its memory map

Memory map: 64K memory device

Address lines required: 16 (A0 A15)

Memory map: 0000H - FFFFH

Memory map: 32K memory device

Address lines required: 15 (A0 A14) Memory map: depends on how address line

A15 is connected

U1 36 1 2 5 6 9 8 7 10 11 29 33 39 35 38 4 37 3 RST-IN X1 X2 SID TRAP RST 5.5 RST 6.5 RST 7.5 INTR INTA S0 S1 HOLD READY HLDA SOD CLKO RST-OT 8085 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 ALE A8 A9 A10 A11 A12 A13 A14 A15 IO/M
WR

U2 12 13 14 15 16 17 18 19 30 21 22 23 24 25 26 27 28 1 34 2 32 74LS32 22 1 U5A 3 3 4 7 8 13 14 17 18 11 D0 D1 D2 D3 D4 D5 D6 D7 G Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 OC 2 5 6 9 12 15 16 19 1 10 9 8 7 6 5 4 3

U4 A0 A1 A2 A3 A4 A5 A6 A7 O0 O1 O2 O3 O4 O5 O6 O7 11 12 13 15 16 17 18 19

74LS373 25 24 21 23 2 26 27 20 A8 A9 A10 A11 A12 A13 A14 CE OE VPP 27C256

RD

Memory device is selected only if IO/M = 0 & A15 = 0

31

 So the memory map is

A15 A14 A13 A12 0 0 0 0
A11 to A0 0. 0 0

= 0000H to

A15 A14 A13 A12

A11 to A0

1. 111

= 7FFFH

Interfacing I/O devices with 8085

Peripheral-mapped I/O & Memory-mapped I/O

Interfacing I/O devices with 8085

I/O Interface I/O Devices

System Bus

8085
Memory Interface Memory Devices

Techniques for I/O Interfacing

Memory-mapped I/O

Peripheral-mapped I/O

Memory-mapped I/O
8085 uses its 16-bit address bus to identify a

memory location Memory address space: 0000H to FFFFH 8085 needs to identify I/O devices also I/O devices can be interfaced using addresses from memory space 8085 treats such an I/O device as a memory location This is called Memory-mapped I/O

Peripheral-mapped I/O
8085 has a separate 8-bit addressing scheme

for I/O devices I/O address space: 00H to FFH This is called Peripheral-mapped I/O or I/O-mapped I/O

8085 Communication with I/O devices

Involves the following three steps

Identify the I/O device (with address) 2. Generate Timing & Control signals 3. Data transfer takes place
1.

8085 communicates with a I/O device only if

there is a Program Instruction to do so

1.Identify the I/O device (with address)

1. Memory-mapped I/O (16-bit address)

2. Peripheral-mapped I/O (8-bit address)

2.Generate Timing & Control Signals

Memory-mapped I/O

Reading Input: IO/M = 0, RD = 0 Write to Output: IO/M = 0, WR = 0 Reading Input: IO/M = 1, RD = 0 Write to Output: IO/M = 1, WR = 0

Peripheral-mapped I/O

3. Data transfer takes place

8085 Communication with I/O devices

Involves the following three steps

Identify the I/O device (with address) Generate Timing & Control signals Data transfer takes place

8085 communicates with a I/O device only if

there is a Program Instruction to do so

Peripheral I/O Instructions

IN Instruction

Inputs data from input device into the accumulator It is a 2-byte instruction Format: IN 8-bit port address Example: IN 01H

 OUT Instruction

Outputs the contents of accumulator to an output device It is a 2-byte instruction Format: OUT 8-bit port address Example: OUT 02H

----------Example Program--------- WAP to read a number from input port (port

address 01H) and display it on ASCII display connected to output port (port address 02H) IN 01H ;reads data value 03H (example)into ;accumulator, A = 03H MVI B, 30H;loads register B with 30H ADD B ;A = 33H, ASCII code for 3 OUT 02H ;display 3 on ASCII display

Memory-mapped I/O Instructions

I/O devices are identified by 16-bit addresses 8085 communicates with an I/O device as if it

were one of the memory locations Memory related instructions are used For e.g. LDA, STA LDA 8000H

Loads A with data read from input device with 16-bit address 8000H

STA 8001H Stores (Outputs) contents of A to output device with 16-bit address 8001H

----------Example Program--------- WAP to read a number from input port (port

address 8000H) and display it on ASCII display connected to output port (port address 8001H) LDA 8000H;reads data value 03H (example)into ;accumulator, A = 03H MVI B, 30H;loads register B with 30H ADD B ;A = 33H, ASCII code for 3 STA 8001H;display 3 on ASCII display