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# Meenakshi Sood

Sequential Circuits
Combines combinational logic with storage Remembers state, and changes output (and state)

## based on inputs and current state

Digital signals are received and interpreted by a digital system an control outputs are generated in accordance with the sequence in which the input signals are received. Inputs

## Combinational Logic Circuit

Outputs Storage Elements

State Machine
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Sequential Circuits
Models for representing sequential circuits
Finite-state machines (Moore and Mealy) Representation of memory (states) Changes in state (transitions)

## Basic sequential circuits

Shift registers Counters

Design procedure
State diagrams State transition table Next state functions

## Definition of a State Machine

All programmable logic designs can be specified in Boolean

form. However some designs are easier to conceptualize and implement using non-Boolean models. The State Machine model is one such model

A state machine represents a system as a set of states, the transitions between them, along with the associated inputs and outputs
So, a state machine is a particular conceptualization of a

## Finite State Machines

Any Circuit with Memory Is a Finite State Machine
Design of FSMs Involves Defining states Defining transitions between states Optimization / minimization Above Approach Is Practical for Small FSMs Only

## Finite State Machine

A description of a system with the following components:
1. 2. 3. 4. 5.

A finite number of states A finite number of external inputs A finite number of external outputs An explicit specification of all state transitions An explicit specification of what determines each external output value

## Often described by a state diagram.

Inputs trigger state transitions. Outputs are associated with each state (or with each transition).

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FSM structure

Synchronous design
Controlled by clock(s).
State changes at time determined by the clock. Inputs to registers settle in time for state change. Primary inputs settle in time for combinational delay

through logic.

## Machine state is determined solely by registers.

Dont have to worry about timing constraints, events

## outside the registers.

The Clock
Frequently, a clock circuit triggers transition from one state to the next.
1

One Cycle

time

At the beginning of each clock cycle, state machine makes a transition, based on the current state and the external inputs.
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## Finite State Machines

A finite state machine (FSM) consists of three sets I, O,

## and S and two functions PS and NS in which:

I is a set of input combinations, O is a set of output combinations, S is a set of states PS is the next state function f(I, S), and NS is the output function f(S) [Moore model] or the output function f(I, S) [Mealy model].

## The FSM is a fundamental mathematical model used for

sequential circuits.

The traditional state diagrams and state tables are just two

## of many ways of representing FSMs.

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FSM Equations

The output logic can be easily derived as a logical sum of all the states where 1 on the output is produced (Moore). o 0 u t 1

00
Out1
in1

in1

Next State
Q1 Q2

D1 D2

Q1

in1 in1

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Q2

01
in1

Clk

## D2 = Q1+ = in1& Q1&Q2 # in1& Q1&Q2 # in1& Q1&Q2 # ...

State
The state of a system is a snapshot of all the relevant elements of the system at the moment the snapshot is taken.

## A uniquely identifiable set of values measured at various points in a digital system

Examples:
The state of a basketball game can be represented by

the scoreboard.

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## Present State and Next State

State 4 For any given state, there is a finite number of possible next states. On each clock cycle, the state machine branches to the next state. One of the possible next states becomes the new present state, depending on the inputs present on the clock cycle.

State 5

State 6

State 7

Two types:
Moore Mealy

## Moore and Mealy Machines

Both these machine types follow the basic characteristics of

state machines, but differ in the way that outputs are produced. Moore Machine: Outputs are independent of the inputs, ie outputs are effectively produced from within the state of the state machine. Mealy Machine: Outputs can be determined by the present state and the present inputs, ie outputs are produced as the machine makes a transition from one state to another.

Machine Models
Inputs Inputs

## Combinatorial Logic to Determine State

Present State Register Bank Combinatorial Logic to Determine Output Based on: Present State

## Combinatorial Logic to Determine State

Present State Register Bank Combinatorial Logic to Determine Output Based on: Present State Present Inputs

Moore Machine
Output Output

Mealy Machine

## Mealy and Moore Models

The Mealy model: the outputs are functions of both

## the present state and inputs

The outputs may change if the inputs change during the

## clock pulse period.

The outputs may have momentary false values unless the inputs are synchronized with the clocks.

## present state only

The outputs are synchronous with the clocks.
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## Fig. 5.21 Block diagram of Mealy and Moore state machine

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Moore Machine
Describe Outputs as Concurrent Statements

## Depending on State Only

transition condition 1
state 1 / output 1 state 2 / output 2

transition condition 2

## Outputs associated with each state are set at clock transition

A Moore Machine
a,b q1/0 a b a

q0/1 b

q3/1 b

q2/0

q0 q1 q2 q3

a q1 q1 q1 q3

b OUT q2 1 q1 0 q3 0 q1 1

## Moore Machine Diagrams

The Moore State Machine output is shown inside the state bubble, because the output remains the same as long as the state machine remains in that state. State 1 q,r a,b
Input condition that must exist in order to execute these transitions from State 1

i,j

## Output condition that results from being in a particular present state

State 2 x,y

Mealy FSM
Output depends on inputs

## AND current state

Outputs are set during

transitions

A Mealy Machine
q1 a/1 a/1, b/1

q0 b/0

a/0

b/0 q2

Qold IN Qnew q0 a q1 q0 b q2 q1 a q1 q1 b q1 q2 a q1 q2 b q2

OUT 1 0 1 1 0 0

## Mealy Machine Diagrams

The Mealy State Machine generates outputs based on: The Present State, and The Inputs to the M/c. So, it is capable of generating many different patterns of output signals for the same state, depending on the inputs present on the clock cycle. Outputs are shown on transitions since they are determined in the same way as is the next state.
Output condition that results from being in a particular present state

State 1

a,b q,r
Input condition that must exist in order to execute these transitions from State 1

i,j x,y

State 2

## Mealy and Moore Models Present Next Present Next

State A B 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 I/P x 0 1 0 1 0 1 0 1 State A B 0 0 0 1 0 0 1 1 0 0 1 0 0 0 1 0 O/P y 0 0 1 0 1 0 1 0 State A B 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 I/P x 0 1 0 1 0 1 0 1 State A B 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0

Mealy

Moore

O/P y 0 0 0 0 0 0 1 1

For the same state, the output changes with the input

For the same state, the output does not change with the input
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## Mealy vs. Moore machine

Moore machine: Output a function of state. Mealy machine: Output a function of primary inputs + state.
Moore and Mealy FSMs Can Be Functionally Equivalent

Mealy FSM Has Richer Description and Usually Requires Smaller Number of States

## Moore vs. Mealy FSM

Mealy FSM Computes Outputs as soon as Inputs

Change
Mealy FSM responds one clock cycle sooner than

## Inputs and Outputs

Moore FSM is less likely to have a shorter critical path

## ANALYSIS AND DESIGN OF SEQUENTIAL MACHINES

1. 2. 3. 4. CODE SEQUENCE DETECTOR COUNTERS AND REGISTERS SEQUENTAL CODE GENERATORS MULTI-INPUT SYSTEM CONTROLLERS

## State Table (Transition Table)

Present Input State Next State
x

Output

Q Q

A 0 0 0 0 1 1 1 1 t

B 0 0 1 1 0 0 1 1

x 0 1 0 1 0 1 0 1

A 0 0 0 1 0 1 0 1

B 0 1 0 1 0 0 0 0

y 0 0 1 0 1 0 1 0

D CLK

Q Q

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x

Present State

Q Q

A 0 0 1 1

B 0 1 0 1

A 0 0 0 0

B 0 0 0 0 t+1

A 0 1 1 1

B 1 1 0 0

y 0 1 1 1 t

y 0 0 0 0

D CLK

Q Q

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State Diagram
AB

Present State

input/output
1/0 0/1
10

A B 0 0

A B A B 0 0 0 1

y 0

y 0

0/0
00

0 1
1 0 1 1

0
0 0

0
0 0

1
1 1

1
0 0

1
1 1

0
0 0

x D Q Q A

0/1 1/0
01

0/1
11

1/0
D CLK

Q Q

## 1/0 Eastern Mediterranean University

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Moore Circuit
Next State Logic Circuit State Memory Output Logic Circuit

## inpu t clock input

outpu t

clock signal

Mealy Circuit
Next State Logic Circuit State Memory Output Logic Circuit

outpu t

clock signal