Meenakshi Sood

Sequential Circuits
 Combines combinational logic with storage  “Remembers” state, and changes output (and state)

based on inputs and current state
Digital signals are received and interpreted by a digital system an control outputs are generated in accordance with the sequence in which the input signals are received. Inputs

Combinational Logic Circuit
Outputs Storage Elements

State Machine
3-2

Sequential Circuits
 Models for representing sequential circuits
 Finite-state machines (Moore and Mealy)  Representation of memory (states)  Changes in state (transitions)

 Basic sequential circuits
 Shift registers  Counters

 Design procedure
 State diagrams  State transition table  Next state functions

the transitions between them. The State Machine model is one such model A state machine represents a system as a set of states. a state machine is a particular conceptualization of a particular sequential circuit. . However some designs are easier to conceptualize and implement using non-Boolean models.  State machines can be used for many other things beyond logic design and computer architecture. along with the associated inputs and outputs  So.Definition of a State Machine  All programmable logic designs can be specified in Boolean form.

Finite State Machines  Any Circuit with Memory Is a Finite State Machine  Design of FSMs Involves  Defining states  Defining transitions between states  Optimization / minimization  Above Approach Is Practical for Small FSMs Only .

2. 3.  3-6 . 5. A finite number of states A finite number of external inputs A finite number of external outputs An explicit specification of all state transitions An explicit specification of what determines each external output value Often described by a state diagram.Finite State Machine A description of a system with the following components: 1. 4.  Outputs are associated with each state (or with each transition). Inputs trigger state transitions.

FSM structure .

events outside the registers. .  Don’t have to worry about timing constraints.Synchronous design  Controlled by clock(s).  State changes at time determined by the clock.  Primary inputs settle in time for combinational delay through logic.  Machine state is determined solely by registers.  Inputs to registers settle in time for state change.

3-9 . state machine makes a transition. based on the current state and the external inputs. “1” “0” One Cycle time At the beginning of each clock cycle. a clock circuit triggers transition from one state to the next.The Clock Frequently.

S). O is a set of output combinations. and S and two functions PS and NS in which:      I is a set of input combinations. O. and NS is the output function f(S) [Moore model] or the output function f(I. Chapter 5 Part 3 10 .Finite State Machines  A finite state machine (FSM) consists of three sets I.  The FSM is a fundamental mathematical model used for sequential circuits.  The traditional state diagrams and state tables are just two of many ways of representing FSMs. S) [Mealy model]. S is a set of states PS is the next state function f(I.

o 0 u t 1 00 Out1 in1 in1 Next State Q1 Q2 D1 D2 Q1 in1 in1 11 Q2 01 in1 1 Clk Out1 = Q1&Q2 # ..FSM Equations  The output logic can be easily derived as a logical sum of all the states where ‘1’ on the output is produced (Moore). D2 = Q1+ = in1& Q1&Q2 # in1& Q1&Q2 # in1& Q1&Q2 # . .....

time remaining. etc.State The state of a system is a snapshot of all the relevant elements of the system at the moment the snapshot is taken.  Number of points. 3-12 . A uniquely identifiable set of values measured at various points in a digital system Examples:  The state of a basketball game can be represented by the scoreboard. possession.

including loops back to the same state. State 5 State 6 State 7  On a well-drawn state diagram.Present State and Next State State 4 For any given state. the state machine branches to the next state. On each clock cycle. there is a finite number of possible next states. depending on the inputs present on the clock cycle. . all possible transitions will be visible. One of the possible next states becomes the new present state.

Finite State Machines (FSMs) Two types:  Moore  Mealy CLASSIFICATION  CLASS A  CLASS B  CLASS C  CLASS D  CLASS E .

. ie outputs are effectively produced from within the state of the state machine.  Mealy Machine:  Outputs can be determined by the present state and the present inputs.Moore and Mealy Machines  Both these machine types follow the basic characteristics of state machines. ie outputs are produced as the machine makes a transition from one state to another. but differ in the way that outputs are produced.  Moore Machine:  Outputs are independent of the inputs.

Machine Models Inputs Inputs Combinatorial Logic to Determine State Present State Register Bank Combinatorial Logic to Determine Output Based on:  Present State Combinatorial Logic to Determine State Present State Register Bank Combinatorial Logic to Determine Output Based on:  Present State  Present Inputs Moore Machine Output Output Mealy Machine .

 The outputs may have momentary false values unless the inputs are synchronized with the clocks.Mealy and Moore Models  The Mealy model: the outputs are functions of both the present state and inputs  The outputs may change if the inputs change during the clock pulse period.  The Moore model: the outputs are functions of the present state only  The outputs are synchronous with the clocks. Eastern Mediterranean University 17 .

Mealy and Moore Models Fig.21 Block diagram of Mealy and Moore state machine Eastern Mediterranean University 18 . 5.

Moore Machine  Describe Outputs as Concurrent Statements Depending on State Only transition condition 1 state 1 / output 1 state 2 / output 2 transition condition 2 Outputs associated with each state are set at clock transition .

A Moore Machine a.b q1/0 a b a q0/1 b a q3/1 b q2/0 q0 q1 q2 q3 a q1 q1 q1 q3 b OUT q2 1 q1 0 q3 0 q1 1 .

State 1 q.r a.b Input condition that must exist in order to execute these transitions from State 1 i.y .Moore Machine Diagrams The Moore State Machine output is shown inside the state bubble. because the output remains the same as long as the state machine remains in that state.j Output condition that results from being in a particular present state State 2 x.

Mealy FSM  Output depends on inputs AND current state  Outputs are set during transitions .

b/1 q0 b/0 a/0 b/0 q2 Qold IN Qnew q0 a q1 q0 b q2 q1 a q1 q1 b q1 q2 a q1 q2 b q2 OUT 1 0 1 1 0 0 .A Mealy Machine q1 a/1 a/1.

Outputs are shown on transitions since they are determined in the same way as is the next state. Output condition that results from being in a particular present state State 1 a.r Input condition that must exist in order to execute these transitions from State 1 i. So. and  The Inputs to the M/c.Mealy Machine Diagrams The Mealy State Machine generates outputs based on:  The Present State. it is capable of generating many different patterns of output signals for the same state.j x. depending on the inputs present on the clock cycle.b q.y State 2 .

the output changes with the input For the same state. the output does not change with the input 25 Eastern Mediterranean University .Mealy and Moore Models Present Next Present Next State A B 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 I/P x 0 1 0 1 0 1 0 1 State A B 0 0 0 1 0 0 1 1 0 0 1 0 0 0 1 0 O/P y 0 0 1 0 1 0 1 0 State A B 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 I/P x 0 1 0 1 0 1 0 1 State A B 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 Mealy Moore O/P y 0 0 0 0 0 0 1 1 For the same state.

 Mealy machine:  Output a function of primary inputs + state. Moore and Mealy FSMs Can Be Functionally Equivalent Mealy FSM Has Richer Description and Usually Requires Smaller Number of States .Mealy vs. Moore machine  Moore machine:  Output a function of state.

Moore vs. Mealy FSM  Mealy FSM Computes Outputs as soon as Inputs Change  Mealy FSM responds one clock cycle sooner than equivalent Moore FSM  Moore FSM Has No Combinational Path Between Inputs and Outputs  Moore FSM is less likely to have a shorter critical path .

CODE SEQUENCE DETECTOR COUNTERS AND REGISTERS SEQUENTAL CODE GENERATORS MULTI-INPUT SYSTEM CONTROLLERS . 4.ANALYSIS AND DESIGN OF SEQUENTIAL MACHINES 1. 2. 3.

 State Table (Transition Table) Present Input State Next State x Output D Q Q A A 0 0 0 0 1 1 1 1 t B 0 0 1 1 0 0 1 1 x 0 1 0 1 0 1 0 1 A 0 0 0 1 0 1 0 1 B 0 1 0 1 0 0 0 0 y 0 0 1 0 1 0 1 0 D CLK Q Q B y A(t+1) = A x + B x B(t+1) = A’ x y(t) = (A + B) x’ 29 t+1 t Eastern Mediterranean University .

 State Table (Transition Table) x Present State Next State Output x=0 x=1 x=0 x=1 D Q Q A A 0 0 1 1 B 0 1 0 1 A 0 0 0 0 B 0 0 0 0 t+1 A 0 1 1 1 B 1 1 0 0 y 0 1 1 1 t y 0 0 0 0 D CLK Q Q B y t A(t+1) = A x + B x B(t+1) = A’ x y(t) = (A + B) x’ 30 Eastern Mediterranean University .

 State Diagram AB Present State Next State x=0 x=1 Output x=0 x=1 input/output 1/0 0/1 10 A B 0 0 A B A B 0 0 0 1 y 0 y 0 0/0 00 0 1 1 0 1 1 0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 0 0 0 x D Q Q A 0/1 1/0 01 0/1 11 1/0 D CLK Q Q B y 1/0 Eastern Mediterranean University 31 .

Moore Circuit Next State Logic Circuit State Memory Output Logic Circuit inpu t clock input outpu t clock signal .

Mealy Circuit Next State Logic Circuit State Memory Output Logic Circuit inpu t clock input outpu t clock signal .

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