Digital Integrated Circuits Prentice Hall 1995 Memory

SEMICONDUCTOR
MEMORIES

Adapted from Jan Rabaey's IC Design.
Copyright 1996 UCB.
Digital Integrated Circuits Prentice Hall 1995 Memory
Chapter Overview
Memory Classification
Memory Architectures
The Memory Core
Periphery
Reliability
Digital Integrated Circuits Prentice Hall 1995 Memory
Semiconductor Memory
Classification
RWM NVRWM ROM
EPROM
E
2
PROM
FLASH
Random
Access
Non-Random
Access
SRAM
DRAM
Mask-Programmed
Programmable (PROM)
FIFO
Shift Register
CAM
LIFO
Digital Integrated Circuits Prentice Hall 1995 Memory
Memory Architecture: Decoders
Digital Integrated Circuits Prentice Hall 1995 Memory
Array-Structured Memory Architecture
Input-Output
(M bits)
R
o
w

D
e
c
o
d
e
r
A
K
A
K+1
A
L-1
2
L-K
Column Decoder
Bit Line
Word Line
A
0
A
K-1
Storage Cell
Sense Amplifiers / Drivers
M.2
K
Problem: ASPECT RATIO or HEIGHT >> WIDTH
Amplify swing to
rail-to-rail amplitude
Selects appropriate
word
Digital Integrated Circuits Prentice Hall 1995 Memory
Hierarchical Memory Architecture
Global Data Bus
Row
Address
Column
Address
Block
Address
Block Selector Global
Amplifier/Driver
I/O
Control
Circuitry
Advantages:
1. Shorter wires within blocks
2. Block address activates only 1 block => power savings
Digital Integrated Circuits Prentice Hall 1995 Memory
MOS NOR ROM
WL[0]
WL[1]
WL[2]
WL[3]
BL[0] BL[1] BL[2] BL[3]
GND
GND
V
DD
Pull-up devices
Digital Integrated Circuits Prentice Hall 1995 Memory
MOS NAND ROM
WL[0]
WL[1]
WL[2]
WL[3]
BL[0] BL[1] BL[2] BL[3]
V
DD
Pull-up devices
All word lines high by default with exception of selected row
Digital Integrated Circuits Prentice Hall 1995 Memory
Equivalent Transient Model for MOS NOR
ROM
V
DD
WL
BL
r
word
c
word
C
bit
Model for NOR ROM
Word line parasitics
Resistance/cell: (7/2) x 10 O/q = 35 O
Wire capacitance/cell: (7 2) (0.6)
2
0.058 + 2 (7 0.6) 0.043 = 0.65 fF
Gate Capacitance/cell: (4 2) (0.6)
2
1.76 = 5.1 fF.
Bit line parasitics:
Resistance/cell: (8.5/4) x 0.07 O/q = 0.15 O (which is negligible)
Wire capacitance/cell: (8.5 4) (0.6)
2
0.031 + 2 (8.5 0.6) 0.044 = 0.83 fF
Drain capacitance/cell: ((3 4) (0.6)
2
0.3 + 2 3 0.6 0.8) 0.375 +
4 0.6 0.43 = 2.6 fF
Digital Integrated Circuits Prentice Hall 1995 Memory
Equivalent Transient Model for MOS NAND
ROM
V
DD
WL
BL
r
word
c
word
C
L
r
bit
c
bit
Model for NAND ROM
Word line parasitics:
Resistance/cell: (6/2) x 10 O/q = 30 O
Wire capacitance/cell: (6 2) (0.6)
2
0.058 + 2 (6 0.6) 0.043 = 0.56 fF
Gate Capacitance/cell: (3 2) (0.6)
2
1.76 = 3.8 fF.
Bit line parasitics:
Resistance/cell: ~ 10 kO, the average transistor resistance over the range of interest.
Wire capacitance/cell: Included in diffusion capacitance
Source/Drain capacitance/cell: ((3 3) (0.6)
2
0.3 + 2 3 0.6 0.8) 0.375 + (3 2) (0.6)
2

1.76 = 5.2 fF
Digital Integrated Circuits Prentice Hall 1995 Memory
Propagation Delay of NOR ROM
Word line delay
Consider the 512

512 case. The delay of the distributed rc-line containing M

cells can be approximated using the expressions derived in Chapter 8.
t
word
= 0.38 (r
word

c
word
) M
2
= 0.38 (35
O

(0.65 + 5.1) fF) 512

2
= 20 nsec
Bit line delay
Assume a (2.4/1.2) pull-down device and a (8/1.2) pull-up transistor. The bit
line switches between 5 V and 2.5 V.
C
bit
= 512

(2.6 + 0.8) fF = 1.7 pF
I
avHL
= 1/2 (2.4/0.9) (19.6 10
-6
)((4.25)
2
/2 + (4.25

3.75 - (3.75)
2
/2)) -
1/2 (8/0.9) (5.3 10
-6
) (4.25

1.25 - (1.25)
2
/2) = 0.36 mA
t
HL
= (1.7 pF

1.25 V) / 0.36 mA = 5.9 nsec

The low-to-high response time can be computed using a similar approach.
t
LH
= (1.7 pF

1.25 V) / 0.36 mA = 5.9 nsec

Digital Integrated Circuits Prentice Hall 1995 Memory
Decreasing Word Line Delay
Metal bypass
Polysilicon word line K cells
Polysilicon word line WL
Driver
(b) Using a metal bypass
(a) Driving the word line from both sides
Metal word line
WL
(c) Use silicides
Digital Integrated Circuits Prentice Hall 1995 Memory
Precharged MOS NOR ROM
WL[0]
WL[1]
WL[2]
WL[3]
BL[0] BL[1] BL[2] BL[3]
GND
GND
V
DD
Precharge devices
|
pre
PMOS precharge device can be made as large as necessary,
but clock driver becomes harder to design.
Digital Integrated Circuits Prentice Hall 1995 Memory
Floating-gate transistor (FAMOS)
Source
Drain
Gate
Floating gate
t
ox
t
ox
Substrate
n
+
n
+
p
(a) Device cross-section
S
D
G
(b) Schematic symbol
Digital Integrated Circuits Prentice Hall 1995 Memory
Floating-Gate Transistor Programming
D
S
20 V
20 V
D
S
0 V
0 V
10 V

5 V
5 V
D
S
5 V
5 V

2.5 V
Avalanche injection. Removing programming voltage
leaves charge trapped.
Programming results in
higher V
T
.
Digital Integrated Circuits Prentice Hall 1995 Memory
FLOTOX EEPROM
Source Drain
Gate
Floating gate
Substrate
n
+
n
+
10 nm
20-30 nm
(a) Flotox transistor
V
GD
I
(b) Fowler-Nordheim I -V characteristic
10 V
10 V
p
BL
WL
V
DD
(c) EEPROM cell during a read operation
Digital Integrated Circuits Prentice Hall 1995 Memory
Flash EEPROM
n
+
drain
n
+
source
p-substrate
Control gate
Floating gate
programming
erasure Thin tunneling oxide
Digital Integrated Circuits Prentice Hall 1995 Memory
Cross-sections of NVM cells
EPROM Flash
Courtesy Intel
Digital Integrated Circuits Prentice Hall 1995 Memory
Characteristics of State-of-the-art
NVM
Digital Integrated Circuits Prentice Hall 1995 Memory
Read-Write Memories (RAM)
STATIC (SRAM)
DYNAMIC (DRAM)
Data stored as long as supply is applied
Large (6 transistors/cell)
Fast
Differential
Periodic refresh required
Small (1-3 transistors/cell)
Slower
Single Ended
Digital Integrated Circuits Prentice Hall 1995 Memory
6-transistor CMOS SRAM Cell
V
DD
Q
Q
M1 M3
M4 M2
M5
BL
WL
BL
M6
Digital Integrated Circuits Prentice Hall 1995 Memory
CMOS SRAM Analysis (Write)
V
DD
Q = 1
Q = 0
M1
M4
M5
BL = 1
WL
BL = 0
M6
V
DD
k
n M6 ,
V
DD
V
Tn
( )
V
DD
2
-----------
V
DD
2
8
-----------
\ .
| |
k
p M4 ,
V
DD
V
Tp
( )
V
DD
2
-----------
V
DD
2
8
-----------
\ .
| |
=
k
n M5 ,
2
--------------
V
DD
2
----------- V
Tn
V
DD
2
-----------
\ .
| |

\ .
| |
2
k
n M1 ,
V
DD
V
Tn
( )
V
DD
2
-----------
V
DD
2
8
-----------
\ .
| |
=
(W/L)
n,M5
>
10 (W/L)
n,M1
(W/L)
n,M6
>
0.33 (W/L)
p,M4
Digital Integrated Circuits Prentice Hall 1995 Memory
CMOS SRAM Analysis (Read)
V
DD
Q = 1
Q = 0
M1
M4
M5
BL
WL
BL
M6
V
DD
V
DD
V
DD
C
bit
C
bit
k
n M5 ,
2
---------------
V
DD
2
------------ V
Tn
V
DD
2
------------
\ .
| |

\ .
| |
2
k
n M1 ,
V
DD
V
Tn
( )
V
DD
2
------------
V
DD
2
8
------------
\ .
| |
=
(W/L)
n,M5

s

10 (W/L)
n,M1
(supercedes read constraint)
Digital Integrated Circuits Prentice Hall 1995 Memory
6T-SRAM Layout
V
DD

GND
Q
Q
WL
BL BL
M1 M3
M4 M2
M5 M6
Digital Integrated Circuits Prentice Hall 1995 Memory
Resistance-load SRAM Cell
V
DD
Q Q
M1 M2
M3
BL
WL
BL
M4
R
L
R
L
Static power dissipation -- Want R
L
large
Bit lines precharged to V
DD
to address t
p
problem
Digital Integrated Circuits Prentice Hall 1995 Memory
3-Transistor DRAM Cell
M2
M1
BL1
WWL
BL2
M3
RWL
C
S
X
WWL
RWL
X
BL1
BL2
V
DD
-V
T
A
V
V
DD
V
DD
-V
T
No constraints on device ratios
Reads are non-destructive
Value stored at node X when writing a 1 = V
WWL
-V
Tn
Digital Integrated Circuits Prentice Hall 1995 Memory
3T-DRAM Layout
BL2 BL1 GND
RWL
WWL
M3
M2
M1
Digital Integrated Circuits Prentice Hall 1995 Memory
1-Transistor DRAM Cell
C
S
M1
BL
WL
C
BL
WL
X
BL
V
DD

V
T
V
DD
/2
V
DD
GND
Write "1" Read "1"
sensing
V
DD
/2
AV V
BL
V
PRE
V
BIT
V
PRE
( )
C
S
C
S
C
BL
+
------------------------
= =
Write: C
S
is charged or discharged by asserting WL and BL.
Read: Charge redistribution takes places between bit line and storage capacitance
Voltage swing is small; typically around 250 mV.
Digital Integrated Circuits Prentice Hall 1995 Memory
DRAM Cell Observations
1T DRAM requires a sense amplifier for each bit line, due to
charge redistribution read-out.
DRAM memory cells are single ended in contrast to SRAM cells.
The read-out of the 1T DRAM cell is destructive; read and
refresh operations are necessary for correct operation.
Unlike 3T cell, 1T cell requires presence of an extra capacitance
that must be explicitly included in the design.
When writing a 1 into a DRAM cell, a threshold voltage is lost.
This charge loss can be circumvented by bootstrapping the
word lines to a higher value than V
DD
.
Digital Integrated Circuits Prentice Hall 1995 Memory
1-T DRAM Cell
(a) Cross-section
(b) Layout
Diffused
bit line
Polysilicon
plate
M1 word
line
Capacitor
Polysilicon
gate
Metal word line
SiO
2
n
+
Field Oxide
Inversion layer
induced by
plate bias
n
+
poly
poly
Used Polysilicon-Diffusion Capacitance
Expensive in Area
Digital Integrated Circuits Prentice Hall 1995 Memory
SEM of poly-diffusion capacitor 1T-DRAM
Digital Integrated Circuits Prentice Hall 1995 Memory
Advanced 1T DRAM Cells
Cell Plate Si
Capacitor Insulator
Storage Node Poly
2nd Field Oxide
Refilling Poly
Si Substrate
Trench Cell
Stacked-capacitor Cell
Capacitor dielectric layer
Cell plate
Word line
Insulating Layer
Isolation Transfer gate
Storage electrode
Digital Integrated Circuits Prentice Hall 1995 Memory
Periphery
Decoders
Sense Amplifiers
Input/Output Buffers
Control / Timing Circuitry
Digital Integrated Circuits Prentice Hall 1995 Memory
Row Decoders
Collection of 2
M
complex logic gates
Organized in regular and dense fashion
(N)AND Decoder
NOR Decoder
Digital Integrated Circuits Prentice Hall 1995 Memory
Dynamic Decoders
WL
3
GND GND Precharge devices
WL
2
WL
1
WL
0
V
DD
| A
0
A
0
A
1
A
1
A
0
A
0
A
1
A
1
V
DD
V
DD
V
DD
V
DD
|
WL
3
WL
2
WL
1
WL
0
Dynamic 2-to-4 NOR decoder 2-to-4 MOS dynamic NAND Decoder
Propagation delay is primary concern
Digital Integrated Circuits Prentice Hall 1995 Memory
A NAND decoder using 2-input pre-
decoders
A
0
A
1
A
0
A
1
A
0
A
1
A
0
A
1
A
2
A
3
A
2
A
3
A
2
A
3
A
2
A
3
A
1
A
0
A
0
A
1
A
3
A
2
A
2
A
3
WL
0
WL
1
Splitting decoder into two or more logic layers
produces a faster and cheaper implementation
Digital Integrated Circuits Prentice Hall 1995 Memory
4 input pass-transistor based column
decoder
BL
0
BL
1
BL
2
BL
3
D
A
0
A
1
S
0
S
1
S
2
S
3

2

i
n
p
u
t

N
O
R

d
e
c
o
d
e
r
Advantage: speed (t
pd
does not add to overall memory access time)
Disadvantage: large transistor count
only 1 extra transistor in signal path
Digital Integrated Circuits Prentice Hall 1995 Memory
4-to-1 tree based column decoder
BL
0
BL
1
BL
2
BL
3
D
A
0
A
0
A
1
A
1
Number of devices drastically reduced
Delay increases quadratically with # of sections; prohibitive for large decoders
buffers
progressive sizing
combination of tree and pass transistor approaches
Solutions:
Digital Integrated Circuits Prentice Hall 1995 Memory
Sense Amplifiers
t
p
C AV
I
av
---------------- =
make AV as small
as possible
small large
Idea: Use Sense Amplifer
output input
s.a.
small
transition
Digital Integrated Circuits Prentice Hall 1995 Memory
Differential Sensing - SRAM
Diff.
Sense
Amp
BL BL
SRAM cell i
x x
y y
D D
V
DD
V
DD
WL
i
PC
EQ
V
DD
x x
y
SE
V
DD
x x
y
SE
V
DD
x x
y
SE
(b) Doubled-ended Current Mirror Amplifier
y
(a) SRAM sensing scheme.
(c) Cross-Coupled Amplifier
M1 M2
M4 M3
M5
Digital Integrated Circuits Prentice Hall 1995 Memory
Latch-Based Sense Amplifier
V
DD
BL
SE
SE
BL
EQ
Initialized in its meta-stable point with EQ
Once adequate voltage gap created, sense amp enabled with SE
Positive feedback quickly forces output to a stable operating point.
Digital Integrated Circuits Prentice Hall 1995 Memory
Single-to-Differential Conversion
Diff.
S.A.
cell
BL
V
ref
+
_
WL
x x
y y
How to make good V
ref
?
Digital Integrated Circuits Prentice Hall 1995 Memory
Open bitline architecture
V
DD
SE
SE
C
S
C
S
C
S
L
...
C
S
C
S
...
C
S
R
BLL
BLR
L
0
L
1
R
0
R
1
dummy
cell
dummy
cell
EQ
Digital Integrated Circuits Prentice Hall 1995 Memory
DRAM Read Process with Dummy Cell
0 1 2 3 4 5
t (nsec)
0.0
2.0
4.0
6.0
V

(
V
o
l
t
)
0 1 2 3 4 5
t (nsec)
0.0
2.0
4.0
6.0
V

(
V
o
l
t
)
0 1 2 3 4 5
0.0
1.0
2.0
3.0
4.0
5.0
V

(
V
o
l
t
)
EQ
WL
SE
BL
BL
BL
BL
(a) reading a zero
(b) reading a one
(c) control signals
Digital Integrated Circuits Prentice Hall 1995 Memory
Address Transition Detection
DELAY
t
d
A
0
DELAY
t
d
DELAY
t
d
ATD
...
A
1
A
N-1
V
DD
ATD
Digital Integrated Circuits Prentice Hall 1995 Memory
Semiconductor Memory Trends
Memory Size as a function of time: x 4 every three years
Digital Integrated Circuits Prentice Hall 1995 Memory
Semiconductor Memory Trends
Increasing die size
factor 1.5 per generation
Combined with reducing cell size
factor 2.6 per generation
Digital Integrated Circuits Prentice Hall 1995 Memory
Semiconductor Memory Trends
Technology feature size for different SRAM generations