You are on page 1of 22

1

. A pipeline is like .................... A) an automobile assembly line B) house pipeline C) both a and b D) a gas line

. Data hazards occur when ..................... A) Greater performance loss B) Pipeline changes the order of read/write access to operands C) Some functional unit is not fully pipelined D) Machine size is limited

A. B. C. D.

MIMD stands for _____. Multiple instruction multiple data Multiple instruction memory data Memory instruction multiple data Multiple information memory data

4
The average time required to reach a storage location in memory and obtain its contents is called_____. A. Latency time. B. Access time. C. Turnaround time. D. Response time.

5
Cache memory works on the principle of_____. A. Locality of data . B.Locality of memory C. Locality of referenceD. Locality of reference & memory

6
Virtual memory consists of _______. A. Static RAM B. Dynamic RAM C. Magnetic memory D. None of these

7
Generally Dynamic RAM is used as main memory in a computer system as it______. A. Consumes less power B. has higher speed C. has lower cell density D. needs refreshing circuitry

8
Von Neumann architecture is ______. A. SISD B. SIMD C. MIMD D. MISD

9
SIMD represents an organization that ______________. A. refers to a computer system capable of processing several programs at the same time. B. represents organization of single computer containing a control unit, processor unit and a memory unit. C. includes many processing units under the supervision of a common control unit D. none of the above.

10

State whether the following statement is True or False for cache memory. i) Cache memories are high-speed buffers which are inserted between the processors and main memory. ii) They can also be inserted between main memory and mass storage. iii) It can be used as secondary memory. A) i- True, ii- False, iii-True

B) i- False, ii- True, iii-True


C) i-True, ii-True, iii-False D) i- False, ii- False, iii-True

11
Instruction pipelining has minimum stages A. 4 B. 2 C. 3 D. 6

12
Pipeline processing implement A. fetch instruction B. decode instruction C. fetch operand D. calculate operand E. execute instruction F. all of the above

13
Systems that do not have parallel processing capabilities are A. SISD B. SIMD C. MIMD D. All of the above

14
In a DMA write operation the data is transferred (A) from I/O to memory. (B) from memory to I/O. (C) from memory to memory. (D) from I/O to I/O.

15
Which of the following memory is fastest memory? A. Registers B. Cache C. Main memory D. Both (a) and b have equal speed

16
The internal h/w organization of a digital computer is best defined by specifying: I. Set of registers II. Sequence of micro operations III. Control to initiate the micro operations A) I only B)II &III only C) I,II &III D)I &II only

17
Which of the following is true A) Both hardwired control and Micro programmed control require control memory B) only hardwired control require control memory C) only Micro programmed control require control memory D) in some situations hardwired control also require control memory

18
Which of the following is not a feature of RISC architecture? I) Few addressing modes II) variable length instruction format III) Hardwired control

A) I only C) III only

B)II only D) II , III only

19
Which of the following is a characteristics of RISC architecture? A) Large number of registers B) overlapped register windows to speed up procedure call and return C) instruction pipelining D) All of these

20
Which of the following is not a cache mapping technique? A) Direct B) Associative C) Set associative D) None of these

21
Which of the following is a problem with a pipelined processor A) Resource conflict B)Data dependency C) Branch difficulties D)All of these