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Memory interface

Memory is a device to store data

To interfacing with memories, there must be: address bus, data bus and control signals (chip enable, output enable etc) To study memory interface, we must learn how to connect memory chips to the microprocessor and how to write/read data from the memory Different kinds of memory chips will also be introduced

Block diagram of a memory interface

Content Address FFFF


Control signals Include enable (chip select) , read/write

Memory capacity 64K 16M 14M No. of address lines ? ? ?

For the 8086 microprocessor, there are two modes: minimum and maximum Under different modes, the memory interface is not the same In the minimum mode, 8086 processor is connected to the external memory block directly In the maximum mode, a Bus controller is needed The bus controller will issue the required control signal to drive the memory block

Minimum Mode



A16-A19 AD0-AD15

Address space and data organization

Memory is organized as 8-bit bytes (byte as the basic unit) To address a word then 2 consecutive bytes are used, lower addressed byte is the LSB (Least Significant Byte) and the higher-addressed byte is the MSB (Most Significant Byte) Words of data can be stored at even, or odd address boundaries MSB LSB



Memory addressing
The address bit A0 of the LSB can be used to determine the address boundary. If A0 is 0 then we have an even address, or aligned If A0 is odd then we have odd-boundary Example: 0001H is an odd-boundary address

A 16-bit data store at 01FFFH (then it is not aligned) and will occupy 01FFFH and 02000H (Odd boundary) What is A0 for the above? A 16-bit data store at 02002H (then it is aligned) and will occupy 02002H and 02003H (even boundary) What is A0 for the above?

If you are asked to implement the memory system for a 8086 microprocessor, what memory configuration will you use?
A) One 1M Bytes chip B) Two 512KBytes chips C) One 1M Word chip

Address Space
Even-boundary data can be accessed in one memory cycle Odd-boundary word must be accessed in two memory cycle In 8086, users data usually is in 8-bit or 16bit format For the system, instructions are always accessed as words (16-bit) There is also double word format (32-bit)

Data type
Double word (32-bit) will be stored in 4 consecutive locations When double word is used? Double word can be used as a pointer that is used to address data or code outside the current segment For a double word, the higher WORD stores the segment address, the lower WORD stores the offset

Memory organization
1M bytes memory using 2 512K byte chips

Odd boundary Address requires 2 memory cycles BHE bank high enable

Hardware organization
In hardware, the 1M bytes memory is implemented as two independent 512K-byte banks Low (even) bank, and the high (odd) bank Data from low bank use data lines 0-7 Data from high bank use data lines 8-15 Signal A0 enables the low bank Signal /BHE enables the high bank /BHE is active low How many address lines are required in order to access 512K locations? (Ans. 19)

Memory organization
Only A1 to A19 are used to drive the memory !!!

High bank

Low bank

Odd-addressed word transfer

Need two cycles!

Consider the 16-bit word stored at 01FFFH then it occupy 01FFFH and 02000H In the first cycle data in 01FFFH will be read In the second cycle data in 02000H will be read Second case data stored in 02002H then data occupy 02002H and 02003H. Compare the bit pattern for 02002H and 02003H 02002H 0000 0010 0000 0000 0010 02003H 0000 0010 0000 0000 0011 Why both byte can be read in a single cycle?

Dedicated Memory locations

Dedicated memory locations should not be used as general memory space for data and program storage For the 8086, address 00000 to 0007F and FFFF0 to FFFFB are dedicated Address from FFFFC to FFFFF are reserved

Determine the values for A0 and /BHE in order to access A byte at even address (/A0=0, /BHE = 1) A byte at odd address (/A0=1, /BHE = 0) A word at even address (aligned) (/A0=0, /BHE=0) A word at odd address (unaligned), as shown in the following figure (two cycles: First cycle get LSB /A0=1 /BHE=0 Second cycle get MSB /A0=0 /BHE =1 )

Memory control signals

To control the memory system in the minimum mode, requires: ALE, /BHE, M/IO, DT/R, /RD, /WR, and /DEN ALE address latch enable, signals external circuitry that a valid address is on the bus (0->1) so the address can be stored in the latch (or buffer) M/IO identify whether it is a memory or IO (Input/Output) operation (high memory, low I/O) DT/R transmit or receive (1 transmit) DEN to enable the data bus

Read cycle of 8086

Consists of 4 time states T1 memory address is on the address bus, /BHE is also output, ALE is enable Address is latch to external device at the trailing edge of ALE T2 M/IO and DT/R are set to 1 and 0 respectively. These signals remain their status during the cycle Late in T2 - /RD is switched to 0 and /DEN also set to 0

Read cycle
T3 and T4 status bits S3, S4 are output Data are read during T3 /RD and /DEN return to 1 at T4

Read Cycle

Write cycle
T1 address and /BHE are output and latched with ALE pulse M/IO is set to 1, DT/R is also set to 1 T2 - /WR set to 0 and data put on data bus Data remain in the data bus until /WR returns to 1 When /WR returns to 1 at T4, data is written into memory

Write Cycle

What is the duration of the bus cycle in the 8086-based microcomputer if the clock is 8MHz and two wait states are inserted
Ans. 750ns (6 cycles) where each clock is 125ns

Demultiplexing the address/data bus

Address and data must be available at the same time when data are to be transferred over the data bus Address and data must be separated using external demultiplexing circuits (eg a latch, or buffer) Address are latched into external circuits by ALE (address latch enable ) at T1 of the memory cycle

Demultiplexing the system bus

One direction

Bi-direction STB - Strobe Latches/buffers

Syntax to describe a memory

Memory is usually described by its size of storage and number of data bits Eg. A 32K bytes memory chip is represented by 32Kx8 A 32K bits memory is represented by 32Kx1

Configurations of memory for 16-bit data

Chip enable (CE) usually generated by some decoding mechanism OE output enable

Read only memory (ROM) nonvolatile Data remains when power is turned off, data are written into the ROM during its fabrication at the factory PROM- Programmable ROM. Can be programmed by user but this can only be done once EPROM erasable programmable ROM Contents of EPROM can be erased by exposing it to ultraviolet light EEPROM Electrical Erasable PROM (your usb memory stick)

Block diagram of a ROM

ROM interface address input, data output, /CE chip enable, /OE output enable (for READ operation)

Memory Read Operation

To read a ROM, we need to issue the proper address There is a delay between address inputs and data outputs The access time (tACC), chip enable time (tCE), and chip deselect time (tDF) are important timing properties You need these information for developing a real computer system!

Timing parameters
The access time delay occurs before data stored at the addressed location are stable at the outputs (ie how long it takes to access data). The microprocessor must wait for tACC before reading the data

ROM read operation

Access time is regarded as address to output delay. Typical value is 250ns tCE represents the Chip Enable to output delay, usually this is equal to access time Deselect time amount of time the device takes for data outputs to return to high-Z state after /OE becomes inactive

Read operation
tAA=access time tCO= chip select to output delay tHZ = deselect to output float

A normal 8086 read cycle takes 4 clocks For a system with a 8MHz clock If there are 3 different types of devices: 1. Tacc = 0.125us $100 2. Tacc = 0.2us $50 3. Tacc = 0.4us $20 Which of the above will you use?

Choosing the proper memory

Configuration of ROM for 8-bit bus

How the circuit operates?

EEPROM electrical Erasable ROM

Data stored in an EEPROM can be erased electrically Example inside the 89C52 microcontroller, there are 8KBytes EEPROM Programming is achieved by an EPROM programmer

Programming the EPROM

In an erased EPROM, all cells hold logic 1 Vpp is in logic 1 for data to be read from EPROM Vpp is ON (eg Vpp = 25V for 2716 EPROM) for programming mode (writing) 2716 is a 2Kx8 EPROM Address of the storage location is put to the address inputs Data is in the data inputs /CE is pulsed to load the data Many program and verify operations are performed to program each storage location

Random access memory (RAM)

Data can be read as well as written into the memory chip Static ram (SRAM) data remains valid as long as the power is ON Dynamic RAM (DRAM) needs to periodically restore (recharge) the data in each storage location by addressing them If storage nodes are not recharged at regular intervals of time, data would be lost. This process is called refreshing

New type of eeprom can be read as well as written ISP (in-service programming) is used to write data no need to use EPROM programmer USB memory, micro flash are examples of this type of device

SRAM circuit
To control RAM: CE chip enable OE output enable (for read operation) WE write enable (for write operation) From decoding logic

Write-cycle for SRAM

To write, we must produce the signal in proper order Minimum duration of a write cycle is tWC (write cycle time ) Address must remain stable during the whole cycle Chip enable (CE) signal becomes active The Write Enable (WE) will be active after the address setup time tAS elapses

RAM write operation

Refer to timing diagram Data should now ready and must be valid for tDW (data valid to end of write) Data should remain valid (tDH) after the write A short recovery period (tWR) takes place after /WE returns to 1 before the write cycle is complete (address is removed)

Write cycle

Timing parameters for a write cycle

Parameter Tc (rd) read cycle time TWC (wr) write cycle time TWP write pulse width Tsu (A) address set up time Tsu (S) chip select setup time Tsu (D) data setup time Th address hold time Th (D) data hold time Time (ns) 120 120 60 20 60 50 0 5

Read Cycle
Read cycle for RAM is similar to the ROM Minimum duration of a read cycle is tRC (read cycle time) Address must remain stable during the whole cycle Chip enable becomes active The Enable(s) (CE) will be active after the address is stable Data should now ready Data should remain valid after the OE and CE have been removed

CO time between Valid data and chip enable

Read Cycle

OE time between Valid data and output enable

DRAM has a higher density Cost less Consume less power Take up less space We can get 64Mx1, 128Mx1 modules

DRAM An example of a DRAM 2164B It is a 64K-bit (64Kx1) device with only 16 pins To address 64K address, requires 16-bit address line 16-bit address is divided into two separate parts: 8-bit row address, and 8-bit column address. And these are time-multiplexed


Address bus is time multiplexed RAS row address strobe CAS column address strobe

Addressing the DRAM

The row address is first applied /RAS is pulsed to 0 to latch the address into the device The column address is applied and /CAS strobed to 0 If RAS is left at 0 after the row address is latched inside the device, the address is maintained within the device

Data cells along the selected row can be accessed by simply supplying successive column addresses This is called page mode accesses (How many bits are there in a row?) Advantage - faster access of memory is achieved

Addressing the DRAM-64Kx16 setup

Refreshing the DRAM

The DRAM must be refreshed every 2ms Refreshing is achieved by cycling through the row addresses (i.e. generating all the row address) During refreshing, /CAS is at logic 1 and no data are output

System memory configuration

Memory configuration for ADuC832

ADuC832 memory architecture

Address Decoding
Address decoding is required because many memory chips are used by a computer system At each memory read/write only a number of chips is used Decoding mechanism is used to guarantee that the proper chips are selected To design, first determine the number of chips required Then determine how many address lines are needed for the decoding purpose Example if 4 chips are used then you need 2 address lines for decoding

For 8086 system, max. 1M bytes of memory Now we use 4 256Kx8 memory chip. Note: Even addresses memory locations should be in the same chip Odd addresses memory locations should be in the same chip

So the 4 memory chips will be divided into Even and Odd group (two chips per group) Only consider the even group, since the chip is only 256K so the Memory locations stored by one chip is from 00000 to 7FFFF (only The even locations) The other chip holds 80000 to FFFFF (only the even locations)

Example Odd Even

Address 80000 to FFFFF

Address 00000 to 7FFFF

Now if the address issued is 12345H which memory chip should be selected? What address line(s) can be used for the decoding ?

Decoding system
Address lines used for driving the memories Memories

Address Used for Decoder Selecting The memory block


Outputs from decoder usually used as /CE for the memories

Any device that can relate its output to its inputs can be used as a decoder Output = f(inputs) Inputs Outputs


Chip enable (/CE)

Address Decoding Techniques

An address decoder is a circuit that examines the address lines and enables the memory for a specified range of addresses. This is vital in any memory design because one block of memory must not be allowed to overlap another. Logic Gate Decoders (ANDS, ORS, NANDS, AND NORS).

Address Decoder circuits

A digital decoder is a circuit that recognizes a particular binary pattern on its input lines and produces an active output indication.

When will you get an active memory select? Ans. When all inputs are 0s then the output is 0

NAND Gate Decoder Circuit

Output of the NAND gate is active when all inputs are 1s so The address from A19 to A11 is 111111111 (FF8) From A0 to A10 is used to address the memory chip

Logic gates as decoder

Only with one output so if your system has many memory chips then you need one gate per memory chip!!!!!!

The 3-to-8 Line Decoder (74LS138)

The truth table shows that only one of the eight outputs ever goes low at any time. Three enable inputs /G2A,/G2B, and G1 must all be active. Once the 74LS138 is enabled, the address inputs A,B, and C select which output pin goes low.
Remarks: / means logic low (0) signal level.

Truth Table for 74LS138 Decoder

Address Lines will Connect To A, B and C

64KByte Memory Bank Circuit

To enable the decoder NAND output (G2B) must be 0 therefore A19 to A17 must be 111. The G1 input must be 1 so A16 is 1 So address lines A19 to A16 must be 1111 (F)

Example-128 MB Memory Circuit

Example-128 MB Memory Circuit (Contd)

BE Bank Enable There are 4 banks to support data in byte, word and double word

Design a memory system for a 8086 based computer Using 64K byte memory chips.

To design the memory system, we must first identify the followings:

How many address lines for the 64Kbyte chip? How many chips are needed for the 8086 system? Determine the address ranges for each memory block Determine the number of address lines can be used for decoding Identify a suitable decoder Draw the block diagram

How many address lines for the 64Kbyte chip? 16-bit How many chips are needed for the 8086 system? 8086 system can address 1M so 16 chips are needed The system should be divided into Even address and Odd address Even address enabled by A0, Odd address enabled by BHE 8 chips will be used for the even address and a decoder can be used

Self test

How many bytes can be stored by a 32Kx4 memory chip? (Ans. 16K bytes) How many 16K bytes memory chips are required to form a 1M system? (Ans. 1M/16K = 64) How many address lines are required to address a 16K bytes memory ? (Ans. 14) Why the signal ALE is necessary for a 8086 microprocessor? (Ans. Because the address bus is multiplexed) Why memory decoding is necessary for a computer system? (Ans. To select the proper memory chips when an address is issued) What is High-block, Low-block? (High-block represents the odd memory address, low-block is the even addresses ) The two address range F8000-F8FFF and FA000-FAFFF can be decoded by what address bit(s)? (Ans. Must first examine the binary pattern of the addresses. F8000-F8FFF = 11111000 (for the first two digits) FA000 FAFFF is 11111010 (for the first two digits) so the difference between the two ranges is bit A14. Therefore, A14 can be used to decode the two ranges. )

Develop a 16-bit wide memory interface that contains ROM memory at locations 000000H 01FFFFH for the 80386SX microprocessor. A 386SX microprocessor has 24-bit address The ROM used is 32Kx8 The decoding logic should output signal to select the chip (/CS) Select a proper decoding device (eg multiplexer, PAL, simple logic gates )

Develop a 16-bit wide memory interface that contains SRAM memory at locations 200000H 21FFFFH for the 80386SX microprocessor. (total of 128K bytes) A 386SX microprocessor has 24-bit address The SRAM used is 32Kx8 (so you need 4 memory chips) The decoding logic should output signal to select the chip (CS) , as well as enable the write operation (WE) Select a proper decoding device (eg multiplexer, PAL, simple logic gates ) You can refer to Figure 10-32

Flash Memory Flash memory (example compact flash) is a type of EEPROM chip. It has a grid of columns and rows with a cell that has two transistors at each intersection (see image below). The two transistors are separated from each other by a thin oxide layer. One of the transistors is known as a floating gate, and the other one is the control gate. The floating gate's only link to the row, or wordline, is through the control gate. As long as this link is in place, the cell has a value of 1. To change the value to a 0 requires a curious process called Fowler-Nordheim tunneling.

Flash memory
Tunneling is used to alter the placement of electrons in the floating gate. An electrical charge, usually 10 to 13 volts, is applied to the floating gate. The charge comes from the column, or bitline, enters the floating gate and drains to a ground. This charge causes the floating-gate transistor to act like an electron gun. The excited electrons are pushed through and trapped on other side of the thin oxide layer, giving it a negative charge. These negatively charged electrons act as a barrier between the control gate and the floating gate. A special device called a cell sensor monitors the level of the charge passing through the floating gate. If the flow through the gate is greater than 50 percent of the charge, it has a value of 1. When the charge passing through drops below the 50-percent threshold, the value changes to 0. A blank EEPROM has all of the gates fully open, giving each cell a value of 1.

Flash Memory The electrons in the cells of a Flash-memory chip can be returned to normal ("1") by the application of an electric field, a higher-voltage charge. Flash memory uses in-circuit wiring to apply the electric field either to the entire chip or to predetermined sections known as blocks. This erases the targeted area of the chip, which can then be rewritten. Flash memory works much faster than traditional EEPROMs because instead of erasing one byte at a time, it erases a block or the entire chip, and then rewrites it.