Verilog VS VHDL

By Kurt Leyba

VHDL & Verilog?

They are Hardware description languages. They are each a notation to describe the behavioral and structural aspects of an electronic digital circuit.

VHDL Background
VHSIC Hardware Description Language.
VHSIC is an abbreviation for Very High Speed Integrated Circuit.

Developed by the department of defense !"#!$

In 19 ! rig"t# $"ere gi%en to I&&& Beca'e a #tandard and (ubli#"ed in 19 ) *e%i#ed #tandard $e kno$ no$ (ubli#"ed in 199+ ,VHDL 1-)!.199+/ regulated by VHDL international ,VI/

VHDL
0#e# to(.do$n a((roac" to (artition de#ign into #'all block# 1co'(onent#2
&ntity3 de#cribe# inter4ace #ignal# & ba#ic building block# 5rc"itecture3 de#cribe# be"a%ior6 eac" entity can "a%e 'ulti(le 5rc"itecture# 7on4iguration3 #ort o4 (art# li#t 4or a de#ign6 $"ic" be"a%ior to u#e 4or eac" entity8 9ackage3 toolbo: u#ed to build de#ign

Verilog Background
De%elo(ed by ;ate$ay De#ign 5uto'ation ,19 -/
Later ac<uired by 7adence De#ign,19 9/ $"o 'ade it (ublic in 199 Beca'e a #tandardi=ed in 199> by I&&& ,Std 1+!?/ regulated by @(en Verilog International ,@VI/

V&*IL@;
Verilog only "a# one building block
Aodule3 'odule# connect t"roug" t"eir (ort #i'ilarly a# in VHDL 0#ually t"ere i# only one 'odule (er 4ile8 5 to( le%el in%oke# in#tance# o4 ot"er 'odule#8 Aodule# can be #(eci4ied be"a%iorally or #tructurally8
Be"a%ioral #(eci4ication de4ine# be"a%ior o4 digital #y#te' Structural #(eci4ication de4ine# "ierarc"ical interconnection o4 #ub 'odule#

Si'ilaritie#
B"e#e language# "a%e taken de#igner# 4ro' lo$ le%el detail to 'uc" "ig"er le%el o4 ab#traction8 In C--- VI & @VI 'erged into 5ccellera Si'ulation & #ynt"e#i# are t"e t$o 'ain kind# o4 tool# $"ic" o(erate on t"e VHDL & Verilog language#8 B"ey are not a tool#et or 'et"odology t"ey are eac" a di44erent language8
Ho$e%er tool#et# and 'et"odologie# are e##ential 4or t"eir e44ecti%e u#e8

Di44erence#?
B"ere are not 'any di44erence# a# to t"e ca(abilitie# o4 eac"8 B"e c"oice o4 $"ic" one to u#e i# o4ten ba#ed in (er#onal (re4erence & ot"er i##ue# #uc" a# a%ailability o4 tool# & co''ercial ter'#8 VHDL i# D"arderE to learn 5D5.like8 Verilog i# Dea#ierE to learn 7.like8

Aarket analy#i#
5ccording to ;ary S'it"6 &D5 5naly#t at Data<ue#t6 "e #ay# t"at alt"oug" Verilog i# do'inating t"e 'arket6 it i# going into t"e u#e o4 a 'i: o4 Verilog and VHDL8 ,re(ort
o4 'arc" C---/

&D5 Bool#
&lectronic De#ign 5uto'ation Bool# Looking at t"e 'arket trend and $e "a%e to look at tool# t"at i# not Fu#t #(eci4ic to one language but t"at can integrate bot" language#8 @ut o4 all t"e di44erent tool# I2%e #een 'odel SIA by Aodel inc6 i# t"e one t"at #"ould be u#ed bot" 5ltera & Gilin: reco''end it6 and it2# 4ree 4or do$nload 4ro' t"eir $eb#ite#8 Aodel inc uni%er#ity (rogra'

&D5 Bool#
5ltera & Gilin: bot" "a%e t"eir o$n de#ign en%iron'ent Aa: H 9lu# II & IS& re#(ecti%ely8 B"ey eac" "a%e t"eir o$n board to u#e $it" (rogra'#8 B"e board# %ary a lot in (rice#8 I ended u#ing 5ltera2# en%iron'ent & board ,kit/ $"ic" can be (urc"a#ed at 5ltera 4or I1>-

Si'ulation o4 counter#
De'on#tration o4 #i'(le %erilog & %"dl

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY Counter1 IS PORT C!o"#$ Re%et$UPDO&N ()*_"ount ' IN Count ' OUT 0; END Counter1;

' IN STD_LOGIC; STD_LOGIC_+ECTOR , -o.nto /0; STD_LOGIC_+ECTOR , -o.nto /0

ARCHITECTURE 1e2)34our O5 Counter1 IS SIGNAL 4ntern)!_"ount ' STD_LOGIC_+ECTOR , -o.nto /0; BEGIN Count 67 4ntern)!_"ount; PROCESS Re%et$C!o"#0 BEGIN I5 re%et78/8 THEN 4ntern)!_"ount679////////9; ELSI5 "!o"# 8E+ENT AND "!o"#78/8 THEN I5 u:-o.n78/8 THEN I5 4ntern)!_"ount6()*_"ount THEN 4ntern)!_"ount674ntern)!_"ount;1; ELSE 4ntern)!_"ount679////////9; END I5; ELSI5 u:-o.n7818 THEN I5 9////////964ntern)!_"ount THEN 4ntern)!_"ount674ntern)!_"ount<1; ELSE 4ntern)!_"ount67()*_"ount; END I5; END I5; END I5; END PROCESS; END 1e2)34our;

'odule counterC ,u(do$n6clock6re#et6Aa:7ount67ount/J out(utK)3-L 7ountJ in(utK)3-L Aa:7ountJ in(ut clock6 re#et6 u(do$nJ regK)3-L 7ntJ a##ign 7ountM7ntJ al$ay# N ,negedge clock or negedge re#et/ begin i4,Ore#et/ 7ntM Pb----Q----J el#e i4,u(do$n/ i4 ,7ntRAa:7ount/ 7ntM7ountH1J el#e 7ntM Pb----Q----J el#e i4,Ou(do$n/ i4 , Pb----Q----R7nt/ 7ntM7nt.1J el#e 7ntMAa:7ountJ end end'odule

Book
%&cellent resource fro VHDL ' Verilog

Digital Sy#te' De#ign and 9rototy(ing 0#ing Sield 9rogra''able Logic and Hard$are De#cri(tion Language 5ut"or3 Toran Salcic 5#i' S'ailagic Klu$er 5cade'ic 9ubli#"er# ISBU3 -.)9C+.)9C-.9