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Lecture 4 Design Rules,Layout and Stick Diagram

ENG.AMGAD YOUNIS amgadyounis@hotmail.com Department of Electronics Faculty of Engineering Helwan University

Acknowledgement

This lecture note has been summarized from lecture note on Introduction to VLSI Design, VLSI Circuit Design all over the world. I can’t remember where those slide come from. However, I’d like to thank all professors who create such a good work on those lecture notes. Without those lectures, this slide can’t be finished.

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Roadmap for the term: major topics
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VLSI Overview CMOS Processing & Fabrication Components: Transistors, Wires, & Parasitics Design Rules & Layout Combinational Circuit Design & Layout Sequential Circuit Design & Layout Standard-Cell Design with CAD Tools Systems Design using Verilog HDL Design Project: Complete Chip
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Review . 2014 4 .CMOS Mask Layers    Determine placement of layout objects Color coding specifies layers Layout objects:    Rectangles Polygons Arbitrary shapes Absolute (“micron”) Scaleable (“lambda”) n well  Grid types   P substrate wafer 204424 Digital Design Automation February 13.

2014 5 204424 Digital Design Automation .Mask Generation    Mask Design using Layout Editor  user specifies layout objects on different layers  output: layout file Pattern Generator  Reads layout file  Generates enlarged master image of each mask layer  Image printed on glass Step & repeat camera  Reduces & copies image onto mask  One copy for each die on wafer  Note importance of mask alignment February 13.

2014 6 .Symbolic Mask Layers   Key idea:  Reduce layers to those that describe design  Generate physical layers as needed Magic Layout Editor: "Abstract Layers”  metal1 (blue) .p diffusion (combination of active. pselect)  ptransistor (brown/red crosshatch) .1st layer metal (equiv.n diffusion (combination of active.combined poly. ndiff  pdiff (brown) . to physical layer)  Poly (red) .polysilicon (equivalent to physical layer)  ndiff (green) . cut mask 204424 Digital Design Automation February 13. nselect)  ntranistor (green/red crosshatch) . pdiff  contacts: combine layers.combined poly.

5 X minimum transistor length Paint squares on grid for each mask layer Layers to interact to form components (e. transistors)  Painting metaphor   204424 Digital Design Automation February 13.About Magic  Scalable Grid for Scalable Design Rules   Grid distance: l (lambda) Value is process-dependent: l = 0.g. 2014 7 .

Mask Layers in Magic        Poly (red) N Diffusion (green) P Diffusion (brown) Metal (blue) Metal 2 (purple) Well (cross-hatching) Contacts (X) 204424 Digital Design Automation February 13. 2014 8 .

specifies area to paint  Command window (not shown)   accepts text commands Box :paint poly : paint red :paint ndiff :paint green Paint :write (poly) prints error & status messages February 13. 2014 Paint (ntransistor) Paint (pdiff) 204424 Digital Design Automation 9 .Magic User-Interface  Graphic Display Window   Cursor Cursor Box .

2014 10 204424 Digital Design Automation .pdc  Metal 1 connecting to P-Diffusion (substrate contact) psc  Metal 1 connecting to N-Diffusion (normal) .where layers connect  Metal 1 connecting to Poly .ndc  Metal 1 connecting to N-Diffusion (substrate contact) nsc  Metal 1 connecting to Metal 2 .ntransistor  poly crosses pdiffusion .polycontact  Metal 1 connecting to P-Diffusion (normal) .where poly. diffusion cross  poly crosses ndiffusion .ptransistor Vias .Layer Interaction in Magic   Transistors .via February 13.

Example nsc p-transistor metal1 nwell polycontact poly polycontact poly metal1 psc ndc ndc ntransistor pdc metal1 204424 Digital Design Automation February 13.Magic Layers . 2014 11 .

Manufacturing processes have inherent limitations in accuracy. Design rules are determined by experience. Design rules specify geometry of masks which will provide reasonable yields. 204424 Digital Design Automation February 13. 2014 12 .Why we need design rules     Masks are tooling for manufacturing.

Impurities. Variations in oxide thickness.Manufacturing problems        Photoresist shrinkage. Variations in temperature. 2014 13 . 204424 Digital Design Automation February 13. Variations in material deposition. tearing. Variations across a wafer. Variations between lots.

Variations in substrate.   Changes in source/drain diffusion overlap. 204424 Digital Design Automation February 13.Transistor problems  Varaiations in threshold voltage:    oxide thickness. 2014 14 . ion implanatation. poly variations.

metal: variations in height. capacitance. width -> variations in resistance. Shorts and opens: 204424 Digital Design Automation February 13.Wiring problems    Diffusion: changes in doping -> variations in resistance. capacitance. Poly. 2014 15 .

2014 16 .Oxide problems   Variations in height. Lack of planarity -> step coverage. metal 2 metal 2 metal 1 204424 Digital Design Automation February 13.

Via may be too large and create short. 204424 Digital Design Automation February 13. 2014 17 . Undesize via has too much resistance.Via problems    Via may not be cut all the way through.

MOSIS SCMOS design rules     Designed to scale across a wide range of technologies. 2014 18 . 204424 Digital Design Automation February 13. Designed to support multiple vendors. Designed for educational use. fairly conservative. Ergo.

Parasitics are generally not specified in l units 204424 Digital Design Automation February 13. 2014 19 .l and design rules    l is the size of a minimum feature. Specifying l particularizes the scalable rules.

Design Rules  Typical rules:  Minumum size  Minimum spacing  Alignment / overlap  Composition  Negative features 204424 Digital Design Automation February 13. 2014 20 .

Types of Design Rules   Scalable Design Rules (e. especially for deep submicron  Layouts not portable February 13. 0.g.l (lambda)  Idea: reduce l value for each new process. 2014 21 204424 Digital Design Automation . SCMOS)  Based on scalable “coarse grid” . but keep rules the same  Key advantage: portable layout  Key disadvantage: not everything scales the same  Not used in “real life” Absolute Design Rules  Based on absolute distances (e.75µm)  Tuned to a specific process (details usually proprietary)  Complex.g.

SCMOS Design Rules  Intended to be Scalable    Original rules: SCMOS Submicron: SCMOS-SUBM Deep Submicron: SCMOS-DEEP   Pictorial Summary: Book Fig.mosis. 2-24. p. 27 Authoritative Reference: www.org 204424 Digital Design Automation February 13. 2014 22 .

Minimum Spacing=3l  metal2: Minimum width=3l. min distance form well edge to source/drain=5l Transistors:  Min width=3l  Min length=2l  Min poly overhang=2l February 13. Minimum Spacing=4l  poly: Minimum width= 2l. 2014 23 204424 Digital Design Automation .SCMOS Design Rule Summary   Line size and spacing:  metal1: Minimum width=3l. Minimum Spacing=3l. Minimum Spacing=2l  ndiff/pdiff: Minimum width= 3l. minimum ndiff/pdiff seperation=10l  wells: minimum width=10l.

2014 24 204424 Digital Design Automation .. 30% Metal February 13. size 4l X 4l  Contacts cannot stack (i. metal2/metal1/poly) Other rules  cut to poly must be 3l from other poly  cut to diff must be 3l from other diff  metal2/metal1 contact cannot be directly over poly  negative features must be at least 2l in size  CMP Density rules (AMI/HP subm): 15% Poly.e.SCMOS Design Rule Summary   Contacts (Vias)  Cut size: exactly 2l X 2l  Cut separation: minimum 2l  Overlap: min 1l in all directions  Magic approach: Symbolic contact layer min.

3) 204424 Digital Design Automation February 13.Design Rule Checking in Magic   Design violations displayed as error paint Find which rule is violated with ":drc why” Poly must overhang transistor by at least 2 (MOSIS rule #3. 2014 25 .

p. 78-79 .if “everything” scales. 2014 26 .Scaling Design Rules    Effects of scaling down are positive See book. scaling circuit by 1/x increases performance by x Problem: not everything scales proportionally 204424 Digital Design Automation February 13.

g. Agilent.Aside .MOS Implementation Service Rapid-prototyping for small chips  Multi-project chip idea .About MOSIS    MOSIS . IBM. TSMC)  Packages chips & ships back to designers Our designs will use AMI 1.several designs on the same wafer  Reduced mask costs per design  Accepts layout designs via email  Brokers fabrication by foundries (e. 2014 27 204424 Digital Design Automation . AMI.5µm process (more about this later) February 13.

2mm X 2.980  AMI 0. Semiconductor Research Corp. 2014 28 .4mm X 9.5µm “Tiny Chip” (2.080  AMI 1.5mm X 1.500  TSMC 100-159mm2 $63..About MOSIS   Some Typical MOSIS Prices (from www.5mm) FREE* *sponsored by Semiconductor Industry Assn.5mm “Tiny Chip” (1.org)  AMI 1.mosis.550  TSMC 0.5µm 9. | AMI.5µm 0-5mm2 $5. Inc..2mm) $1.7mm $17.5µm “Tiny Chip” (2. and MOSIS 204424 Digital Design Automation February 13. DuPont Photomasks.2mm) FREE*  AMI 0.900  TSMC 0.25µm 0-10mm2 $15.250 + $900 X size MOSIS Educational Program (what we use)  AMI 1.Aside .18µm 0-7mm2 $24..2mm X 2.

Layout Considerations    Break layout into interconnected cells Use hierarchy to control complexity Connect cells by   Abutment Added wires Minimize size of overall layout Meet performance constraints Meet design time deadlines February 13. 2014 29  Key goals:    204424 Digital Design Automation .

hypothetical “UART”   204424 Digital Design Automation February 13.“ring” that contains I/O pads Core .Hierarchy in Layout  Chips are constructed as a hierarchy of cells   Leaf cells .contains overall cell Pad frame .bottom of hierarchy Root cells . 2014 30 .contains logic organized as subcells Shift register  FSM  Other cells   Example .

. Pad N Shift Re giste r FSM Othe r Ce lls 204424 Digital Design Automation February 13..Hierarchy Example  Root Cell: UART Root Ce ll: UART Pad Frame Core Pad 1 Pad 2 . 2014 31 .

2014 32 .Wires 6 metal 3 3 3 metal 2 metal 1 3 2 204424 Digital Design Automation pdiff/ndiff poly February 13.

2014 33 .Transistors 2 3 2 3 1 5 204424 Digital Design Automation February 13.

metal1/metal2. 4 1 2 4 204424 Digital Design Automation February 13. metal1/poly. 2014 34 .Vias  Types of via: metal1/diff.

Metal 3 via   Type: metal3/metal2. 2014 35 . Rules:     cut: 3 x 3 overlap by metal2: 1 minimum spacing: 3 minimum spacing to via1: 2 204424 Digital Design Automation February 13.

Tub tie 4 1 204424 Digital Design Automation February 13. 2014 36 .

2014 37 .Spacings        Diffusion/diffusion: 3 Poly/poly: 2 Poly/diffusion: 1 Via/via: 2 Metal1/metal1: 3 Metal2/metal2: 4 Metal3/metal3: 4 204424 Digital Design Automation February 13.

Overglass      Cut in passivation layer. active: 15 204424 Digital Design Automation February 13. Minimum bonding pad: 100 m. Pad overlap of glass opening: 6 Minimum pad spacing to unrelated metal2/3: 30 Minimum pad spacing to unrelated metal1. poly. 2014 38 .

relative placement. 2014 39 . Does show all components/vias (except possibly tub ties). wire lengths. 204424 Digital Design Automation February 13. tub boundaries.Stick diagrams (1/3)    A stick diagram is a cartoon of a layout. Does not show exact placement. wire widths. transistor sizes.

2014 40 .Stick Diagrams (2/3)   Key idea: "Stick figure cartoon" of a layout Useful for planning layout     relative placement of transistors assignment of signals to layers connections between cells cell hierarchy 204424 Digital Design Automation February 13.

2014 41 .Stick Diagrams (3/3) 204424 Digital Design Automation February 13.

2014 42 .Example .Pull-up Network Circuit Diagram. Pull-Down Network (The easy part!) Complete Stick Diagram 204424 Digital Design Automation February 13.Stick Diagrams (1/2) Alternatives .

Stick Diagrams (2/2) 204424 Digital Design Automation February 13.Example . 2014 43 .

Dynamic latch stick diagram VDD in out VSS phi’ 204424 Digital Design Automation phi February 13. 2014 44 .

2014 45 .Stick Diagram XOR Gate Examples 204424 Digital Design Automation February 13.

2014 46 .Hierarchical Stick Diagrams  Define cells by outlines & use in a hierarchy to build more complex cells 204424 Digital Design Automation February 13.

mirroring . 2014 47 .design cells to connect when adjacent Reflection.Cell Connection Schemes    External connection .use to make abutment possible 204424 Digital Design Automation February 13.wire cells together Abutment .

Example: 2-input multiplexer  First cut: 204424 Digital Design Automation February 13. 2014 48 .

2014 49 .Sticks design of multiplexer  Start with NAND gate: 204424 Digital Design Automation February 13.

2014 50 .NAND sticks VDD a out b VSS 204424 Digital Design Automation February 13.

Refined one-bit Mux Design    Use NAND cell as black box Arrange easy power connections Vertical connections for allow multiple bits 204424 Digital Design Automation February 13. 2014 51 .

2014 52 .3-bit mux sticks select’ a2 b2 ai bi select’ select select m2(one-bit-mux) VDD oi VSS VDD oi VSS o2 a1 b1 ai bi select’ select m2(one-bit-mux) select’ select o1 a0 b0 ai bi m2(one-bit-mux) VDD oi VSS o0 204424 Digital Design Automation February 13.

Multiple-Bit Mux 204424 Digital Design Automation February 13. 2014 53 .

2014 54 . Overlap  Use mirroring. overlap to save area 204424 Digital Design Automation February 13.Cell Mirroring.

2014 55 .Example: Layout / Stick Diagram  Create a layout for a NAND gate given constraints:       Use minimum-size transistors Assume power supply lines “pass through” cell from left to right at top and bottom of cell Assume inputs are on left side of cell Assume output is on right side of cell Optimize cell to minimize width Optimize cell to minimize overall area 204424 Digital Design Automation February 13.

Exterior of Cell 204424 Digital Design Automation February 13. 2014 56 .Layout Example Circuit Diagram.

Magic Layout  Overall Layout: 52 X 16 204424 Digital Design Automation February 13.Example . 2014 57 .

Review - VLSI Levels of Abstraction
Specification
(what the chip does, inputs/outputs)

Architecture
major resources, connections

Register-Transfer
logic blocks, FSMs, connections

Logic
gates, flip-flops, latches, connections

Circuit
transistors, parasitics, connections

You are Here

Layout
mask layers, polygons
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Levels of Abstraction Perspective

Right now, we’re focusing on the “low level”:
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Circuit level - transistors, wires, parasitics Layout level - mask objects Logic level - individual gates, latches, flip-flops Register- transfer level - Verilog HDL Behavior level - Specifications

We’ll work upward to higher levels:
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The Challenge of Design

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Start: higher level (spec) Finish: lower level (implementation) Must meet design criteria and constraints

Design time - how long did it take to ship a product? Performance - how fast is the clock? Cost - NRE + unit cost

CAD tools - essential in modern design

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CAD Tool Survey: Layout Design      Layout Editors Design Rule Checkers (DRC) Circuit Extractors Layout vs. Schematic (LVS) Comparators Automatic Layout Tools   Layout Generators ASIC: Place/Route for Standard Cells. Gate Arrays 204424 Digital Design Automation February 13. 2014 61 .

LEdit. Mentor ICStation.easier to learn.Layout Editors   Goal: produce mask patterns for fabrication Grid type:   Absolute grid (MAX. other commercial tools) Magic: lambda-based grid . 2014 62  Mask description:   204424 Digital Design Automation . LASI. but less powerful Absolute mask (one layer for each mask) Magic: symbolic masks (layers combine to generate actual mask patterns) February 13.

especially for large chips 204424 Digital Design Automation February 13.Design Rule Checkers     Goal: identify design rule violations Often a separate tool (built in to Magic) General approach: “scanline” algorithm Computationally intensive. 2014 63 .

2014 64 .Circuit Extractors  Goal: extract netlist of equivalent circuit   Identify active components Identify parasitic components Capacitors  Resistors  204424 Digital Design Automation February 13.

2014 65 . schematic netlists    Compare transistors.Layout Versus Schematic (LVS)  Goal: Compare layout. connections (ignore parasitics) Issue error if two netlists are not equivalent Important for large designs 204424 Digital Design Automation February 13.

configurable pre-manufactured gates (only change metal masks) FPGAs . 95) Complex: Netlist . route modules with fixed shape    Standard Cells .Place. 2014 66 204424 Digital Design Automation .produce cell from spec.    Simple: Procedural specification of layout (see book Fig.places & wires individual transistors  ASIC .electrically configurable array of gates February 13. 2-33.Automatic Layout Tools  Layout Generators . p.use predefined cells as "cookie cutters" Gate Arrays .

Design rule checkers are generally batch--identify DRC errors on the layout. 2014 67 .Layout design and analysis tools     Layout editors are interactive tools. Connectivity verification systems (CVS) compare extracted and original netlists. Circuit extractors extract the netlist from the layout. 204424 Digital Design Automation February 13.

 Sea-of-gates allows routing over the cell. etc. Standard cell/sea-of-gates layout creates layout from predesigned cells + custom routing. 2014 68 . 204424 Digital Design Automation February 13.Automatic layout   Cell generators (macrocell generators) create optimized layouts for ALUs.

2014 69 .Standard cell layout routing area routing area routing area routing area 204424 Digital Design Automation February 13.