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Chapter 5 – The

Processor: Datapath
and
Control
Implementation of
Instruction sets

An instruction set architecture is an interface


that defines the hardware operations which are
available to software.
Any instruction set can be implemented in
many different ways. Over the next few weeks we’ll
see several possibilities.
— In a basic single-cycle implementation all
operations take the same amount of time—a single
cycle.
— In a multicycle implementation all
instructions is executed in multiple clock
cycles.
— Finally, pipelining lets a processor overlap
the execution of several instructions, potentially
BUILDING A DATAPATH
• Datapath element - A funtional unit
which is used to operate on or hold
data within a pracessor.
• 1 . Program counter [ PC ] - The
register which holds the address of
current instruction.

PC
Instruction Memory

 Memory unit to store


instructions of a program and
supply instructions given an
address.
Instruction Fetching
• The CPU is always in an infinite
loop, fetching instructions from
memory and executing them.
• The program counter or PC
register holds the address of the
current instruction.
• MIPS instructions are each four
bytes long, so the PC should be
incremented by four to read the
next instruction in sequence.
Register File

Our register file stores thirty-two 32-


bit values.
— Each register specifier is 5 bits
long.
— You can read from two registers at
a time.
— RegWrite is 1 if a register should be
written.

Here’s a simple ALU with five


operations, selected by ALU control
signal which is 4 bits wide.
Executing an R-type
instruction

1. Read an instruction from the


instruction memory.
2. The source registers, specified by
instruction fields rs and rt, should be
read from the register file.
3. The ALU performs the desired
operation.
4. Its result is stored in the destination
register, which is specified by field
rd of the instruction word.
R Type
Executing an I- Type
Instructions

1. Read an instruction from the


instruction memory.
2. For an instruction like lw $t0, 4($s2),
the base register $s2 is added with
the sign-extended constant [ 4 ] to get
a data memory address.
5.Data is read from data memory by
supplying an address.
4. Its result is stored in the destination
register, which is specified by field
rt of the instruction word.
rs

rt
Need of Multiplexors
The arithmetic and logical instructions
use the ALU with inputs coming from
two registers.The memory instructions
use ALU to do address calculation. 1
input – register , 2nd input – sign
extend.
The value stored into destination register
comes from ALU(R Type instructions) or
memory (load).
Steps in executing branches

1. Fetch the instruction, like beq $s1, $s2,


offset from memory.
2. Read the source registers, $s1 and $s2,
from the register file.
3. Compare the values by subtracting them
in the ALU.
4. If the subtraction result is 0, the source
operands were equal and the PC
should be loaded with the target address,
PC + 4 + (offset x 4).
5. Otherwise the branch should not be
taken, and the PC should just be
incremented to PC + 4 to fetch the next
instruction sequentially.
Need for additional
multiplexors
 An additional multiplexor is required to select
either the sequentially following instruction
address (PC+4) or branch target address to be
written into the PC.
 The destination register is in one of the 2
places.For a load, it is in bit positions 20:16(rt),
while for an R Type instruction, it is in bit
positions 15:11(rd).Thus we will need to add a
multiplexor to select which field of instruction
is used to indicate the register number to be
written .
Branching Hardware
Final Datapath

rs

rt

rd
R-Type Instruction Path
Lw instruction datapath
Sw instruction Datapath
beq instruction datapath
J - Format

31 26 25 o

Op address

For j instruction
Target address = PC[31-28] | | (offset
address << 2)
Datapath with control unit
ALU control Function
lines
0000 AND
0001
0010
0110
0111
1100