CISC is an acronym for Complex Instruction Set Computer and are chips that are easy to program and

which make efficient use of memory. Since the earliest machines were programmed in assembly language and memory was slow and expensive.

Pronounced sisk, and stands for Complex Instruction Set Computer. Most PC's use CPU based on this architecture For instance Intel and AMD CPU's are based on CISC architectures. Typically CISC chips have a large amount of different and complex instructions. The philosophy behind it is that hardware is always faster than software, therefore one should make a powerful instruction set, which provides programmers with assembly instructions to do a lot with short programs.

Pronounced risk, and stands for Reduced Instruction Set Computer. RISC chips evolved around the mid-1980 as a reaction at CISC chips. The philosophy behind it is that almost no one uses complex assembly language instructions as used by CISC, and people mostly use compilers which never use complex instructions. Therefore fewer, simpler and faster instructions would be better, than the large, complex and slower CISC instructions other advantage of RISC is that - more simple instructions, RISC chips require fewer transistors, which makes them easier to design and cheaper to produce. It's easier to write powerful optimized compilers, since fewer instructions exist.

CISC Emphasis on hardware Includes multi-clock complex instructions Memory-to-memory: "LOAD" and "STORE" incorporated in instructions RISC Emphasis on software Single-clock,reduced instruction only Register to register:"LOAD" and "STORE" are independent instructions Low cycles per second large code sizes Spends more transistors on memory

Small code sizes, high cycles per second Transistors used for storing complex instructions registers

So simply say: RISC and CISC are growing to each other .RISC and CISC architectures are becoming more and more alike. Many of today's RISC chips support just as many instructions as yesterday's CISC chips.

Processor Architecture • Princeton – Princeton provided ‘Von Neumann’ architecture where common memory space are used for storing program and data. Memory unit is responsible for arbitrary access to memory space between reading instructions and passing data back and forth with processor and its internal registers. . • Advantages: simple memory interfacing and management.

Princeton architecture block diagram instruction decode program ROM Data Add Ctrl Variable RAM memory interface unit Processor and builtin registers Stack RAM .

• Advantage: execute instruction in fewer cycles than Von Neumann . and variable RAM. the processor stack.– Harvard proposes a design that used separate memory banks for program storage.

Harvard architecture block diagram Data Add Ctrl instruction decode PC Stack program ROM Processor and built-in registers Data Add Ctrl Variable RAM .

• Microcontroller primarily differ from a microprocessor in the areas of built-in peripheral features. DMA. . interrupt controllers. timers. These features could include memory device selection. and IO devices like serial ports.

PIC architecture is a “Harvard” architecture • The Harvard Architecture .

Feature of Harvard architecture • Near all instructions are single instruction word instructions – Only one fetch per instruction • Instruction fetch and execute are pipelined so you can operate at near clock rate instructions per second • 2 separate buses – One for instructions and one for data .

. It also makes it feasible to build complex multi-step instructions while still reducing the complexity of the electronic circuitry compared to other methods. network processors. disk controllers. graphics processing units. It resides in special high-speed memory and translates machine instructions into sequences of detailed circuit-level operations. and in the implementation of the internal logic of many channel controllers.Microcode is a layer of hardware-level instructions or data structures involved in the implementation of higher level machine code instructions in central processing units. network interface controllers. Writing microcode is often called microprogramming and the microcode in a particular processor implementation is sometimes called a microprogram. and other hardware. It helps separate the machine instructions from the underlying electronics so that instructions can be designed and altered more freely.

not even by an assembly programmer. Microcode is generally not visible or changeable by a normal programmer. or a combination of both machines also exist which have some (or all) microcode stored in SRAM or flash memory Complex digital processors may also employ more than one (possibly microcode based) control unit in order to delegate sub-tasks which must be performed (more or less) asynchronously in parallel.Modern microcode is normally written by an engineer during the processor design phase and stored in a ROM (read-only memory) or PLA (programmable logic array)[1] structure. . microcode only runs on the exact electronic circuitry for which it is designed. as it constitutes an inherent part of the particular processor design itself. Unlike machine code which often retains some compatibility among different processors in a family.

whether microcode or machine code. one clock cycle for each step in the microprogram for that instruction. so that all code in a device. Some CISC processors include instructions that can take a very long time to execute.Some hardware vendors. especially IBM. . what is far more important in modern systems. pipelining. use the term as a synonym for firmware. Such variations interfere with both interrupt latency and. which typically contains both) A CPU that uses microcode generally takes several clock cycles to execute a single instruction. is termed microcode (such as in a hard drive for instance.

a hardwired control RISC has these advantages over microcoded CISC: •Programming has largely moved away from assembly level. avoiding the performance penalty of microcoded execution. and are difficult to pipeline for increased performance.Complex microcoded instructions may require many clock cycles which vary. Many RISC and VLIW processors are designed to execute every instruction (as long as it is in the cache) in a single cycle . When designing a new processor. so it's no longer worthwhile to provide complex instructions for productivity reasons. •Simpler instruction sets allow direct execution by hardware.

. The instruction loaded into the instruction holding register is used to initiate a specific portion of the execution logic that carries out all the functions of the instruction.A hardwired processor uses the bit pattern of the instruction to access specific logic gates (possibly unique to the instruction) that are executed as a combinatorial circuit to carry out the instruction.


The 8-bit PIC microcontroller is divided into following four categories on the basis of internal architecture: 1. . These microcontrollers work on 12-bit instruction architecture which means that the word size of instruction sets are of 12 bits for these controllers. PIC18 Base Line PIC Base Line PICs are the least complex PIC microcontrollers. in industries. Enhanced Mid-Range PIC 4. Mid-Range PIC 3. The small size and low cost of Base Line PIC replaced the traditional ICs like 555. available with 6 to 40 pin packaging. These are smallest and cheapest PICs. logic gates etc. Base Line PIC 2.

. LIN. Ethernet (TCP/IP protocol) to communicate with local and/or internet based networks. The PIC18 range is integrated with new age communication protocols like USB. PIC18 PIC18 range is based on 16-bit instruction architecture incorporating advanced RISC architecture which makes it highest performer among the all 8-bit PIC families. I2C (TWI). SPI. I2C and so on. SPI. PWM. These microcontrollers are available with different peripherals like ADC. Op-Amps and different communication protocols like USART. This range of controllers provides additional performance.Mid-Range PIC Mid-Range PICs are based on 14-bit instruction architecture and are able to work up to 20 MHz speed. etc. greater flash memory and high speed at very low power consumption. This range also supports the connectivity of Human Interface Devices like touch panels etc. CAN. These controllers are available with 8 to 64 pin packaging. which make them widely usable microcontrollers not only for industry but for hobbyists as well. This range of PIC also includes multiple peripherals and supports protocols like USART. Enhanced Mid-Range PIC These controllers are enhanced version of Mid-Range core.

of Pins Program Memory Data Memory Instruction Length 6-40 Up to 3 KB Up to 134 Bytes 12-bit 8-64 Up to 14 KB Up to 368 Bytes 14-bit 8-64 Up to 28 KB Up to 1.PIC12. of instruction set 33 35 49 83 Speed 5 MIPS* • Comparator • 8-bit ADC • Data Memory •Internal Oscillator 5 MIPS 8 MIPS Up to 16 MIPS Feature In addition of baseline · SPI · I2C · UART · PWM · 10-bit ADC · OP-Amps In addition of Mid-range · High Performance · Multiple communication peripherals In addition of Enhanced Midrange • CAN • LIN • USB • Ethernet • 12-bit ADC Families PIC10. PIC16 PIC12.*MIPS stand for Millions of Instructions per Second Base Line Mid-Range Enhanced Mid-Range PIC18 No. PIC16 PIC12F1XXX. PIC16F1XXX PIC18 .5 KB 14-bit 18-100 Up to 128 KB Up to 4 KB 16-bit No.

They are denoted with different symbols as given in the following table: Symbol Memory Type Example C EPROM PIC16Cxxx CR Mask ROM PIC16CRxxx F Flash memory PIC16Fxxx The letter ‘L’ is included in controller’s name to denote extended voltage range controllers. For example.Memory variations: The PIC microcontrollers are available with different memory options which are mask ROM.0 volts). EPROM and flash memory. .0-6. PIC16LFxxx (Operating voltage 2.




Program Memory (ROM) External Internal Data Memory (RAM) Direct Indirect SFR’s .

which makes the access to each one of them very easy.A memory that contains the program(which we had written). one after the other. then what about them being based on 14-bit instructions set. which contains a special registers like SFR (Special Faction Register) and GPR (General Purpose Register).A memory that allows storing the variables as a result of burning the written program. As a reminder. Data Memory – This is RAM memory type. These two memories have separated data buses. ‘PIC16 is an 8-bit microcontroller’ this statement means that the CPU core can receive/transmit or process a maximum of 8-bit data at a time. Program Counter executes commands stored in the program memory. The variables that we store in the Data Memory during the program are deleted after we turn of the micro. Data EEPROM (Electrically Erasable Programmable Read-Only Memory) . . The data memory is interfaced with 8-bit bus and program memory is interfaced with 16-bit bus Memory of the PIC16F87x divided into 3 types of memories: Program Memory . after we've burned it.The question may arise that if PIC16 are called 8-bit microcontrollers.

There are four SFRs used to read and write this memory. This memory is not directly mapped in the register file space. Instead it is indirectly addressed through the Special Function Registers.The EEPROM data memory is readable and writable during normal operation (full VDD range). These registers are: • EECON1 • EECON2 • EEDATA • EEADR .


while EECON2 is the register used to initiate the read/write. The 8-bit EEADR register can access up to 256 locations of Data EEPROM. EECON1 contains the control bits.EEDATA holds the 8-bit data for read/write EEADR holds the address of the EEPROM location being accessed. The device programmer can no longer access this memory. . When the device is code protected. the CPU may continue to read and write the data EEPROM memory.

Program memory is not generally changed during program execution. including control store and firmware (as well as some permutations of these names). The name really isn’t important. and the application code is stored in it using custom chip programming equipment. . as long as you understand that this memory space is used to store the application software. The program memory space is the maximum size of application that can be loaded into the microcontroller and contains all the code that is executed in an application along with the initial values for the variables used in the application.Program memory is known by a number of different names.

Program Memory Organization     The PIC16F87X devices have a 13-bit program counter capable of addressing an 8K x 14 program memory space. The PIC16F877/876 devices have 8K x 14 words of FLASH program memory. . Accessing a location above the physically implemented address will cause a wraparound. The RESET vector is at 0000h and the interrupt vector is at 0004h.

The low byte comes from the PCL register. which is a readable and writable register.Program counter:•The program counter (PC) is 13-bits wide. •The upper bits (PC<12:8>) are not readable. . but are indirectly writable through the PCLATH register.

and each word contains a single 14-bit wide instruction. When a GOTO or CALL instruction is executed. PCLATH<4:3> is used to select the page branched to. the program memory for the 14-bit core microcontroller has a limit of 8K words. It is physically carried out as a combination of a 5-bit register PCLATH for the five higher bits of the address.e. By its incrementing or change (i. or 4 pages of 2K words each. 2. The PCLATH register is used to select which page the next execution branch will go to. . The microcontroller uses its data memory (Register file) to move among the pages. and the 8-bit register PCL for the lower 8 bits of the address. • For example. PCLATH<4:0> is used with PCL to form the full PC address of the next instruction to be executed. The program memory is divided into 1.• Program counter and stack Program Counter Program counter (PC) is a 13-bit register that contains the address of the instruction being executed. When the PCL is modified by user code. in case of jumps) microcontroller executes program instructions step-by-step.


When an interrupt occurs during code execution. Little useful code can be placed at the start of Program Memory if interrupts are used.As you can see on this diagram. code execution begins at the reset vector . the next instruction address to be fetched (whatever it is) is saved to the stack and execution branches to the interrupt vector at location 4. . servicing the interrupt can begin at this vector location. Often. instructions to load PCLATH and a GOTO at this location will cause execution to branch to somewhere else in memory. Page 0 contains the Reset vector at location 0(0000h). After a reset. Alternatively.

•The PC is PUSHed onto the stack when a CALL instruction is executed.RETLW or a RETFIE instruction execution. •The stack is POPed in the event of a RETURN. or an interrupt causes a branch.STACK •The PIC16F87X family has an 8-level deep x 13-bit wide hardware stack. . The stack space is not part of either pro-gram or data space and the stack pointer is not readable or writable.

When you use subroutines and interrupts it will be essential to have such a storage region. A stack is usually maintained as a "last in. In order for a program to know how to go back to the point where it started from. a group of 8 memory locations. . When you take something OFF of the stack (PULL from the stack). with special purpose. Its basic role is to keep the value of program counter after a jump from the main program to an address of a subprogram . including functions. it has to return the value of a program counter from a stack. etc. first out" (LIFO) data structure. so that the last item added to the structure is the first item used. A reserved area of memory used to keep track of a program's internal operations. Sometimes is useful to have a region of memory for temporary storage . or in other words. 13 bits wide. the SP is decremented before the item is placed on the stack. which does not have to be allocated as named variables.PIC16F84 has a 13-bit stack with 8 levels. passed parameters. Such region is called a Stack When you PUT something ONTO the stack (PUSH onto the stack). the SP is incremented after the item is pulled from the stack. return addresses.


calibration data for different peripherals. The processor addressing modes . which is used for the temporary storage of data. The nonvolatile data memory provides long-term storage of information even when power is lost.The variable memory available in an embedded microcontroller consists of a fairly small amount of RAM (random-access memory). Variable memory is volatile. . and IP address information for networked devices. were primarily referring to accessing the variable memory of a microcontroller. which means that its values will be lost when power is removed from the microcontroller. Typical information stored in this memory includes data logging information for later transmittal to another device.



This memory is shared across all banks. but will be available in all banks. Labels for variables in the shared memory region should be declared only once. Some addresses in these sections have no SFR and are not implemented. In other words. this shared memory is usually the last 16 bytes of each bank. the RP1 and RP0 bits in the STATUS register select the desired bank for direct memory access. the same memory location within a bank can be accessed in all banks without having to select a different bank. . Some PIC micro devices have a shared data memory region. Within each bank. Some of these Special Function Registers (SFR) appear in all banks such as the STATUS and File Select Register (FSR) . 7 bits of addressing select 1 of 128 addresses. If it is present. in a microcontroller with 4 banks of data memory. Therefore. 9 bits are required to uniquely address any data memory location. When direct addressing is used.The first 32 bytes in each bank are reserved for Special Function Registers. in any bank.


. the IRP bit is used to select either Banks 0 and 1. or Banks 2 and 3 for indirect addressing.When indirect addressing is used. The FSR register provides the remaining 8 bits of address data.