Architecture and instruction set

Microcontroller Core Features:

Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle
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Up to 8K x 14 words of FLASH Program Memory, Up to 368 x 8 bytes of Data Memory (RAM) Up to 256 x 8 bytes of EEPROM Data Memory

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Pinout compatible to the PIC16C73B/74B/76/77 Interrupt capability (up to 14 sources) Eight level deep hardware stack Direct, indirect and relative addressing modes Power-on Reset (POR) Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation Programmable code protection Power saving SLEEP mode Selectable oscillator options

Peripheral Features
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Timer0: 8-bit timer/counter with 8-bit prescaler Timer1: 16-bit timer/counter with prescaler, can be incremented during SLEEP via external crystal/clock Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler Two Capture, Compare, PWM modules


Capture is 16-bit, max. resolution is 12.5 ns Compare is 16-bit, max. resolution is 200 ns PWM max. resolution is 10-bit

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10-bit multi-channel Analog-to-Digital converter Synchronous Serial Port (SSP) with SPI (Master mode) and I2C (Master/Slave) Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI) with 9-bit address detection Parallel Slave Port (PSP) 8-bits wide, with external RD, WR and CS controls (40/44-pin only) Brown-out detection circuitry for Brown-out Reset (BOR)

. The RESET vector is at 0000h and the interrupt vector is at 0004h. Accessing a location above the physically implemented address will cause a wraparound.Program Memory Organization     The PIC16F87X devices have a 13-bit program counter capable of addressing an 8K x 14 program memory space. The PIC16F877/876 devices have 8K x 14 words of FLASH program memory.

Above the Special Function Registers are General Purpose Registers. The lower locations of each bank are reserved for the Special Function Registers.Data Memory Organization       The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers. Each bank extends up to 7Fh (128 bytes). All implemented banks contain Special Function Registers. . Some frequently used Special Function Registers from one bank may be mirrored in another bank for code reduction and quicker access. Bits RP1 (STATUS<6>) and RP0 (STATUS<5>) are the bank select bits. implemented as static RAM.

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.  First we need to go to Bank 1 to set the particular bit.  An example is as follows:  Let us say we want to make one bit on Port A high. on Port A as an output.What are the two/four banks for?    Memory space is organized in 128Byte banks. PIC 16F684 has two banks . Bank 1 is used to control the actual operation of the PIC for example to tell the PIC which bits of Port A are input and which are output.  Bank 0 is used to manipulate the data.  We then come back to Bank 0 and send a logic 1 (bit 1) to that pin.Bank 0 and Bank 1. or pin.

184h).80h.Special Function Registers  W. 82h.100h. 8Ah. File Select Register  Indirect data memory addressing pointer INDF (00h. the Program Counter. 10Ah.180h) accessing INDF accesses the location pointed by IRP+FSR  PC. 102h. 182h) and PCLATH (0Ah.  FSR (04h. the working register.104h.84h. PCL (02h. the value must pass through the W register. To move values from one register to another register. 18Ah) .

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Direct/Indirect Addressing .

Direct Addressing  Use only 7 bits of instruction to identify a register file address. RP1 . other XORWF STATUS. BCF STATUS. F . RP0 . MOVLW 0x60 .  The other two bits of register address come from RP0 and RP1 bits in the STATUS register  Example: Bank switching (Note: case of 4 banks)             CLRF STATUS . BCF STATUS. RP0 . BSF STATUS. RP0 . Bank0 :. Set RP0 and RP1 in STATUS register. Bank1 :. BCF STATUS. Clear STATUS register (Bank0) :. Bank2 :. Bank0 . bits unchanged (Bank3) :.

inc pointer BTFSS FSR. Addressing the INDF register will cause indirect addressing.Indirect Addressing  The INDF register is not a physical register.all done? (to 0x2F) GOTO NEXT .to RAM NEXT: CLRF INDF .no clear next CONTINUE:  .clear INDF register INCF FSR.yes continue .  The effective 9-bit address is obtained by concatenating the 8-bit  FSR register and the IRP bit in STATUS register.4 .initialize pointer MOVWF FSR .  Any instruction using the INDF register actually access the register  pointed to by the File Select Register (FSR).  Example        MOVLW 0x20 .F .

while a ‘0’ corresponds to that pin being an output  The PORTx register is the latch for the data to be output. .E).I/O Ports  General I/O pins are the simplest of peripherals used to monitor and control other devices.D. the I/O pin’s direction (input or output) is controlled by the data direction register TRISx (x=A. whereas writing to it will write to the port latch.  For most ports.B.  A ‘1’ in the TRIS bit corresponds to that pin being an input. Reading PORTx register read the status of the pins.C.

RP0 . RP0 . value used to initialize data direction (1100 1111) movwf TRISD . initializing PORTD by clearing output data latches bsf STATUS. PORTD<7:6>=inputs. PORTD<3:0>=inputs . RP1 clrf PORTD . . select bank1 movlw 0xCF .Example: Initializing PORTD       bcf STATUS.PORTD<5:4>=outputs. bank0 bcf STATUS.

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INSTRUCTIONS 33-35  SLEEP  CLRWDT  NOP .