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Basic Planar Processes

Basic Planar Processes
• • • • • • • • • The basic processes used to fabricate ICs using silicon planar technology can be categorised as follows: Silicon Wafer (substrate) Preparation Epitaxial Growth Oxidation Photolithography Diffusion Ion Implantation Isolation Technique Metallization Assembly processing and packaging

Silicon Wafer Preparation
Steps Involved in Silicon Wafer Preparation : 1. Crystal Growth and Doping 2. Ingot Trimming and grinding 3. Ingot slicing 4. Wafer polishing and Etching 5. Wafer Cleaning

Crystal Growth & Doping
• Highly purified (99.99999) polycrystalline silicon. (Starting Material)
• Czochralski crystal growth process - most often used for producing single pure silicon crystal • PC Si + Appropriate amount of dopant is put in quartz crucible & is then placed in a furance. • Material is heated above 14200C

• A small single crystal rod of silicon called a seed crystal is then dipped into the silicon melt and slowly pulled out
• During the crystal pulling process, the seed crystal and the crucible are rotated in opposite directions in order to produce ingots of circular cross-section. • The diameter of the ingot is controlled by the pulling rate and the melt temperature.

Aluminium Ingot

Ingot Trimming & Grinding
• Top and Bottom portions of the ingot are cut off and the ingot surface is ground to produce an exact diameter • The ingot is also ground flat slightly along the length to get a reference plane.

Reference plane

Ingot Slicing
• The ingot is then sliced using a stainless steel saw blade with industrial diamonds embedded into the inner diameter cutting edge. This produces circular wafers or slices .

Wafer Polishing & Etching
• Due to the machining operations during trimming, grinding and slicing, the surface and edges of the wafers get contaminated and even damaged. • By using chemical etching process, all the damaged and contaminated edges can be removed. • The silicon wafers so obtained have very rough surface due to slicing operation, therefore these wafers undergo a number of polishing steps to produce a smooth flat surface

Wafer Cleaning
• Finally the wafers are thoroughly rinsed and dried • These silicon wafers will contain several hundred rectangular chips, each one containing a complete integrated circuit.

Epitaxial Growth
• Epitaxy means arranged upon • Epitaxy is the growth of a thin layer of single crystal material on the surface of the wafer • Epitaxy layer formed on the substrate may be either n-doped or p-doped • For p-type Doping bi-borane and For n-type doping phosphine are used with steam of silicon tetrachloride hydrogen gas.

Epitaxial Growth
• The process is carried out in a reaction chamber consisting of a long cylindrical quartz tube encircled by an RF induction coil. • The Si wafers placed on a rectangular graphite rod called a boat. • This boat is then placed in the reaction chamber where the graphite is heated inductively to 1200 degree C • The various gases required for the growth of desired epitaxial layers are introduced into the system through a control console.

• The process in which a thin/thick layer of silicon dioxide formed on a surface of silicon wafer using thermal growth technique is called oxidation. • Reason for selecting SiO2 1. Extremely hard protective coating and is unaffected by almost all reagents except hydrofluoric acid. 2. Mask in the etching of Si Substrates

Mask Meaning

• The silicon wafers are stacked up in a fused quartz cassette and then inserted into quartz furnace tube. • The Si wafers are raised to a high temperature in the range of 950 to 1115 degree C and at the same time exposed to a gas containing oxygen or water vapour or both.

• The thickness of the film is governed by time, temperature and the moisture content

• Photo-litho-graphy: latin- light-stone-writing • It is an optical means for transferring patterns onto a substrate • As many as 10,000 transistors can be fabricated on a 1 cm * 1cm chip. • The conventional photolithographic process uses UV and device dimension as small as 2micro-meter can be obtained. • Nowadays using X-Ray or Electron Beam Lithographic techniques, device dimension down to submicron range (<1 micro meter)

• Photolithography involves three processes : 1. Development 2. Etching 3. Photoresist Removal


• The mask is removed and the wafer is developed using a chemical which depends on what type of photoresist used. • The chip is immersed in the etching solution of hydrofluoric acid, which removes the SiO2 from the areas which are not protected by photoresist. • After diffusion of impurities, the photoresist is removed with a chemical solvent (hot sulphuric acid) and mechanical abrasion.

• The process of doping i.e., adding impurity to the silicon wafer is called diffusion • This uses a high temperature furnace having a flat temperature profile over a useful length

• A quartz boat containing cleaned wafers is pushed into the hot zone with temperature maintained at abt 1000 0C. • Impurities to be diffused are rarely used in their elemental forms. • Compounds like boron oxide, boron chloride are used for boron & phosphorous pentaoxide, phosphorous oxychloride are used as soures of Phosphorous.

• A carrier gas such as dry oxygen or nitrogen is normally used for sweeping the impurity to the high temperature zone. • The depth of diffusion depends upon the time of diffusion which normally extends to 2 hours

Ion Implantation
• It is the other technique used to introduce impurities into a silicon wafer.

Ion Implantation
• Silicon wafers are placed in a vacuum and are scanned by a beam of high energy dopant ions (borons for p-type & phosphorous for n-type) • These ions are accelerated by energies between 20 kV to 250kV. • As the ions strike the silicon wafers, they penetrate some small distance into the wafer.

Advantage of Ion Implantation
1.Performed at low temp. 2.In diffusion, temp has to be controlled over a large area inside the oven where as here, accelerating potential and the beam current are electrically controlled from outside.

Disadvantage of Ion Implantation
• The Dopant distribution in the substrate is less uniform

Isolation Techniques
•Since a number of components are fabricated on the same IC chip, it becomes necessary to provide electrical isolation between different components and interconnections. •Two techniques: 1. pn junction isolation 2. Dielectric isolation

• The purpose of this process is to produce a thin metal film layer that will serve to make interconnections of the various components on the chip. • Al is used for the metallization of most ICs. Reasons – 1. A good conductor, easy to deposit Al films using vacuum deposition, 2. Al makes good mechanical bonds with Si 3. Al forms low resistance, ohmic contacts with heavily doped n-type Si and p-type Si.

• Process takes place in a Vacuum Evaporation Chamber • The pressure in the chamber is reduced to the range of abt 10-6 to 10-7 Torr. • The material to be evaporated is placed in a resistance heated tungsten coil or basket. • A very high power density electron beam is focussed at the surface of the material to be evaporated.


• This heats up the material to very high temp & it starts vaporizing. These vapours travel in straight line paths. • The evaporated molecules hit the substrate and condense there to form a thin film coating. • After thin film metallization is done, the film is patterned to produce the required interconnections and the bonding pad configuration. This is done by photolithographic process. • Al is etched away from unwanted places by using mixture of phosphoric acid, nitric acid & acetic acid


Assembly Processing & Packaging
• Scribing & Separating into chips • Mounting & Packaging • Encapsulation

• Linear Integrated Circuits by D. Roy Choudhury & S B Jain