Design of an 8 Bit Barrel Shifter

Gene Vea, Perry Hung, Ricardo Rosas, Kevin Yoo Advisor: D. Parent May 11, 2005
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Agenda
Abstract Introduction
Why Simple Theory Back Ground information (Lit Review)

Summary of Results Project (Experimental) Details Results Cost Analysis Conclusions

Abstract
Summarize the logic, clock frequency, area, and power specs of your final design We designed an 8-bit barrel shifter that operated at 200 MHz 20mW of Power Area of 370x350 mm2

Introduction
The barrel shifter is a very important part of a combinational logic block. It was incorporated the 386 processor and is also used in microcontrollers. Intel has since moved on to software implemented barrel shifters in their Pentium 4s but AMD still uses it to this day. The designed circuit should shift a data word by any number of bits in a single operation. An N-bit shifter would require log2N number of levels to implement. For an 8 bit barrel shifter, it would require 3 logic levels.
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Project Summary
Project was implemented with an array of 24 MUXs and 19 DFF MUXs arranged in three stages. Implemented with the new DFF MUXs designed in class

Project Details
Explain all the details of your project.
Schematics should be legible, and not too busy. If you did a set of experiments describe the conditions you did them under. show a table with all hand calculations for your longest path

Show
Final schematic (not test bench) Final layout Final simulation
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Longest Path Calculations

Logic Level 1 1a 1b 1c 2 2a 3 3a 4 4a 5 Mux-DFF Slave Nand Mux-DFF Slave Latch Mux-DFF Master Nand Mux-DFF Master Latch Inveter Mux (AOI22) Inveter MUX (AOI22) Inveter MUX (AOI22) Superbuffer inverter 1 Gate Cg to Drive 17.1 5.99 17.1 5.99 20 8.43 40 13.6 32 11.1 17.8 240 1 2 1 2 1 6 1 6 1 6 4 1 2 2 2 2 1 6 1 6 1 6 4 1 #N #M #NS N 1 2 1 2 1 2 1 2 1 2 2 1 #NS P 2 2 2 2 1 2 1 2 1 2 2 1 WN (H.C) 1.96 3.96 3 3.96 1.5 4.31 2.86 3.46 2.32 3.45 3.7 26.7 WP (H.C) 1.63 6.8 2.55 6.8 2.7 7.49 5.14 5.99 4.17 6.15 6.36 49.2 WN (S) 3.9 3.9 3.9 3.9 1.95 2.85 3 2.25 3 3.45 3.7 26.7 WP (S) 3.45 6.85 3.45 6.85 3 4.65 6 3.9 6 6.15 6.36 49.2 WN (L) 1.96 3.96 1.96 3.96 1.95 2.85 3 2.25 3 3.45 3.7 26.7 WP (L) 1.63 6.8 1.63 6.8 3 4.65 6 3.9 6 6.15 6.36 49.2 Cg of gate 5.99 18.3 5.99 18.3 8.43 20.1 13.6 16.1 11.1 16.4 12

Schematic

Layout

Verification

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Simulations

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Cost Analysis
Estimate how much time you spent on each phase of the project
verifying logic (40 hours) verifying timing (10 hours) Layout (many hours 100+ hours) Post extracted timing (3 hours)

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Lessons Learned
Start early Using the excel sheet to calculate Wn & Wp Make sure to use the correct devices for layout if the same type of parts are used more than once. Plan device schematic carefully and attack it part by part making sure that it works with the other parts of the circuit Problems will always come up during LVS no matter how carefully it was wired together. Because a device passes DRC does not mean that it will pass LVS when placed in layout
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Summary
Barrel shifters have the ability to shift data words in a single operation over standard shift left or shift right registers that utilize more than one clock cycle. Barrel shifters will continue to be used in smaller devices because it has a speed advantage over software implemented ones.

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Acknowledgements
Cadence Design Systems Synopsys Prof. Parent David Flores Junghoon Kang

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