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Copyright 2003  Mani Srivastava
Four Phases in Creating a Chip
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Copyright 2003  Mani Srivastava
The Design Problem
Source: sematech97
A growing gap between design complexity and design productivity
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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Copyright 2003  Mani Srivastava
Designing a VLSI
 Economic viability affected by design time
 Design time affected by the efficiency of
concept  requirements  architecture
 logic/memory  circuit  layout
 Continuous trade-off between
 performance (speed, area, power)
 size of die (hence cost of die and packaging)
 time of design (hence cost of engineering & schedule)
 ease of test generation and testability
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Copyright 2003  Mani Srivastava
VLSI-design Tools &
Methodologies
 Goal is to reduce complexity, increase productivity,
and increase chances of a working chip
 Key is the use of Constraints and Abstractions
 Constraints
– help automate the procedure by simplifying the problem
 Abstractions
– collapse detail and arrive at a simpler problem to deal
with
 Different design methodologies
 different types of constraints and trade-offs
 choice driven by economics!
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Copyright 2003  Mani Srivastava
Design Domains
 Behavioral
 what a system does

 Structural
 how entities are connected together to perform the
behavior

 Physical (geometrical)
 how to build a structure that has the required
connectivity to implement the prescribed behavior
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Copyright 2003  Mani Srivastava
Levels of Design Abstractions for
Each Design Domain
 Architectural
 Algorithmic
 Module or functional block
 Logical
 Switch
 Circuit
 Device
etc.
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Copyright 2003  Mani Srivastava
Design Abstraction Levels
SYSTEM
GATE
CIRCUIT
V
out
V
in

CIRCUIT
V
out
V
in

MODULE
+
DEVICE
n+
S D
n+
G
Adapted from Irwin & Nayaranan‘s Slides from PSU. Copyright 2002 J. Rabaey et al."
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Copyright 2003  Mani Srivastava
A More Simplified Flow
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Copyright 2003  Mani Srivastava
Principles of Structured Design
Techniques
 Hierarchy

 Regularity

 Modularity

 Locality
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Copyright 2003  Mani Srivastava
Hierarchy
 Divide and conquer
 compose system from simpler widgets
 Analogy with software
 break large programs into threads and subroutines
 Hierarchy can be there in all domains
 behavior, structural, physical
 The hierarchy in different domains may not
correspond
 e.g. a structural hierarchy may not map well to
physical
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Copyright 2003  Mani Srivastava
Example of Structural Hierarchy
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Copyright 2003  Mani Srivastava
Regularity
 Hierarchy breaks a system into submodules
 but this may not solve the complexity problem
 there may not be any regularity in the subdivision
– we just end up with a large # of different submodules

 Regularity as a guide
 subdivide into a set of similar building blocks
– e.g. RAM composed of identical cells

 Regularity means that the hierarchical decomposition of a
large system should result in not only simple, but also
similar blocks, as much as possible
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Copyright 2003  Mani Srivastava
Regularity (contd.)
 Regularity can be at all levels
 circuit: use identically sized transistors
 gate: similar gate structures
 higher level: architectures with identical processors

 Regularity helps in many ways
 correct by construction
 reuse of design
 simplify verification of correctness
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Copyright 2003  Mani Srivastava
Modularity
Condition that sub modules have ―well-defined‖
functions and interfaces
 in addition to regularity and hierarchy
 ‗Well-formed‖ modules allow their interaction with
others to be ―well-characterized‖
 Depends on the situation
 e.g. in s/w a subroutine has a well-defined interface
– argument list with typed variables
 e.g. in IC a well-defined physical, structural, and
behavioral interface
– pin position, layer, size, signal type, electrical
characteristics, logic function
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Copyright 2003  Mani Srivastava
Why Modularity?
 Allows the design of system to be broken up
with confidence that the system will work as
specified when the parts are combined
 Allows team design by a number of designers
 Examples:
 bad use: use of transmission gates as inputs
– internal signals now depend on source impedance
 bad use: use dynamic CMOS logic but fail to latch
or register the inputs
– timing of each module will have to be checked
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Copyright 2003  Mani Srivastava
Locality
 Modularity provided ―well-characterized‖ interfaces
 internals of modules unimportant to exterior interface
• internal details remain at the local level
 a form of ―information hiding‖
• reduces apparent complexity of the module
Locality ensures that connections are between neighboring
modules, avoiding long-distance connections
 Example: timing locality so that time critical operations are local
• clock generation and distribution network
• entire clock cycle for global signals to traverse chip
• placement so that global wiring is minimized
 Analogy with software
• global variables are to be avoided
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Copyright 2003  Mani Srivastava
Parallels between H/W & S/W
Design
 Strong parallels in the way VLSIs are designed
and the way complex software is
 HDLs used to describe hardware systems in
essence merge these two disciplines
 software methods used to define hardware
 Hardware-software Co-design
 But, can‘t ignore hardware aspects entirely
 important since a physical chip is the end product
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Copyright 2003  Mani Srivastava
T
y
p
i
c
a
l

V
L
S
I

D
e
s
i
g
n

F
l
o
w

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Copyright 2003  Mani Srivastava
Types of Tools
 Analysis and verification

 Implementation and synthesis

 Testability techniques
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Copyright 2003  Mani Srivastava
Design Analysis and Verification
 Accounts for largest fraction of design time
 More efficient when done at higher levels of
abstraction
 select of correct analysis level can reduce
verification time by orders of magnitude
 Two approaches:
 simulation: depends on choice of excitation
 verification: extracts desired results directly from
circuit description

[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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Copyright 2003  Mani Srivastava
Simulation Approaches
 Key distinction is how are data & time represented?
 Circuit-level simulation (e.g. Spice)
 Switch-level simulation (e.g. IRSIM)
– transistors as switches with resistance
 Gate-level (logic) simulation
– now obsolete due to logic synthesis
 Functional simulation (e.g. VHDL, Verilog)
– primitives of arbitrary complexity
 Behavioral simulation (e.g. VHDL)
– only mimic I/O functionality
– hardware delay loses its meaning
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Copyright 2003  Mani Srivastava
Structural Description of
Accumulator
entity accumulator is
port ( --
definition of input and output terminals
DI: in bit_vector(15 downto 0) --
a vector of 16 bit wide
DO: inout bit_vector(15 downto 0);
CLK: in bit
);
end accumulator;
architecture structure of accumulator is
component reg --
definition of register ports
port (
DI : in bit_vector(15 downto 0);
DO : out bit_vector(15 downto 0);
CLK : in bit
);
end component;
component add --
definition of adder ports
port (
IN0 : in bit_vector(15 downto 0);
IN1 : in bit_vector(15 downto 0);
OUT0 : out bit_vector(15 downto 0)
);
end component;
--
definition of accumulator structure
signal X : bit_vector(15 downto 0);
begin
add1 : add
port map (DI, DO, X); --
defines port connectivity
reg1 : reg
port map (X, DO, CLK);
end structure;
Design defined as composition of
register and full-adder cells (―netlist‖)

Data represented as {0,1,Z}

Time discretized and progresses with
unit steps
Description language: VHDL
Other options: schematics, Verilog
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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Copyright 2003  Mani Srivastava
Behavioral Description of
Accumulator
entity accumulator is
port (
DI : in integer;
DO : inout integer := 0;
CLK : in bit
);
end accumulator;
architecture behavior of accumulator is
begin
process(CLK)
variable X : integer := 0; --
intermediate variable
begin
if CLK = '1' then
X <= DO + D1;
DO <= X;
end if;
end process;
end behavior;
Design described as set of input-output
relations, regardless of chosen
implementation


Data described at higher abstraction
level (―integer‖)
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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Copyright 2003  Mani Srivastava
Behavioral Simulation of
Accumulator
Integer data
Discrete time
(Synopsys Waves display tool)
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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Copyright 2003  Mani Srivastava
Timing Analysis (contd.)
 Unlike simulation, timing analysis is value-independent—
doesn‘t require specifying inputs.
 Simulation can be optimistic—you may not apply worst-
case input vector.
 Timing analysis can be pessimistic, but that is safer than
optimistic.
 Must apply worst case to find longest delay:
Modern VLSI Design 3e: Chapter 10, Copyright © 1998, 2002 Prentice Hall PTR

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Copyright 2003  Mani Srivastava
Timing Analysis Procedure
 Two major steps:
 build graph with elemental delays;
 traverse graph to find longest path.
 Must model 0-1 and 1-0 delays independently
for more accurate total delay.
 Use value analysis to prune impossible paths.
 False paths create unexcercisable paths which
make delay pessimistic. Can be identified using
analysis algorithms.
Modern VLSI Design 3e: Chapter 10, Copyright © 1998, 2002 Prentice Hall PTR

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Copyright 2003  Mani Srivastava
Issues in Timing Analysis
bypass
4-bit adder
M
U
X
Out
In
False Timing Paths
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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Copyright 2003  Mani Srivastava
Design Verification
 Simulation only tells how circuit reacted to input
excitation that was specified
 Verification tools analyze design and find problems
 Example:
 electrical verification
– transistor sizing for rise/fall time constraints
 timing verification
– find critical path
 functional (formal) verification
– compare circuit behavior against designer‘s specification
– proof that the two are ―equivalent‖, i.e. proof that the
circuit will work
– e.g. prove that two state machines are equivalent
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Copyright 2003  Mani Srivastava
Transistor Sizing
 Once transistor-level critical path has been
identified, transistors can be sized to optimize
delay.
 Transistor sizing is cast as optimization problem
to meet performance goal while minimizing total
active area.
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Copyright 2003  Mani Srivastava
Economics of Implementation
 Decision depends on
 Non-recurring engineering cost
– engineering design cost (personnel, support etc.)
– prototype manufacturing cost
 Production cost (Recurring cost)
– wafer cost, processing cost
– die per wafer
– die yield per wafer, packaging yield, final test yield
 Fixed costs
– data sheets, cost of sales
 Important to estimate design time and design cost
 guide to select the design method
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Copyright 2003  Mani Srivastava
Choosing a Design Style
Custom Cell-based Prediffused Prewired
Density Very High High High Medium-Low
Performance Very High High High Medium-Low
Flexibility Very High High Medium Low
Design Time Very long Short Short Very Short
Manufacturing Time Medium Medium Short Very Short
Cost – low volume Very High High High Low
Cost – high volume Low Low Low High
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Copyright 2003  Mani Srivastava
Custom Circuit Design
 When performance & design density important
 High cost and long time-to-market
 justified only if
– high volumes
– design will be reused (e.g. library cell)
– cost no concern
 due to CAD tools, custom design is minimal

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Copyright 2003  Mani Srivastava
Tools for Custom Design
 Layout editor (e.g. Virtuoso)
 Symbolic layout
 relative positioning followed by compactor
 Design rule checking
 technology file, hierarchical DRC
 Circuit extraction
 schematic from layout
 transistors, caps, resistances, inductances
 Netlist comparison and netlist isomorphism
 Back annotation from layout to schematic
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Copyright 2003  Mani Srivastava
Layout Synthesis
 Two critical phases of layout design:
 placement of components on the chip;
 routing of wires between components.
 Placement and routing interact, but separating layout
design into phases helps us understand the problem and
find good solutions.
 Quality metrics for layout:
 area
 delay
 Area and delay deterined in part by wiring.
 How do we judge a placement without wiring? Estimate
wire length without actually performing routing.
Modern VLSI Design 3e: Chapter 10, Copyright © 1998, 2002 Prentice Hall
PTR