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An introduction to finite state machines

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**Example 1. A surgeon activates the laser by pressing the button b.
**

•Assume the laser should stay ON for 30 ns.

•Assuming a clock with time period of 10 ns, so 30 ns means 3 clock cycles

•Assume b is synchronized with the clock and stays high for only 1 clock

cycle

Design a controller that turns on the laser for exactly 30 ns once b =1 is

detected and holds x high for exactly 3 clock cycles

State diagram for one cycle on, one cycle off for x

State diagram for x

• x = 0 for one cycle and x = 1 for next 3 cycles

• To extend the behavior we can introduce input conditions on the transitions

• For example, for a transition from OFF to ON introduce a new condition along

with clock as b = 1.

• Add a transition from OFF back to OFF with the condition of a rising clock and

b=0

State Diagram Timing diagram

FSM continued

• FSM is a mathematical formalism consisting of several things

– A set of states (our example had 4 states; { On1, On2, On3, Off}

– A set of inputs, and a set of outputs inputs: {b} and output {x}

– An initial state namely, a state to start in when we power up the system

– AN FSM has only one initial state, For our example, it is OFF

– A description of the next state to go to based on the current state and

the values of the inputs. We used directed edges with associated input

conditions to tell us the next state. The edges are named as transitions

– A description of what output values to generate in each state. Our

example assigns a value to x in every state. Assigning an output in an

FSM is called as action

– We used graphical representation of an FSM known as state diagram for

our example.

Example 2. Code detector

Problem statement : doors at hospitals or airports require a person to press a

particular sequence of buttons to unlock the door

• Assume there are three buttons colored RED, GREEN and BLUE

• Fourth button for starting the code (start)

• Pressing the start button, followed by the sequence red, blue, green, red -

unlocks the door

• Any other sequence does not unlock the door

• An extra output from the buttons component a = 1 whenever any button is

pressed

Code detector architecture

Code detector FSM

•FSM begins with a Wait state

•As long as the start button is not pressed, FSM stays in Wait state, When start button is

pressed s =1, it transits to the next state START

• In this state the FSM is ready to detect the sequence RED, BLUE, GREEN, RED

• If no button is pressed a= 0, FSM stays in start

•If button is pressed AND the button is RED (a =1, andr= 1), FSM transits to state RED1

•If button is pressed AND the button is not RED ( a= 1,and r=0), FSM returns to wait state

•FSM stays in RED1 as long as no button is pressed. If a button is pressed and the button is

BLUE, FSM transits to ( a=1, and b=1) then FSM transits to the BLUE state,

•If button is pressed and it is not BLUE, FSM returns to the Wait state

• Likewise FSM stays in Blue as long as no button is pressed and goes to a state GREEN

when a = 1, and g=1

•If FSM makes it RED2 that means user has pressed the correct sequence of buttons, Red2

sets u=1, which unlocks the door

Behavior

Example. Draw a state diagram for an FSM with no inputs and three

outputs, x, y and z. xyz should always follow the following

sequence: 000, 001, 010, 100, repeat. The output should change

only on a rising clock edge. Make 000 the initial state

Example:

A wrist watch display can show one of the four items: the time, the alarm, the stopwatch, or the

date, controlled by two signals S1 and S0 (00 displays the time, 01 displays the alarm, 10 displays

the stop watch and 11 displays the date.

Assume S1S0 control an n bit wide MUX that passes through the appropriate register.

Pressing a button B (which sets B=1) sequences the display to the next item ( f the present display is

time, the next item is alarm)

Create a state diagram for an FSM describing this sequence behavior, having an input bit B, and two

output bits S1 and S0. Be sure to only sequence forward by one item each time the button is

pressed, regardless of how long the button is pressed. Make displaying the time as the initial

state

Example: For FSMs with the following number of states, indicate the smallest

possible number of bits for a state register representing those states

a) 4,

b) 8,

c) 9,

d) 23,

e) 900

Solution a) 2 bits

b) 3 bits

c) 4 bits

d) 5 bits

e) 10 bits

Example: How many possible states can be represented by a 16 bit register?

Solution: 2

16

= 65,536 states

Example: If an FSM has N states, what is the maximum number of possible transitions

that could exist in the FSM ( assuming there are a large number of inputs, meaning the

number of transitions are not limited by the number of inputs

Solution: Maximum number of transitions = N

2

Example: Draw a state diagram for an FSM that has an input X and an output Y.

Whenever X changes from 0 to 1, Y should become 1 for two clock cycles and then

return to 0 - even if X is still 1. Assume that rising edge of the clock is ANDed with every

FSM transition condition.

Solution:

Example: Using D flip flops, create a circuit with an input X and an output Y such

that Y always equals X delayed by 2 clock cycles. Draw Waveforms.

Example: Consider three 4 bit registers connected together as shown in figure below.

Assume the initial values in the registers are unknown. Trace the behavior of the

registers by completing the timing diagram

Solution:

Finite state machines

Eliminating redundant states

a) Original FSM

b) Equivalent FSM with fewer states

c) FSMs are indistinguishable and provide same output behavior for any input

sequence

State reduction

• Note: S2 and S3 appear to be same as S0 and S1

• Regardless of whether we start in S0 or S2, outputs will be

identical

• If we start in S0 and input sequence for four clock cycles is

1,1,0,0 (these are x values)

• The state sequence will be S0, S1, S1, S2, S2 so the output

sequence will be 0,1,1,0,0

• If we start in S2, the same input sequence will result in a state

sequence of S2, S3, S3, S0,S0, so the output sequence will

again be 0, 1, 1, 0, 0

• The FSM of a) and b) have exactly same behavior

•For a large FSM, visual inspection cannot guarantee that we can

remove all redundant states

•A more systematic approach is needed

•Two states are equivalent if

• They assign same value to the output AND

•For all possible sequences of inputs, FSM outputs will be

same starting from either state

Implication table

Step 1. Look at every table cell and mark the cell with a large X if states for

that cell have different outputs.

Refer to such cells as being Marked.

•First state pair ( S1, S0) is not equivalent because S0 outputs Y =0, while S1

outputs Y =1

•Look for state pair (S2, S0) and (S2, S1)

• Step 2. Write the next state pairs for each remaining unmarked cell

• There are two unmarked cells

• (S2, S0) when X= 1, state S2’s next state is S3 while S0’s next state is S1

(looking at the FSM

• So write (S3, S1) as the next state in the same cell

• This means that for state S2, S0 to be equivalent, S3 and S1 must be

equivalent

• Step 3. Mark as non equivalent any unmarked cells whose next state pairs are

already marked as nonequivalent

– Looking at cell (S2, S0), the next state pair (S3, S1) is not marked

– Nor is the next state pair (S2,S0) which happens to be current cell

– So we cannot mark this cell

– Similarly we cannot mark (S3, S1) for which next state pair (S0, S2)

– We made a pass through Step3 without any changes

• Step 4. Declare the unmarked state pairs as equivalent,

– So S2 and s0 are equivalent

– S3, and S1 are equivalent

– Finalize the step 4 of the algorithm, combine the equivalent states in the

FSM

Algorithm for state reduction

Step Description

Mark State pairs having different outputs

as non equivalent

State having different outputs

cannot be equivalent

For each unmarked state pair, Write the

next state pairs for the same input values

For each unmarked state pair, mark state

pairs having nonequivalent next state

pairs as non equivalent.

Repeat this step until no change occurs or

until all states are marked

State with nonequivalent next

states for the same input values

cannot be equivalent.

Each time through this step is

called a PASS

Merge remaining state pairs Remaining state pairs must be

equivalent

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