You are on page 1of 39

N.

Senthil Kumar,
M. Saravanan &
S. Jeevananthan

OVERVIEW OF INTEL 8096
MICROCONTROLLERS
Oxford University Press 2013
Introduction
Microprocessor or CPU contains an ALU, a program
counter, a stack pointer, some working registers, a
clock timing Circuit and interrupt circuit.
To make a complete microcomputer, one must add
memory usually ROM and RAM, memory decoder, an
oscillator and a number of Input / Output (I/O) devices
such as parallel and serial data ports.
Like the microprocessor, a micro controller is a general-
purpose device, but is meant to read data, perform
limited calculation on that data and control the
environment based on those calculations.


Oxford University Press 2013
Comparison between Intels
8-bit and 16-bit processors


Oxford University Press 2013
Details
Z80 8051
(8 Bit)
8096
(16 Bit)
Total Pins
40 40 68
Address Pins
16 16 16
Data Pins
8 8 16
8 Bit registers
20 34 232
16 bit registers
4 2 ---
Internal ROM
0 4k 8k
Internal RAM
0 128 232
Oxford University Press 2013
Comparison between Intels
8-bit and 16-bit processors
Details
Z80
8051
(8 Bit)
8096
(16 Bit)
External Memory
64k 120k 64k
Flags 6 4 7
Timers 0 2 2
Parallel Ports 0 4 5
Serial Port 0 1 2
Features of INTEL 8096 Micro
Controller
Intel has a series of 16-bit microcontrollers under the
name 8X9X series.
Intel 8096 is the basic chip in the 8X9X series of
microcontrollers.
The other microcontrollers in this series are 8094,
8396, 8394, 8097, 8095, 8397, 8395 etc.
All these devices come with the part number as
8X9XBH or 8X9XJF.


Oxford University Press 2013
Oxford University Press 2013
Features of INTEL 8x9x Micro
Controller

16-bit CPU On chip clock generator
256 bytes RAM Special Function Registers
Parallel ports Analog input channels ADC
High Speed inputs High Speed outputs
2 timers Interrupts
Serial ports Watch dog timer


Oxford University Press 2013
Comparison between Intels
8X9X series microcontrollers
Details 8096 8396 8097 8397 8095 8395
Total Pins
68 68 68 68 48 48
Internal ROM
0 8K 0 8K 0 8K
Internal RAM
256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes
Parallel port
lines
40 (5 ports) 40 (5 ports) 24 24 20 20
Timers

2 2 2 2 2 2
Serial port
1 1 1 1 1 1
Oxford University Press 2013
Functional Block Diagram
Oxford University Press 2013
CPU Section
The central processing Unit (CPU) fetches instructions
from the memory and performs specified tasks.
It stores results in the memory and send results to the
output device, according to the instruction given in the
program.
CPU controls and communicates with memory and input
/ Output devices.
The Intel 8096 is inherently a 16 bit microcontroller in
that the data path for operands is 16 bits wide i.e. when
data is transferred between RAM or ROM and the CPU, it
is transferred 16 bits per internal memory cycle.


Oxford University Press 2013
The major components of the 16 bit CPU on the 8096 are
register file and RALU.
The major components of the 16 bit CPU on the 8096 are
register file and RALU.
The RALU (Register / Arithmetic logic Unit) does not use
an accumulator, it operates directly on the 256 byte
register space made up of the register file and the SFRs.
The CPU of 8096 uses a 16 bit ALU, which operates on a
256-byte register file instead of an accumulator.
The CPU of 8096 has Register Arithmetic Logic Unit
(RALU).


CPU Section
Oxford University Press 2013
RALU performs arithmetic and Logical operation using set
of 232 register arrays.
The register file or register array is in the form of RAM.
It is used to store data temporarily during execution of
program.
The register file contains 232 bytes of RAM, which can be
accessed as bytes, words or double words.
The first word in the register file is reserved for use as the
stack pointer, so it cannot be used for data when stack
manipulations are taking place.


CPU Section
Oxford University Press 2013
In the lower 24 bytes of the register file are the register
mapped I/O control locations, also called special function
registers or SFRs.
These registers are used to control the on chip I/O
features.
The remaining 232 bytes are general purpose RAM, the
upper 16 of which can be kept alive using a low current
power down mode.
The control unit provides necessary timing and control
signals to all the operations.
It controls the flow of data between the controller,
memory and peripherals.


CPU Section
Oxford University Press 2013
When the reset signal is activated, all internal operations
are suspended and the program counter is cleared.
After reset, the program execution can begin from the
zero memory address.
The sequencing the execution of instructions is carried
out using the special function register program Counter.
This register is a memory pointer, which always points to
the memory address from which the next instruction is
to be fetched.
When an instruction is being fetched, the PC is
incremented by one to point to the next instruction.


CPU Section
Oxford University Press 2013
The Micro Controller can be interrupted from the normal
execution of instructions and asked to execute some other
instructions of higher priority called interrupt service
routine.
The controller returns to its normal operations after
completing the service routine.
There are many interrupt sources for a micro-controller
system and the programmer can set the priority for each
interrupt.
Clock circuit unit generates the clock signal and
synchronizes all operations within the chip.
It also supplies clock necessary for communication between
CPU and peripheral units.


CPU Section
Oxford University Press 2013
A control unit and two buses connect the register file and RALU
The two buses are the A bus which is 8 bits wide and the D
bus which is 16 bits wide.
D bus transfers data only between the RALU and the register file
or special function registers (SFRs).
A bus is used as the address bus for the above transfers or as a
multiplexed address / data bus connecting to the memory
controller.
Instructions to the RALU are taken from the A- Bus and stored
temporarily in the instruction register.
The control unit decodes the instructions and generates the
correct sequence of signals to have the RALU perform the
desired function.


CPU Buses
Oxford University Press 2013
RALU
Most calculations performed by 8X9X take place in the RALU.
The RALU contains a 17-bit ALU, the program status word
(PSW), the program counter (PC), a loop counter and three
temporary registers.
All the registers are 16 bits or 17 bits (16 + sign extension)
wide. Some of the registers have the ability to perform simple
operations to off load the ALU.
A separate incrementor is used for the PC: however jumps
must be handled through the ALU.
The DELAY is used to convert the 16-bit bus into an 8-bit bus.
This is required as all addresses and instruction are carried on
the 8 bit A bus.


Oxford University Press 2013
RALU Unit block Diagram
Oxford University Press 2013
Temporary register
Two of the temporary registers have their own shift logic.
These registers are used for the operations, which require logical
shifts including normalize, multiply and divide.
The lower word register is used only when double word quantities
are being shifted, the upper word register is used whenever a shift
is performed or as a temporary register for many instructions.
The 5-bit loop counter counts repetitive shifts.
A temporary register is used to store the second operand of two
operand instructions.
This includes the multiplier during multiplications and the divisor
during divisions.
To perform subtractions the output of their register can be
complemented before being placed into the B input of the ALU.


Oxford University Press 2013
Register File
Locations 00H through 0FFH contain the register file and special
function registers (SFRs).
No code can be executed from this internal RAM section.
If an attempt to execute instructions from locations 000H through
0FFH is made, the instruction will be fetched from external
memory.
This section of external memory is reserved for use by Intel
development tools.
The RALU can operate on any of the 256 internal register locations.
Locations 00H through 17H are used to access the SFRs. Locations
18H and 19H contains the stack pointer.
These are not SFRs and may be used as standard RAM if stack
operations are not being performed.
The stack pointer must be initialized by the user program and can
point any where in the 64K memory space.



Oxford University Press 2013
Program Status Word (PSW)
The program status word (PSW) is a collection of Boolean flags, which
contain information concerning the state of users program.
The high byte of the PSW contains status flags and the low byte contains
an interrupt mask register.
The PSW can be saved in the system stack with a single operation (PUSHF)
and restored in a link manner (POPF).

Oxford University Press 2013
Format of PSW of 8096 and
the bit definitons
Oxford University Press 2013
Memory Controller
The RALU talks to the memory through the memory
controller, which is connected to the RALU by the A
bus, and several control lines.
Since the A bus is 8 bit wide, the memory controller
uses a slave program counter to avoid having to
always get the instruction location from the RALU.
In addition to holding a slave PC, the memory
controller contains a 4-byte queue to help speed
execution.


Oxford University Press 2013
Internal Timing
The 8x9x requires an input clock frequency of
between 6 MHz and 12 MHz to function.
This frequency can be applied directly to XTAL-1.
Alternatively, since XTAL1 and XTAL2 are inputs and
outputs of the inverter, it is also possible to use a
crystal to generate the clock.


Oxford University Press 2013
I/O Section
The Micro controller I/O section consists of the
following peripherals on chip
1) ADC interface
2) Pulse Width Modulator
3) Parallel I/O lines
4) High-speed I/O lines
5) Full duplex serial port


Oxford University Press 2013
I/O Section
The analog to digital converter (ADC) has 8 multiplexed inputs
and 10 bit resolution and use successive approximation
technique for the conversion.
The addition of A/D conversion capability means that large
number of transducers for temperature, pressure strain,
position etc. can be used directly with the micro controller.
Any transducer, which generates an output voltage
proportional to derived physical parameters, can be
interfaced with the micro controller.
The conversion of an analog voltage to digital number is
implemented in 8096 with the Successive approximation
technique.

Oxford University Press 2013
I/O Section
The Pulse width modulation output (PWM) can be used as a
Digital to Analog Converter, a motor driver analog circuit or for
many other purposes.
The Intel 8096 includes a pulse width modulator as one of its on
chip resources.
Once it has been setup, it requires no further CPU intervention
to continue generating a wave form with a period of 64 micro
seconds and a duty cycle of any value between 0 and 255/256,
depending upon the 8 bit number written to a PWM register.
Because of this, it provides a reasonable way to carry out a D/A
conversion if all we need is a waveform with dc components,
which is proportional to a digital quantity.
Oxford University Press 2013
PWM Output Driver Circuit
and Output Waveform
Oxford University Press 2013
I/O Section
Pulse width modulation is to achieve width modulated pulses
and thereby to generate variable average dc output as shown
in figure
A watchdog timer is an internal timer, which can be used to
reset the system if the software fails to operate properly i.e. it
resets 8096 if a mal function occurs.
The high speed I/O section includes a 16-bit timer, a 16 bit
counter, a 4-bit programmable edge detector, 4 software
timers, and a 6 output programmable event generators.
High speed input unit provides automatic recording of events.
High output unit provides automatic triggering of events and
real time interrupts.
Oxford University Press 2013
I/O Section
The serial port has several modes and its own baud rate
generator. Serial port provides synchronous or Asynchronous
link.
Input Output interactions of a micro controller some times
require hand shaking.
8096 includes programmable timer facilities, which can be
used to cause output events to occur at precise times, even
while the CPU is doing something else.
They can also be used to measure the time of occurrence of
input events again even the CPU is doing something else.
The 8096 has two time bases, timer1 and timer2. Timer1 is a
16 bit free running timer, which is incremented every 8 state
times.
Oxford University Press 2013
Memory Structure of 8096
The 8096 has internal memory with a provision to have
external memory.
The memory in the 8096 system is divided into two types
namely, the data memory and program memory.
In general, the data memory is Random access or read-write
memory.
The program memory is read only memory.
With 16 bit address lines, 8096 can access a maximum of
64Kbytes of memory.
RAM is user memory and is used to store data.
This information stored in this memory can be easily read
and altered.
Oxford University Press 2013
Memory Map
Oxford University Press 2013
Memory Structure of 8096
The addressable memory space on an 8X9X consists of 64K
bytes, most of which is available to the user for program or
data memory.
There are several registers labeled Reserved.
These registers are reserved for future expansion and test
purposes.
Operations should not be performed with these registers as
reads from them and writes to them may produce unexpected
results.
The locations 0000H through 00FFH, 0100H through 01FFH and
1FFEH through 2080H are for reserved purposes.

Oxford University Press 2013
All other locations can be used for either program or data
storage or for memory mapped peripherals.
All the reserved locations except 2019H must be filled with Hex
value of 0FFH to insure compatibility with future devices.
Locations 2019H must be filled with 20H.
Locations 1FFEH and 1FFFH are reserved for port3 and 4
respectively.
This is to allow easy construction of these ports if external
memory is used in the system.
If port 3 and port 4 are not going to be reconstructed, these
locations can be treated as any other external memory
locations.

Memory Structure of 8096
Oxford University Press 2013
The 9-interrupt vectors are stored in the locations
2000H through 2011H.
Locations 2012H through 2017H are reserved for
future use.
Location 2018H is the chip configuration byte which
gives configuration information.
Locations 2020H through 202FH are the security key
used with the ROM lock feature.
All the unspecified addresses in locations 2000H
through 207FH, including those marked reserved
should be considered reserved for use by Intel.

Memory Structure of 8096
Oxford University Press 2013


Special Function Registers (SFRs)
There are several restrictions on using special function
registers, they are as follows:
Neither the source nor destination addresses of the
multiply and divide instructions can be writable special
function register.
These registers may not be used as base or index registers
for indirect or indexed instructions.
These registers can only be accessed as bytes unless
otherwise specified. Some of these registers can only be
accessed as words and not as bytes.

List of Special Function Registers
Oxford University Press 2013
Oxford University Press 2013
List of Special Function Registers
Power Down Mode of CPU
Oxford University Press 2013
The upper 16 RAM locations (0F0H through 0FFH)
receive their power from the Vpd pin.
If it is desired to keep the memory in these locations
alive during a power down situation, one need only
keep voltage on the Vpd pin.
The current required to keep the RAM alive is
approximately 1 mA.
Both Vcc & Vpd must have power applied for normal
operation.
If Vpd is not applied the power down RAM will not
function properly even if Vcc is applied.
To place the 8096 into a power down mode, the RESET
pin is pulled low.

You might also like