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Lecture Notes

Diodes for Power Electronic Applications

OUTLINE

• PN junction power diode construction


• Breakdown voltage considerations
• On-state losses
• Switching characteristics
• Schottky diodes
• Modeling diode behavior with PSPICE

Copyright © by John Wiley & Sons 2003 Diodes - 1


Basic Structure of Power Semiconductor Diodes
Anode
i
10
P+ 19 -3 microns
N = 10 cm
A
breakdown
v 14 -3 voltage
N- epi N = 10 cm
D dependent

19 -3
N+ substrate N = 10 cm 250
D
microns

Cathode
anode i
1
i
R on
BVBD
v v
≈ 1 V v

cathode

Copyright © by John Wiley & Sons 2003 Diodes - 2


Breakdown Voltage Estimate - Step Junction
Φ
¥ N on-punch-through diode. Drift
W(V)
region length W d > W (BV BD ) =
length of space charge region at
breakdow n. x
Φ
χ
¥ W (V ) = W o 1+V /Φχ
Φχ + ς

2 εΦχ( Να+ Νδ )
∞ Ωο =
θ ΝαΝδ 4ÊΦ χ
¥ (Em ax )2 = (EBD )2 = Βς Β∆
Ω ο2
2Φ χ
¥ Em ax = 1 ⊇+ ⊇ς / Φ χ
Ωο
∞ Σο λϖε φο ρ Ω ( Βς Β∆ ) ανδ Βς Β∆
∞ Πο ω ε ρ δ ιο δ ε ατ ρε ϖε ρσε β ρε ακ δ ο ω ν:
Να >> Νδ ; Ε = ΕΒ∆ ; ς = Βς Β∆ >> Φ χ το ο β ταιν ( π υτ ιν Σι ϖαλυε σ)
ε⊇ΕΒ∆ 2 1 .3 ξ 1 0 1 7
Ω ο 2 ⊇Βς Β∆ 2 εΦ χ
2 2 = Βς Β∆ = = ; [ς ]
∞ Ω ( Βς Β∆ ) = Φχ ; Ω ο 2 ⊇θ ⊇Νδ Νδ
θ ⊇Νδ
2 ⊇Βς Β∆
Ω ( Βς Β∆ ) = = 1 0 −5 Βς Β∆ ; [∝µ ]
ΕΒ∆
¥ Conclusions
1.Large BV BD (10 3 V ) requires N d < 10 15 cm -3

2.Large BV BD (10 3 V ) requires N - drift region > 100 µ m

Copyright © by John Wiley & Sons 2003 Diodes - 3


Breakdown Voltage - Punch-Through Step Junction
¥ Punch-through step junction - W (BV BD ) > W d
¥ A t breakdow n:

- V + ¥ V 1 + V 2 = BV BD
+ +
P N- N ¥ E1 + E2 = EBD

W qN dW d2
d
¥ BV BD = EBD W d -
Electric 2ε
E + E2 field
1
V
1 ε( ΕΒ∆) 2
E
2 ∞ Ιφ Νδ < < ( ρε θ υιρε δ
V2 2 θ ( Βς Β∆ )
x ϖαλυε οφ Νδ φορ νον−πυνχη−τηρυ
δ ιοδ ε ) , τηε ν
qN dW d θ Νδ Ω δ 2
¥ E1 = ;ς1 = ∞ Βς Β∆ ⊕ ΕΒ∆ Ω δ ανδ
ε 2ε
∞ Ω δ ( Πυνχη−τηρυ)
∞ ς 2 = Ε2 Ω δ ⊕ 0 .5 Ω δ ( νον−πυνχη−τηρυ)

Copyright © by John Wiley & Sons 2003 Diodes - 4


Effect of Space Charge Layer Curvature
diffusing incident acceptor impurities
acceptor
impurities SiO2
¥ If radius of curvature is comparable
to depletion layer thickness, electric
field becomes spatially nonuniform.
+
P
R
depletion ¥ Spatially nonuniform electric field
layer N- reduces breakdown voltage.
+
N
¥ R > 6 W(BVBD) in order to limit
breakdown voltage reduction to 10%
¥ Impurities diffuse as fast laterally as vertically or less.

¥ Not feasible to keep R large if


¥ Curvature develops in junction boundary and in BVBD is to be large ( > 1000 V).
depletion layer.

Copyright © by John Wiley & Sons 2003 Diodes - 5


Control of Space Charge Layer Boundary Contour
field plates

• Electrically isolated conductors


(field plates) act as equipotential
P+ surfaces.
depletion layer • Correct placement can force
boundary depletion layer boundary to have
-
N larger radius of curvature and t;hus
minimize field crowding.

SiO 2 • Electrically isolated p-regions


P P
(guard rings)has depletion regions
P+ which interact with depletion region
guard ring of main pn junction.
depletion
layer
boundary N
- • Correct placement of guard rings
can result in composite depletion
N+
region boundary having large radius
aluminum of curvature and thus minimize field
contact
crowding.
Copyright © by John Wiley & Sons 2003 Diodes - 6
Surface Contouring to Minimize Field Crowding
depletion layer
boundary

N
+ N+
SiO
2
N-

N-

P+ P+
bonding pad bonding pad
high field
region

• Large area diodes have depletion • Proper contouring of surface can


layers that contact Si surface. mimimize depletion layer curvature and
• Difference in dielectric constant of Si thus field crowding.
and air causes field crowding at surface. • Use of a passivation layer like SiO2 can
• Electric fields fringing out into air also help minimize field crowding and
attract impurities to surface that can also contain fringing fields and thus
lower breakdown voltage. prevent attraction of impurities to
surface.
Copyright © by John Wiley & Sons 2003 Diodes - 7
Conductivity Modulation of Drift Region
• Forward bias injects holes into drift
region from P+ layer. Electrons
x attracted into drift region from N+
+ + -
layer. So-called double injection.
P N - N+

W • If Wd ≤ high level diffusion length La ,


d
carrier distributions quite flat with p(x)
p(x) = n(x) log scale ≈ n(x) ≈ na.
16
= n a= 10

• For na >> drift region doping Nd, the


p (x)
n p(x) 14 n resistance of the drift region will be
n no= 10
p quite small. So-called conductivity
no modulation.
n
po p = 10 6
no
x
• On-state losses greatly reduced below
those estimated on basis of drift region
low-level (Nd) ohmic conductivity.
Copyright © by John Wiley & Sons 2003 Diodes - 8
Drift Region On-State Voltage Estimate

QF θ⊇Α⊇Ω δ ⊇να
¥ IF = = ; Χυρρεντ νεεδεδ
τ τ
το µαινταιν στορεδ χηαργε Θ Φ.
W
d
θ⊇[∝ ν⊇+⊇∝π ]⊇ν α⊇Α⊇ς δ x
∞ ΙΦ = ;
Ωδ
Οηµ∏σ Λαω (ϑ = σΕ)
+ + -
P N - N+
IF
Ωδ2
∞ ςδ= ; Εθυατε αβοϖε +V - + V -
⊇[∝ν⊇+⊇∝π ]⊇τ j d
Cross-sectional
τωο εθυατιονσ ανδ σολϖε φορ ς δ
area = A

∞ Χονχλυσιον: λονγ λιφετιµε τ µινιµιζεσ ς δ .

Copyright © by John Wiley & Sons 2003 Diodes - 9


Diode On-State Voltage at Large Forward Currents

µo
¥ µn + µp = ; nb Å 10 17 cm -3 .
na
1Ê+Ê
nb
¥ M obility reduction due to increased
carrier-carrier scattering at large na.

qÊnaÊA ÊV d µo
¥ IF = ; O hm s Law
Wd na
1Ê+Ê IfÊW d
nb
¥ Vd =
w ith density-dependent m obility. qʵoÊnbÊA

¥ V d = IF Ron
¥ Invert O hm Õs Law equation to find V d as
function IF assum ing na >> nb.
¥ V = V j+ V d
Copyright © by John Wiley & Sons 2003 Diodes - 10
Diode Switching Waveforms in Power Circuits
Q rr = I t /2
rr rr

di / dt d i / dt
F I F R 0.25 I rr

I
rr

t t t
3 4 5 diF diR
¥ and determined
dt dt
V on t
V
FP
rr by external circuit.

t ¥ Inductances or power
t V
V
R semiconductor devices.
2 rr
t
t 5
1 S =
t
4

Copyright © by John Wiley & Sons 2003 Diodes - 11


Diode Internal Behavior During Turn-on
t interval
1
- +
+ - + ε⊇Α δι Φ
P - + N - N+
C sc(V) = ς ΦΠ ⊕ Ι Φ Ρ δ + Λ
i (t) - + ⊇Ω(ς) δτ
F
Ωδ
Ρδ = Λ = στραψ ορ
θ⊇µ ν ⊇Νδ ⊇Α ωιρινγ ινδυχτανχε
C sc Rd L

t interval
2
- +
P+ - + N - N+
i (t) - +
F
V j Å 1.0 V

time
• Injection of excess
time carriers into drift
time
region greatly
reduces Rd.
x

Copyright © by John Wiley & Sons 2003 Diodes - 12


Diode Internal Behavior During Turn-off
t - t interval
3 4
i (t)
R + - + - N+
P - N
- +
+
V j Å 1.0 V ¥ R d increases as excess

Rd
carriers are rem oved via
C L
sc recom bination and carrier
sw eep-out (negative current).
time
time time diR
¥ V r = IrrR d + L
dt

ts inte rv al
¥ Insufficient excess carriers rem ain to support Irr,so

P + N - junction becom es reverse-biased and current


decreases to zero.

¥ V oltage drops from V rr to V R as current decreases


to zero.N egative current integrated over its tim e
duration rem oves a total charge Q rr.

Copyright © by John Wiley & Sons 2003 Diodes - 13


Factors Effecting Reverse Recovery Time

diR diR trr ¥ If stored charge rem oved m ostly


¥ Irr = t = ; Defined on by sw eep-out Q rr Å Q F Å IF τ
dt 4 dt(SÊ+Ê1)
sw itching w aveform diagram

∞ Υσινγ τηισ ιν ε θ σ. φορ Ιρρ ανδ τρρ


ανδ ασσυµ ινγ Σ + 1 ⊕ 1 γ ιϖε σ
IrrÊ trr diR trr2
¥ Q rr = = ; Defined
2 dt 2(SÊ+Ê1)
2 ⊇ΙΦ⊇τ
on w aveform diagram τρρ = ανδ
δ ιΡ
δτ
¥ Inverting Q rr equation to solve for trr yields
diR δ ιΡ
2Q rr(S+1) 2Q rr Ιρρ = 2 ⊇ΙΦ⊇τ⊇
dt δτ
trr = and Irr =
diR (SÊ+Ê1)
dt

Copyright © by John Wiley & Sons 2003 Diodes - 14


Carrier Lifetime-Breakdown Voltage Tradeoffs

¥ Low on-state losses require Conclusions


κΤ
L = DÊ τ = ⊇τ 1. Higher breakdow n voltages
θ⊇[∝ ν ⊇+⊇∝π ]
require larger lifetim es if low
Λ = Ω δ ≥ Ω(ς) = 10 −5 Βς
Β∆ on-state losses are to be
m aintained.

∞ Σολϖινγ φορ τηε λιφετιµε ψιελδσ 2. High breakdow n voltage


Ω δ2 devices slow er than low
τ= = 4ξ10 −12 (Βς Β∆ ) 2 breakdow n voltage
(κΤ/θ)⊇[∝ ν +∝π ]
devices.

3. Turn-off tim es shortened


∞ Συβστιτυτινγ φορ τ ιν Ιρρανδ τ ρρεθυατιονσ γιϖεσ
diR
ΙΦ by large but Irr is
−6 Βς dt
∞ τρρ= 2.8ξ10 Β∆ (δι Ρ /δτ) increased.
διΡ
∞ Ιρρ= 2.8ξ10 −6 Βς ΙΦ⊇
Β∆ δτ

Copyright © by John Wiley & Sons 2003 Diodes - 15


Schottky Diodes
anode
aluminum
SiO2 contact -
Characteristics rectifying

¥ V (on) = 0.3 - 0.5 volts.


P P

¥ Breakdow n voltages guard


² 100-200 volts. ring
depletion layer depletion layer
boundary with N boundary
¥ M ajority carrier device - no guard rings without guard
stored charge. rings

¥ Fast sw itching because of lack


of stored charge. N+

aluminum
cathode
contact -
ohmic
Copyright © by John Wiley & Sons 2003 Diodes - 16
Physics of Schottky Diode Operation

¥ Electrons diffuse from Sito A l


because electrons have larger + V -
i(t)
average energy in silicon
Aluminum n-type Si
com pared to alum inum .
Electron Energy
¥ Depletion layer and thus potential
barrier set up.Gives rise to
E
rectifying contact. Si
E
Al
¥ No hole injection into silicon.No
source of holes in alum inum .Thus
- +
diode is a m ajority carrier device. Al - + N-Si
+
¥ Reverse saturation current m uch Depletion layer
Diffusing
larger than in pn junction diode.
electrons
This leads to sm aller V (on) (0.3 -
0.5 volts)

Copyright © by John Wiley & Sons 2003 Diodes - 17


Schottky Diode Breakdown Voltage

¥ Breakdow n voltage lim ited to


100-200 volts.

¥ Narrow depletion region


w idths because of heavier
drift region doping needed for
low on-state losses.

¥ Sm allradius of curvature of
depletion region w here
m etallization ends on surface
of silicon.Guard rings help to
m itigate this problem .

¥ Depletion layer form s right at


silicon surface w here
m axim um field needed for
breakdow n is less because of
im perfections,contam inants.

Copyright © by John Wiley & Sons 2003 Diodes - 18


Schottky Diode Switching Waveforms
¥ Schottky diodes sw itch m uch
faster than pn junction diodes.No Current
m inority carrier storage.
I
F
¥ Forew ard voltage overshoot V FP
t
m uch sm aller in Schottky diodes.
Drift region ohm ic resistance RΩ. V
FP

∞ Ρε ϖε ρσε ρε χοϖε ρψ τιµ ε τρρ µ υχη


V(on)
σµ αλλε ρ ιν Σχηοττκψ δ ιοδ ε σ. Νο
µ ινοριτψ χαρριε ρ στοραγ ε . t
voltage
∞ Ρε ϖε ρσε ρε χοϖε ρψ χυρρε ντ Ιρρ
χοµ παραβλε το πν ϕυνχτιον δ ιοδ ε σ. C(Schottky) Å 5 C(PN)
σπαχε χηαργ ε χαπαχιτανχε ιν
Σχηοττκψ δ ιοδ ε λαργ ε ρ τηαν ιν πν
R (Sch.) <<
ΩR (pn)
ϕυνχτιον δ ιοδ ε βε χασυε οφ Ω
ναρροωε ρ δ ε πλε τιον λαψε ρ ωιδ τησ
ρε συλτινγ φροµ ηε αϖιε ρ δ οπινγ σ.

Copyright © by John Wiley & Sons 2003 Diodes - 19


Ohmic Contacts

¥ Electrons diffuse from A linto p-


type Sibecasue electrons in A l
have higher average energy.

¥ Electrons in p-type Siform an Electron Energy


accum ulation layer of greatly
E
enhanced conductivity. Al

E
¥ Contact potentialand rectifying Si
junction com pletely m asked by Accumulation layer
i(t)
enhanced conductivity.So-called P-Si or
-
Al
ohm ic contact. - N + -Si

¥ In N + Sidepletion layer is very Diffusing


narrow and electric fields approach electrons
im pact ionization values.Sm all
voltages m ove electrons across
barrier easily becasue quantum
m echanicaltunneling occurs.

Copyright © by John Wiley & Sons 2003 Diodes - 20


PN Vs Schottkys at Large BVBD
¥ M inority carrier drift region ¥ Desired breakdow n voltage
relationships 1.3x10 17
qÊ[µnÊ+ʵp]ÊnaÊA ÊV d requires N d = and
¥ IF Å
BV BD
Wd
W d ³ 10 -5 BV BD

¥ M axim um practicalvalue of na =10 17


¥ Large BV BD (1000 V ) requires N d
cm -3 and corresponding to
µn + µp = 900 cm 2 /(V -sec)
= 10 14 cm -3 w here µn + µp =
1500 cm 2 /(V -sec)
¥ Desired breakdow n voltage requires
W d ³ 10 -5 BV BD IF Vd
¥ Å 3.1x10 6
IF Vd A [BV BD ]2
= 1.4x10 6
A BV BD
¥ Conclusion:M inority carrier
¥ M ajority carrier drift region devices have low er on-state
relationships
losses at large BV BD .
qÊ[µnÊ+ʵp]ÊN dÊA ÊV d
¥ IF Å
Wd

Copyright © by John Wiley & Sons 2003 Diodes - 21


PSPICE Built-in Diode Model

• Circuit diagram • Components

¥ Cj - nonlinear space-charge capacitance

+ i

diode

¥ Cd - diffusion capacitance. Caused by excess


+

carriers. Based on quasi-static description of


v

j
C
i (v )
stored charge in drift region of diode.
C
dc j
v j
d
diode
-

¥ Current source idc(vj) models the exponential


R
s
I-V characteristic.
-

¥ Rs accounts for parasitic ohmic losses at high


v = v + R i

diode
j
s diode currents.

Copyright © by John Wiley & Sons 2003 Diodes - 22


Stored Charge in Diode Drift Region - Actual
Versus Quasi-static Approximation
x

+ - +
• One dimensional diagram of a
P N N

power diode.

n(x,t) n(x,t)

time

• Quasistatic view of decay of


time
excess carrier distribution
time

during diode turn-off.


n(x,t) = n(x=0,t) f(x)

0 Wd
x

• Redistribution of excess
carriers via diffusion ignored.
time
Equ;ivalent to carriers moving
with inifinte velocity.
time
time

• Actual behavior of stored


charge distribution during
x
turn-off.

Copyright © by John Wiley & Sons 2003 Diodes - 23


Example of Faulty Simulation Using Built-in Pspice Diode Model
L

stray

50 nH

+
D

f
I
o
• Test circuit example - step-down converter.
V 50 A

100 V - • PSPICE diode model parameters - (TT=100ns


Cjo=100pF Rs=.004 Is=20fA)
Sw

Diode

Voltage

0V

-100V

-200V

-300V
• Diode voltage transient
-400V

-500V

0s 100ns 200ns 300ns 400ns 500ns

time

Diode

Current

100A

50A

0A

-50A

-100A
• Diode current transient.
0s 100ns 200ns 300ns 400ns 500ns

time

Copyright © by John Wiley & Sons 2003 Diodes - 24


Improved (lumped-charge) Diode Model

N - region
• More accurately model distributed nature p(x) = n(x)
of excess carrier distribution by dividing
it into several regions, each described by N+
P+ Q
a quasi-static function. Termed the Q1 Θ Q3 region
region 2 4
lumped-charge approach.
x
δ d

diode
• Circuit diagram of improved diode model. Circuit written in
+

D
terms of physical equations of the lumped-charge model.
v Gd
CJ j

Vsense1
-
6
5 7 8

+ -
2

R
s + + +
Re
Ee Em Rm Edm Cdm
Rdm
- - -
3

+
Emo
- 0

+
Vsense2
- • Detailed equations of model given in subcircuit listing.
• Many other even better (but more complicated models available in
9

technical literature..
Copyright © by John Wiley & Sons 2003 Diodes - 25
Details of Lumped-Charge Model
Subcircuit Listing
.Subckt DMODIFY 1 9 Params: Is1=1e-6, Ise=1e-40, Tau=100ns, • Symbolize subcircuit listing into
+Tm=100ns,Rmo=Rs=.001, Vta=.0259, CAP=100p, Gde=.5,
+ Fbcoeff=.5, Phi=1, Irbk=1e20,Vrbk=1e20
SCHEMATICS using SYMBOL
*Node 1= anodeand Node 9 = cathode WIZARD
Dcj 1 2 Dcap ; Included for space charge capacitance and reverse
*breakdown. • Pass numerical values of
.model Dcap D (Is=1e-25 Rs=0 TT=0 Cjo={CAP} M={Gde} parameters Tau, Tm, Rmo,Rs, etc.
+FC={Fbcoeff} Vj={Phi} +IBV={Irbk} BV=Vrbk})
Gd 1 2 Value={(v(5)-v(6))/Tm +Ise*(exp(v(1,2)/Vta)-1)}
by entering values in PART
*Following components model forward and reverse recovery. ATTRIBUTE window (called up
Ee 5 0 VALUE = {Is1*Tau*(exp(V(1,2)/(2*Vta))-1)}; Ee=Qe
Re 5 0 1e6
within SCHEMATICS).
Em 6 0 VALUE = {(V(5)/Tm-i(Vsense1))*Tm*Tau/(Tm+Tau)}
*Em=Qm
• See reference shown below for
Rm 6 0 1e6 more details and parameter
Edm 7 0 VALUE = {v(6)};Edm=Qm extraction procedures.
Vsense1 7 8 dc 0 ; i(vsense1)=dQm/dt
Cdm 8 0 1 • Peter O. Lauritzen and Cliff L. Ma,
Rdm 8 0 1e9 "A Simple Diode Model with
Rs 2 3 4e-3
Emo 3 4 VALUE={2*Vta*Rmo*Tm*i(Vsense2) Forward and Reverse Recovery",
+/(v(6)*Rmo+Vta*Tm)}; Vm IEEE Trans. on Power Electronics,
Vsense2 4 9 dc 0 Vol. 8, No. 4, pp. 342-346, (Oct.,
.ends
1993)
Copyright © by John Wiley & Sons 2003 Diodes - 26
Simulation Results Using Lumped-Charge Diode Model
Diode voltage and current waveforms Simulation Circuit
L
Diode
10V
stray
50 nH
Voltage

0V
0V

Io
.

D
+ V f
-10V d 50 A
410ns 415ns 420ns

- 100 V Sw
-100V

-200V

0s 100ns 200ns 300ns 400ns 500ns

time

Diode

Current

• Note soft reverse


50A
recovery and forward
voltage overshoot.
Qualitatively matches
experimental
0A

measurements.
-50A

0s 100ns 200ns 300ns 400ns 500ns

time

Copyright © by John Wiley & Sons 2003 Diodes - 27