UNIT-VII Advanced Micro Processors

Introduction to 80286 • • • • • • • 80286 16 bit µp 16 Mbytes physical memory Multi-user Multitasking OS User protection Virtual memory management

80286 - Architecture
• The bus unit – BU
– Performs all memory and i/o reads and writes, pre-fetches instruction bytes and controls transfer of data to and from processor extension devices such as the 80287 math coprocessor.

The instruction unit – IU
– IU fully decodes up to three pre-fetched instructions and holds them in a queue, where the execution unit can access them. – Instructions in the pipeline

• •

The execution unit – EU
– Machine Status Word (MSW) register

The address unit – AU
– AU computes the physical addresses that will be sent out to memory or I/O by the BU.
• Real address mode • protected virtual address mode • CS, DS, SS, ES registers

Register organization
– Eight 16-bit GPRs • AX, BX, CX, DX, BP, SP, SI, DI – Four 16-bit segment regs. • DS, CS, SS, ES. – Status and control reg. • Flag reg. – Instruction pointer (IP)

• Signal description
– COD/INTA: This output signal, in combination with M/IO signal and S1 – S0 distinguishes different memory, I/O and INTR cycles. – BUSY and ERROR:
• BUSY=0 ; Processor suspend the execution and wait until it becomes 1 • An active ERROR signal causes the 80286 to perform the processor extension interrupt while executing the WAIT and ESC instruction. • The active ERROR signal indicates to 80286 that the processor extension has committed a mistake and hence it is reactivating the processor extension interrupt.

– CAP: A 0.047µf, 12v capacitor must be connected between this

input pin and ground to filter the output of the internal substrate bias generator. For correct operation of 80286 the capacitor must be charged to its operating voltage.

Flag register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


30 29

28 27







Ac X
20 19




TS Machine status word
O – Overflow Flag D – Direction I – Interrupt Flag T – Trap Flag S – Sign Flag Z – Zero Flag Ac – Auxiliary Carry Flag P – Parity Flag Cy – Carry Flag X – Not used



TS – Task switch EM – Emulate processor extension MP – Monitor processor extension PE – Protection enable NT – Nested task flag IO I/O privilege level PL

Interrupts of 80286
Divide error exception Single step interrupt NMI interrupt Break-point interrupt INTO detected overflow exception BOUND range exceeded exception – Invalid opcode exception Processor extension not available exception Inter reserved, do not use Processor extension error interrupt Inter reserved, do not use User Defined 0 1 2 3 4 5 6 7


8-15 16 (ESC or WAIT) 17-31 32-255

• • • •

Maskable Interrupt INTR Non-maskable Interrupt NMI Single Step Interrupt Interrupt Priorities
1 2 3 4 5 6

Instruction exception Single step NMI Processor extension segment overrun INTR INT instruction

80286 Real Address Mode Operation
• After the 80286 is reset, it starts executing in its real address mode. • MS-DOS systems operates in Real Address Mode • In this mode 80286 can address up to 1MB of physical memory. • Interrupt Vector Table of the 80286 is located in the first 1KB of memory. (from address 00000h to 003FFh ). • The addresses from FFFF0h to FFFFFh are reserved for system initialization. • Functions performed in this mode:
– – – – – It initializes the IP and other registers of 80286 Initializes the peripheral Enables interrupts Sets up descriptor tables Prepares for entering the protected virtual address mode.

Protected Virtual Address Mode Operation (PVAM)
The 80286 is able to address 1Gbyte if virtual memory per task. Swapping Unswapping Program is divides into Segments or pages Segments or pages have been associated with a data structure called as a descriptor. • Descriptor contains • • • • •
– – – – – – – segment base address, segment limit, segment type, privilege level, segment availability in physical memory, descriptor type and segment use by another task.

• Descriptor table.

Descriptors and Their Types
Special types of descriptors which are used to carry out additional functions like – – 1. 2. Transfer of control Task switching Data segment descriptors System segment descriptors – Store system data and execution state of a task for multitasking system. Gate descriptors – The gate descriptors control the access to entry points of the code to be executed. Interrupt descriptors – These are used to store task gates, interrupt gates and trap gates.



Segment descriptor cache registers: 6-Byte format Local and Global descriptor table: LDTs & GDTs are 8K array.

• The 80286 supports a four level hierarchical privilege mechanism to control the access to descriptors to prevent
– unwanted access to any of the code or data segments. – Unintentional interference in the higher privilege level tasks. (level 0 is the most privilege level while level 4 is the least)

• The privilege levels provide protection within a task.

• 1. The 80286 supports three basic mechanisms to provide protection: Restricted use of segments (segment load check): • This is accomplished with the help of read/write privileges. The segment usages are restricted by classifying the corresponding descriptors under LDT and GDT. Restricted Accesses to Segment (operation reference check): • This is accomplished using descriptor usages limitations and the rules of privilege check Privileged Instructions or Operations (privileged instruction check): • These are to be executed or carried out at certain privilege levels determined by current privilege level (CPL) and I/O privilege level (IOPL) as defined by the flag register.



Special Operations
• Processor reset and initialization – The processor is reset by applying a high on RESET input that terminates all execution and internal bus activities till RESET remains high. • Task switch operation – A no. of task allocation strategies like FCFS, STF, Time sharing, etc. – In case of time sharing, the CPU’s time is divided into equal duration slices. – The switch-over operation from one task to another is called as task switch operation. – This operation is carried out using a JMP or CALL to a new segment of the new task. • Pointer testing instructions – The pointer testing instructions of 80286 use the memory management hardware to verify whether the loaded selector value refers to a valid segment without generating any exception.

• Protected mode initialization
– The initialization of protected mode is carried out in real mode by setting the internal registers of 80286 suitably. – To enter into protected mode, 80286 executes LMSW (load MSW) instruction that set PE flag.

• How to enter protected mode?
– The execution of instruction LIDT (load interrupt descriptor table base) prepares the 80286 for protected virtual address mode. – Then the PE flag of MSW is set to enter the PVAM, using the LMSW instruction.

• Halt
– This instruction stops program execution and prevents the CPU from restarting, till it is interrupted or RESET is asserted. – If the CPU is interrupted in the HALT state, the execution starts from the next instruction after HLT.

• The I/O devices are also addressed using even and odd address banks technique, using A0 and BHE. The 80286 bus cycles are of six types
– – – – – – Memory read Memory write I/O read I/O write Interrupt acknowledge Halt.

The 80286 bus at a particular instant may be in either of these four states:
1. 2. 3. 4. Idle state (Ti) Perform command state (Tc) Send status state (Tc) Hold state (TH)

80386 µp
• • • • • • • 32-bit µp 4 GB physical memory 16K - segment size Page size – 4KB 8 debug registers DR0-DR7 80386 has an on-chip address translation 80386DX
– 132 pins, 20MHz, 33MHz

• 80386SX
– 16-bit data bus – 24-bit address bus

Architecture of 80386


Central Processing Unit (CPU)
Execution Unit
1. 2. 8 – General Purpose Registers 8 – Special Purpose Registers

Instruction Unit
1. 2. 3. 16-byte instruction code queue 3-byte instruction decoded queue The barrel shifter increases the speed of all shift and rotate operations


Memory Management Unit (MMU)
Segment Unit
1. 2. 3. 4-GB size of segment Segment and offset for relocability SU provides a 4 level protection mechanism for protection and isolating the system’s code and data. Each segment is further divided into pages 4KB- page size Page Unit works under Segment Unit It converts linear address into physical address

Page Unit
1. 2. 3. 4.


Bus Control Unit (BCU)
Bus control unit had a prioritizer to resolve the priority of the various bus requests.

• BE0# to BE3# :
– 80386 can be viewed as a 4-byte wide memory access mechanism. These lines enable four banks (i.e. 1byte/2byte/3byte/4byte data transfer simultaneously)

• • • • • • • •

W/R : write/read control bit D/C : data/control bit M/IO : LOCK# : ADS# : Address status indicates address bus and bus cycle definition NA# : Next address – allows address pipe lining READY# : BS16# : Bus size 16 – allows the interfacing of 16-bit devices with the 32-bit wide 80386 data bus i.e. two bus cycles = 32 bit data. • HOLD : • HLDA :

• BUSY#: Co-processor is busy and main processor is in waiting state. • ERROR# : Co-processor has encounter an error. • PEREQ : Processor extension request. i.e. CPU fetches a data from co-processor. • INTR : • NMI : • RESET : • N/C : No connections pins are expected to be left open while connecting the 80386 in the circuit.

Register organization

FLAG Register

VM Flag : If this is set, 80386 enters the virtual 8086 mode within the protected mode RF-Resume flag : This is used with the debug register breakpoints, i.e. any debug fault is ignored during the instruction cycle.

Addressing Modes: Eleven addressing modes
Scaled Indexed Mode Based Scaled Indexed Mode. Based Scaled Indexed mode with Displacement

Data Types • • • • • • • • • • • Bit Bit field Bit string Signed byte Unsigned byte Offset Pointer BCD Packed BCD Character Strings

Descriptors tables • LDT • GDT • IDT, etc Control registers • CR0,CR2,CR3
– Load, store instructions are available to access these registers.

1. RAM
1. After reset FFFF FFF0h under the RAM 2. Interrupt Vector table – 0000 003FFh -- 1KB

1. 4-GB --- PA 2. 64-TB --- virtual memory/task

Real Addressing Mode – physical address

Physical Address formation in Protected mode


Virtual 8086 mode

• The Pentium processor has 237 pins, arranged in a pin grid array (PGA) • 64 pins are data pins --- D0-D63 • 8 pins are parity --- DP0-DP7 – Parity errors are indicated by these pins • Address bus (with parity check bit) --- A3-A31 • BE0-BE7: are used to select the eight memory banks to accomplish an 8-byte data transfer

RISC Processors
• RISC: Reduced Instruction Set Computer • CISC :
– – – – complex instructions Increase in processor die size Consumes more power and silicon Needs more cooling arrangement.

– Small, highly optimized set of instructions – Every instruction is executed in a single clock after it is fetched and decoded. – Very fast execution – Less power consumption

• John Cocke of IBM research in New York, who had first originated the RISC concept in 1974. • First time RISC is implemented in IBM 801 system in John project • IBM RISC processors starting with R6000 series were designed based on the concepts of IBM 801. HYBRID ARCHITECTURE
– RISC AND CISC CONVERGENCE – Pentium and Athlon family of processors – SIMD : single Instruction Multiple Data

• The Advantages of RISC
– RISC instructions, being simple, can be hardwired – Processor can work at a high clock frequency and thus yields higher speed. – On-chip MMU, Floating point arithmetic units. – Chip cost is low – More devises can place on chip – Compilers produce more efficient codes in RISC µp – Loading and decoding of instructions in a RISC processor is simple and fast.

Design issues of RISC processor

• Register Windowing • Massive Pipelining • Single cycle instruction execution


Sign up to vote on this title
UsefulNot useful

Master Your Semester with Scribd & The New York Times

Special offer for students: Only $4.99/month.

Master Your Semester with a Special Offer from Scribd & The New York Times

Cancel anytime.