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ALLAH the most Merciful, the most Beneficent”

contents
 Recall.
 Electronic Gates.
 classification for digital logic gates.
 Diode Logic Family .
 Diod –Transistor Logic (DTL)
 Resistor Transistor Logic (RTL)
 Transistor –Transistor Logic (TTL)
 Totem pole Configuration
Analog verses Digital signal
Analog verses Digital signal

Anlog signal Digital signal

Any phisical signal seems to be change in continous Signal Representted only a finit number of discrete
manner like value
Temperature, Pressur, Velocity, ......

Signal which passes through every possible Value Signal which is a series of samples points
between the Limits. Called Analog Value

Anloge ckt design for use with small signal and use in Digital Ckt use with large signals & Considrer Non-
linear fashion like Op-Am linear , I.e Remot ckt for switch On/Off w.r.t
sunlight

Analog sisgnal mostly effected by unwanted electrical Digial signal less effected by unwanted electrical
signal interfarence(Noise)
Basic Component of analog Circuit and Digital Circuit

Analog
Analog Processing i.e Analog
I/P I=V/R O/P
Analog sig Digit
Mem
A/D al si
Conver:
Genration of Digital Signal CPU
O/P(crt)

Digital Signal are composed of two voltage level(TTL Voltage l)


(1)Low (GND) or 0V
(2)High +3 to +5 V
This Digital signal made mannually by using a mechanical switch

5v Debouncing
Latch

2nd way to generate the


digital signal we use
Push button
Digital Signal Processing(DSP)

Equipment use DSP MODEM, DVD palyer, Cellular phones etc


All those thare are similarity to micro computer systems.
Digital signals used in DSP systems are acquired from analog signals using
a process Known as Sampling

Basic Blk dia A/D


Converter DSP D/A Convertyer
Memory

Common calculation perform in DSP is SOP


Yi= ∑ Ai .Bi (i=1 to n)
Electronic Gates
Electronic Gates
The analysis of AND/OR gates is made measurable easier by using
the approximate equivalent for a diode rather then the Ideal because
we can stipulate that the voltage across the Diode must be 0.7V +ve
for silicon Diode (0.3v for GE) to switch to the “On” state.

In general, the best approach is simply to establish a “gut” feeling for


the state of the diodes by noting the direction and the “pressure”
established by the applied potentials. The analysis will the verify or
Negate your initial assumptions[1] .

As the Logic Ckts make use of logic gates which perform logic operations governed by Boolean
algebra. (Symbolic representation)

logic gates are available in Integrated circuits.

]
P67 Electronic device & ckt theory by Robert L. Boylestad& Lois Nashelsky
classification for digital logic gates with
reference to scale/ Size.
Small-scale Integrated Circuit(SSI) It consist over 100 discrete
devices & up till 12 gates.
MSI. Consist 100<component>1001 or 11 <Gates >101,i.e.
4790,74121
LSI
Consist 1000to 10000 component or 100 to 1000 Gates.

VLSI Consist 10000 to 100000 component or 1000 to 10000


Gates ie 8085,80386 μ processor chip.

Ultra LSI I.e. Pentium-III chip consist 106 components


classification for digital logic gates with
reference to Technology
1. TTL Family
2. C MOS Logic family
3. ECL logic family
The emitter couple logic used in super high speed computers. And TTL is used
in digital ckts belonging to SSI, MSI, and LSI categories.
CMOS ckts are being used in all modern low power digital ckts and high-density
component chips ie P-IV.

obsolete or almost obsolete Logic Families


1. Diode Logic
2. Resistor-Transistor logic
3. Diode-Transistor Logic
4. Integrated-Injection logic
5. N-type Metal-Oxide semiconductor(NMOS) Logic

Hve replace with TTL & CMOS family


Curently not Active
Diode Logic Family

•A & B are at logic 0 level, The Input terminals are shorted to ground,
and current flow +v through D1 and D2 to ground.
•As The Diod conduct, they become short circuits across the output
terminal and ground,

•When apply positive voltage +v across both A & B inputs, the Diod
become reverse biased and hence they stop conducting. There will be
no current through the load resistance RL and Hence Vo=+V

Draw back:- The DL family has major drawback that inversion is not
possible unless we connect transistor switch to Diod to perform
inversion & that introduce DTL family

K A
As the Vak=forward Va should be more +ve or Less _ve then Vk
Diod –Transistor Logic (DTL)
The D1, D2 perform AND Operation and T
invert the the AND function. With DL AND
gate add a BJT to incorporate inversion so
that NAND operation is obtained.

For further insuring the


proper circuit D3 Diod
is also added, which
ensures more speedy
switching operation
Diod –Transistor Logic (DTL)

When D1 & D2 are OFF the Diod gets forward biased and
drive the transistor into ON state.
And Z=VCES =0.2`

Assume that 0.2=logic 0 , therefore when A=0 & B=0 or


one or both of Diodes conduct, which make the diod D3
reverse Biased, will drive T into OFF state and hence into
Logic 1. So this give NAND function. To increase Noise
immunity, May add more diod series with D3 which
produces voltage swings in case of low voltage level.
Resistor- Transistor Logic (RTL)

About every five years , a new BJT ligic subfamily


introduced starting with RTL in 1962. Subsequent models
(DTL,TTL, STTL,….) are improvements of previous
subfamilies with the same general TTL super-circuitry.
RTL is the first logic family to become commercially
available
Resistor- Transistor Logic (RTL)
Type of RTL GATE
RTL INVERTOR
RTL NOR
RTL NAND
RTL BUFFERS
In addition low medium and high power version of various RTL gates were
obtained by varying the magnitude of resisters. Large resistors are used for low
power applications and small resistors for high power applications.
RTL PARAMETERS
FANOUT
NOISE MARGIN
PROPAGATION DELAY
POWER DESSIPATION
Resistor- Transistor Logic (RTL)
VCC 5V Consider Basic Transistor ckt, apply one of two voltages
(0 or 1 logic) The exact voltage used as +v depends on
R2 the circuit design parameters; In RTL IC the usual
640ohm voltage is +3.6v. So, Assume an ordinary NPN
R1
transistor here, with a reasonable dc current gain, an
O/P emitter-base forward voltage of 0.65v, and a collector
Q1
470ohm
emitter saturation voltage no higher than 0.3 v.
Case:- when Vi=0v(>0.5v) There is no forward bias to
Emitter-base junction flows through the collector resistor,
& output voltage is +v. Result ‘ll be 1 output

Case:- I/P= +V volts, Transistor’s emitter- base Junction ‘ll clearly be


forward biased. Assume a similar O/P ckt connected to this points ‘ll have
a voltage of 3.6-0.65=2.95volts applied across a series combination of
RB&RC, so The BASE CURRENT
2.95v/1110Ω=0.00265amperes=2.6ma.
Resistor- Transistor Logic (RTL)

VL- Nominal voltage, corresponding to a high-logic state

VH - Nominal voltage, corresponding to a high-logic state

VIL -Maximum input voltage, that will be recognized as a low input logic level

VIH -Maximum input voltage, that will be recognized as a high input logic level

VOH -Maximum output voltage, that will be recognized as a high output logic
level

VOL -Maximum output voltage, that will be recognized as a high output logic
level
Resistor- Transistor Logic (RTL)
VCC
5V

Ideally matched BJTs and R4


Base resistor using a common
collector resistor

Q1
RB1 RB2 RB3
Q2 Q3

ANALYSIS

Current in single collector resistor is the sum of BJT collector current & given by

IRC =I1+I2+I3+…….IN εIc,I


IRC =

Output voltage Vout=VCC-IRC *RC- ------------------1


Let RB1=RB2=330KΩ, RC1=RC2=1.2KΩ
VCC
5V

Resistor- Transistor Logic (RTL)


R4

Q1
RB1 R B2 RB3
Q2 Q3

Case VIN1 =VIN2 =5v OR A=B=1

IB1 =[VIN1 -VBE ]/RB1 (5-0.7)/330KΩ=13.03μA=IB1

IC1 =β1*IB1 150*13.03 μA=1.95mA=IC1


309mA=IRC
IRC =IC1+IC2

SO OUTPUT VOLTAGE IS
Vout =
(5- (3.9 mA * 1.2KΩ)=0.32v=Vout

When both inputs are high, both Transistors are saturated and carry equal
currents, and output voltage is VCE (sat) [Low]
Resistor- Transistor Logic (RTL)
Case – One of the input is High, and other is Low, Then the
transistor with the high input operates in the saturation
region carries the current and the voltage drop across it is
VCE(Sat) Thus the output is LOW
VOLTAGE LEVEL TRUTH TABLE
0 0 5 0 0 1
0 5 0.2 0 1 0
5 0 0.2 1 0 0
5 5 0.32 1 1 0

NOR Operation in term of Boolean Algebra C=A’+B’


Resistor- Transistor Logic (RTL)
VCC
Two I/P RTL configuration with
stacked BJTs. Assume β>>1 for
R4 both BJTs, The base current are
negligible in comparison with the
R1 collector currents
Q2
Vin-A IE1=IC1
R2
And IE2=Ic2
Vin-B Q1 Clear, IC1=IC2=IRc
Suppose RB1=RB2=330KΩ, RC1=RC2=2.5KΩ
Vcc=5V, β1=β2=150, VIN1 =VIN2 =Vcc

IB1= ?
IC1= ?
VOUT= ?
Resistor- Transistor Logic (RTL)

IB1=(VIN1-VBE)/RB1= (5-0.7)/330*103 =13.03μA


Ic1=β*IB1 = 150*13.03*10-6 = 1.95mA

As Ic1>>IB1, SO

IE1≈Ic1 Similarly IE2≈IC2


Ic1≈IE2
There for Ic2=1.95mA Ic1=Ic2=IRC

So voltage output is Vout -=Vcc -IRC Rc


= 5-(1.95mA*2.5kΩ)
=0.125v

Assignment calculate further case wise


Resistor- Transistor Logic (RTL)

RTL Power dissipation


The average power dissipation of RTL gates depends upon
the output current of RTL gates which depend upon the high or low sate of the
output. The two current are Icc(oL) and Icc(oH)

Generaly the power dissipation in a gate with all input at


HIGH level is called PDH. With I/Ps at low level called PDL.
The average PDavg= (PDH+PDL)/2
This NO. is obtained by assuming the I/P to gate spends as
much at time low level as it does at HIGH level, that there
is a 50% duty cycle.
Resistor- Transistor Logic (RTL)

RTL fan-out
When an RTL gate such as NOR gate is in the output low
sate, any load gate would be cutoff and draw no input
current, since VIN =VCE(SAT)<VBE(
For driving gate in the output high state, all the load gate
operating in saturation and draw input current. The
maximum Fan-out of RTL gate is therefore limited by the
output high state of the load gate
Resistor- Transistor Logic (RTL)
NOISE MARGIN> The input signal to a gain can be corrupted by some
unwanted & unexpected signal. If the gate is not properly designed the
unwanted signal can force the gate to malfunction. A noise margin is the figure
of merit for the gate.., The higher the noise margin, the less susceptible the
gate to malfunction.
Leakage current
>218μA to 100 μA
RTL obsolete due to below draw backs
Bulkiness,
Low speed,
Limited fan-out,
Poor noise margin
Mostly RTL logic use in latches, buffers, counters etc
Transistor Transistor Logic (TTL)

The major goal in IC manufacturing is to reduce


the total chip area & the component which cover
large area are resistor & capacitor so to reduces
these components as far as possible )
Transistor Transistor Logic (TTL)

In TTL gates, to eliminate Resistance is not entirely possible. Hence


the density of TTL gates is much less than the that of CMOS gates.

TTL use BJT technology for manufacturing VLSI gates.

In MOS Ic gates, all components are madeup of MOS transistors


alone, which make them highly dense
Transistor Transistor Logic (TTL)

In TTL the D1, D2 Replace with a multiple-emitter Transistor T1

A & B represent two separate base-emitter


junction of transistor, which act as two
independent Diodes.
The Collector-base Junction of T1 forms diode D3
of DTL Gates.
Consider A TTL NAND circuit which available
in IC 7400
As the T1 is multiple-emitter transistor.
T2 is Phase-splitter driving output
TransistorsT3 and T2.
The output Section Consisting over T3
& T4 ,Diode (D) and 100 ohm Resistors
known as totem pole Configuration
since it looks like totem-pole with its
ups and downs.
If D and T3 Removes then A open-
collector configuration is seen
Transistor Transistor Logic (TTL)
7400 IC

Situation-1
Let A & B both in saturation=0v at logic -0v
T1 –Forward Bias & Current flow from VCC
Through BE of T1 to Ground
•This makes the Base collector diod of T1
reverse biased, and prevents the current
from flowing into the base of Transistor T2.
Since there is no current flow through its
base,
•T2 remains OFF making its collector
current Ic2=0and Collector voltage Vx-Vcc.
And Also the Collector Current of T2 is
Zero, Its emitter voltage Vy=0.
Transistor Transistor Logic (TTL)
Let A & B both in saturation=0v at logic -0v
7400 IC
•T2 OFF, Ic2=0 and Collector voltage

•Vx-Vcc.
•And Also the Collector Current of T2 is Zero, Its
VE=Vy=0.
•the states of the totem-pole Transistor T3& T4

Let Collector Voltage of T2, Vx=Vcc and T3 is


turn On it act as a short circuit between the
VCC and Z
•As VY =0, Transistor T4 Remain OFF
•So the T3 is on and T4 is off
It is find that Z of The TTL NAND, and when
A=B=0, VCC OR logic 1.
Transistor Transistor Logic (TTL)
7400 IC
Situation-2 A=0,B=1or
A=1,B=0
In both case one of the
Diodes is conducting and
input is grounded.
So the result will be same
as
A=B=0
Transistor Logic (TTL)
Situation-3 Situation 3. If A=B=1. Now
7400 IC
Both diodes Remains Reverse Biased. So,
Current flows from VCC through the base-
collector diode of T1 into the base of T2 turning
it ON.
The Collector current of T2 Starts flowing now.
Developing enough voltage(.8v) at its emitter Y
to Turn T4 ON.
Also, Since T2 is ON its Collector –emitter
voltage drops to the saturation value
VCES=0.2v and its collector voltage
Vx=0.8+0.2=1V With Diode D present, T3
Remain OFF. However Since T4 is ON, the
collector-emitter voltage of T4, VCES=0.2V, and
output Z is at Logic 0.thus for the situation

A=B=1Get Z=0.
Transistor Transistor Logic (TTL)
Totem pole Configuration

In totem-pole output section, Transistor T3 acts as the Load of Transistor T4 why?

Let replace T3 with Load Resistor ( RL)

Assume that input terminals are shorted


and trigger pulse applied to it.
So, as in Ideal situation when the trigger
is applied, it is expected the NAND gates
to switch suddenly from OFF to ON state
& vice versa.
But practically it is not the case.

It is find that these exists parasitic


capacitance due to various types of
dielectrics existing between wires,
transistor terminals.., etc, at the Output
of a TTL gate.
These effect represented by
CL
Transistor Transistor Logic (TTL)
Totem pole Configuration

Now, when a trigger pulse is applied to the input of TTL gate to produce transition
of the state, so find that CL must be charged OR discharged First before
transition is completed.

Case:- Consider +VE trigger pulse being


applied to the input of the gate,. this make T4
ON and CL is discharges through transistor T4.
As, Its known that the ON-resistance of a BJT
is very small. There fore, CL discharges very
fast through T4.
Now come to the situation. When Input is 0
(zero) and output of the NAND gate is 1.

This Transition from 0 to VCC will be


completed only after CL has been fully charged
to Vcc through RL.
Transistor Transistor Logic (TTL)
Totem pole Configuration

Case:- If RL is pure resistor, CL will be


large to avoid large power dissipation
(this technique called passive-pull-up due
to use of passive component R so
convert the Pull-up to active pull-up by
using transistor T3 on the top of
Transistor which is active component.)

So when 0 input is applied, the output


rises to VCC through T3, which is now
ON state. As the T3 has low ON
resistance and hence charges CL fast.
Thus the active use to produce faster
transition in the switching between sates
Transistor Transistor Logic (TTL)
Totem pole Configuration
NEED FOR THE 100 Ohm RESITOR ON TOP OF T3

IF there were only transistor in the output


stage, while switching from ON-to-OFF or
OFF-to-ON will be moments when the output
transistors become dead short across the
supply before steady state is reached. This
will draw heavy current and destroy the
transistors T3 and T4. to prevent this, we use
the 100 Ohm resistor, which limits the output
current to a safe value
Transistor Transistor Logic (TTL)
Totem pole Configuration
USE OF DIOD (D)

Let there is No Diode and T4 is in saturation


(ON) at this time, we want T3 to to be OFF.
To invert This., Consider T2 to be ON, then
heavy collector current flows through T2 to
develop enough potential at point Y Which
turn ON T4.

Since T4on Requires its Base-Emitter


voltage VBE4 =VBES . When VBES is the
saturation Base-Emitter Voltage(0.8v) ,It is
Find that Y is Clamped at o.8v.
Therefore, the voltage at X is
Vx=VBES of T4 +VCES OF T2 =0.8 + 0.2
=1.0V=VB3 w.r.t.Ground
Transistor Transistor Logic (TTL)
Totem pole Configuration
USE OF DIOD (D)

Vx=VBES of T4 +VCES OF T2 =0.8 + 0.2


=1.0V=VB3 w.r.t.Ground
Now the Collector of T4(Hence emitter of T3) is
at VCES(0.2V) w.r.t ground. Therefore,
VBE3(base-emitter voltage of T3)=1.0-0.2=0.8V.
A voltage of 0.8v between the base and emitter
of T3 means that it is in saturation, where as our
assumption was that T3 was OFF. Hence to
ensure that T3 is indeed in the OFF state,
Diode(D) is introduced in between the emitter of
T3 and collector of T4. The drop across the
diode is usually 0.6v so that T3 is indeed in the
Cut-off state with its base having not enough
voltage to turn it ON.
NAND Gate As Whole

IC 7400 Quad NAND Gate


NAND Gate from IC 7400
(Internal structure of NANAD gate)
TTL Inverter
Discuss Characteristics

The inverter characteristics is that by varying input


voltage from 0V to +5 V in step of 0.1V the
corresponding values of voltage is such that
when Vi=0V , output Vo=5V, and vise versa. It's
mean that Ideally, the transition from logic 0 to 1
& 1 to 0 should occur in time t=0 second. But if
we study it practically it make some differ
TTL Inverter
Discuss Characteristics

+5V +5V Slop


–1.6
A B
3.6V
1.6k
2.4V C
Slop
IB1 RB1 =4K –-22

D
Vx T3 Vi=0.2V E
0.7V 1.2 1.3V Vi
T1
T2 V
VBE3 + VD
Vi=0V D
VBE2
V0
T4
VB2 =0.2V

VRE2

RE2 =1K
Slop
TTL Inverter
–1.6 Discuss Characteristics
A B
3.6V
C
Let, Draw the plot of the Inverter, vary the
2.4V Slop
–-22
voltage Vi in steps of say 0.1V each, and
note the corresponding output Voltage.
D Let First, Vi=0V. Then it is find that Vi-0,
Vi=0.2V E
1.3V
Transistor T1 starts conducting and its base
0.7V 1.2 Vi
V current IB1 Start flowing, The Value of IB1 is
as havimg the Voltage across the 4-K base
resistor of T1
VRB1 = VCC - VBES1 = 5-0.8=4.2V
VBES1 is the Base-emitter saturation Voltage of T1.
So, IB1 =4.2/4k=1.05 mA
1. Hence, the base current turns T1 ON and its collector-emitter drop
VCE1 becomes the saturation value VCE1= 0.2 V.
2. SO, the Voltage at the base of T1 W.R.T. THE GROUND,
VB2= VCE1=O.2v.
This keeps T2 OFF and turns T3 ON, since the voltage at point X,
3. VX= VCC =From Dia, Output Voltage

Vo = VCC - VBES3 -VD = 5 - 0.8 - 0.6=3.6V


Where VBES3 is base-emitter saturation Voltage of T3, and VD is Voltage Drop across
the Diode D. There may be slight variations in this value of 3.6V.
NAND Gate from IC 7400
(Internal structure of NANAD gate)

Suppose VBES3 may vary from 0.7 to 0.8V. and VD` may vary from 0.6 to
0.7v then Vo may vary from 3.6 to 3.4V.
Consider now the input being slowly increased in step of 0.1v from its initial
value of 0V. It is find that Vo remain constant at 3.6V up to about Vi=0.7V. It is
because up to 0.7V,
VB2 = Vi(0 to 0.7V)+ VCE1 (0.2V)
At about Vi=0.7 V, VB2 =0.7 + 0.2=0.9V. Let the voltage be divided
between VBE2 and VRE2, where VBE2=base-emitter voltage of T2, and
VRE2=Voltage drop across the 1-K emitter resistor of T2,
LET VBE2=0.5V and VRE2=0.4V. when VBE2=0.5V(cut-in voltage),
T2 will enters into its active region and begins to act as an amplifier. Since RE2
is not bypassed, T2 will act as a current-Series feedback amplifier with gain,

AV2=RC2/RE2=1.6K/1K=1.6
NAND Gate from IC 7400
(Internal structure of NANAD gate)

+5V +5V AS T2 begins to conduct, Collector current


Ic2 starts flowing through RC2 and RE2 At
RC2 =1. Ic2 this time, we still have T3 ON and T4 OFF.
4 6k
K
Therefore, when IC2 flows to develop
Vx VRC2=IC2RC2, The Voltage at point X, Vx
T1
VCE1 =0.2
T2 will drop by this value from its original
V value of Vcc=5V.
VBE2 =0.5
V
Vi=0.7
When Vx=5 - IC2RC2, Vo also drop by the
VB=0.9V
V same factor from 3.6V. Therefore
VRE2=0.4 RE2 =1K
Vo=3.6-IC2RC2
V

From the Equation it is clear that as th IC2 is Increasing, The output voltage is unoforlmaly
decreasing from 3.6V with a slop of –1.6, equal to the gain of the current-series feedback
amplifier T2. This state will continue up to about Vi=1.2V. If Vi=1.2V, It is find that

IB1(base current of T1)= Vcc-VBE -Vi =5 – 0.7 –1.2 = 0.7mA

RB1
NAND Gate from IC 7400
(Internal structure of NANAD gate)

This show that T1 is still in Active Region. For Vi=1.2 V , The Voltage Level will be
VB2=1.2+0.2=1.4V [= VBE2 + VRE2=0.8(assumed) +0.6V(assumed)]

For VBE2= 0.8V, Find that T2 in saturation, and its


collector-emitter voltage VCE2=0.2 V. Also find that
+5V
+5V T2 is still acting as a current-series feedback
1.6k
amplifier, and with an input voltage of 0.75V, Its
4K
IC2 collector voltage is
–1.6 * 0.75= -1.2V and
Vo= 3.6 – 1.2= 2.4V( shown in graph)
T1
0.2V T2

VBE2=0.8V
Notice that, Since VRE2=0.6 V,
V0 VBE4 =0.6V this make T4 star
T4 conducting.
VB2 =1.4V
Vi=1.20 RE2 =1K
V VRE2= VBE4=0.6V
NAND Gate from IC 7400
(Internal structure of NANAD gate)

Again, Increase the Input voltage more than 1.2 V, say 1.3V , Find that
VRE2 becomes greater than 0.6V, and T4 enters into saturation. With T4
in the conducting state, we find that the output voltage Vo=0.2V. This
drop from 2.4V to 0.2V when Vi is 1.2V and 1.3V respectively, is very
sharp, and has a slop of approximately
-((2.4-0.2)/0.1)) =22 (indicated by line CD )
When input is above 1.3V the output remains constant at 0.2V, which indicates
that TTL inverter is outputting a Logic 0.
Slop –1.6

A
B
3.6V
C
2.4V Slop –-2.2

D
Vi=0.2V E

0.7V 1.2V 1.3V Vi


Open Collector Output Gate )

In this Configuration Transistor T3 is removed from the Totem-Pole


configuration Then we can get Open Collector TTL gate. ( NAND gate )

The out put is taken from the


open collector of T3. A external
resistor connected to Vcc must
be inserted to the IC package for
the output to “pull up” to the
high voltage level when T3 is off:
otherwise, the output acts as an
open circuit.
If any input is low The
corresponding base-emitter junction
in T1 is forward biased. The Voltage
at the base of T1 is equal to the
input voltage of 0.2V plus a VBE
drop of 0.7 or 0.9V
Open Collector Output Gate )

In order for T3 to start conducting, the path


from T1 to T3must overcome a potential of
one DIOD drops in T2 and T3 or 3*0.6=1.8V.
Since the base of T1 is maintained at 0.9V by
the input signal, The output Transistor can not
conducted between the output and Vcc(or an
open ckt if a resistor is not used)
If all inputs high, both T2 and T3 conducted and
saturate.

The base voltage of T1 is equal to the voltage across its base-collector PN


Junction plus two VBE drops in T2 and T3, or about 0.7*3=2.1V. Since all
inputs are High and greater than2.4V, the base-emitter junction of T1 are
reverse biased. When output transistor T3 saturates, the output voltage goes
low to 2.0V. This confirm the condition of NAND operation. goes low to 0.2V,
APPLICATIUON OF OPEN COLLECTOR GATES
these gates used to driving a lamp or relay, performing wired logic, and for
the construction of a common-bus system.
An open-collector output can drive a lamp placed in its output through a limiting
resistor. When the output is low, the Saturated transistor T3 forms a path for the
current that turns the lamp ON . When the output transistor is off, the lamp turns
off because there is no path for the current

Wired Logic
If the output of several open-collector TTL gates are tied together with
a single external resistor, a wired-AND logic is performed. Remember
that a positive-logic AND function gives a high level only if all variables
are high; otherwise, the function is low. With the outputs of open –
collector gates connected together, The common out put is high only
when all output transistors are off and vise versa
APPLICATIUON OF OPEN COLLECTOR GATES [Wired Logic ]

The Physical Wiring shows the outputs must be connected to common resistor

The AND function formed by the connecting together


the two outputs is called a wired- and function. The
Boolean function obtained from the circuit is the AND
operation B/w O/P of two NAND.
Y=(A’B’).(CD)’ = (AB+CD)’
The open –Collector gates can be tied together to form a common bus .At any
time all gates can be tied together to form a common bus

At any time all gates output tied to the


bus, except one , must be maintained in
their High sate, The selected gate may
be either in high or low state. Control ckt
must be used to select particular gate
that drives the bus at any time.
TRI-STATE Logic Gates
In this type of logic a third state is introduce and this state is known as Hi-impedance (high-
Z) state. So called tri-state logic gate. They are used as buffer gates. Fi is the modification of
NAND gate with addition of diodes D1 and D2 and an inverter gate.

+Vcc Operation
Let initially the chip-select enable input CS=0. This makes
1.6K
CS’=1, which reverse biase the diodes D1 and D2. In this
condition. The circuit behaves as a normal NAND gate.

Data T3
IN B
T2
Now, Let Cs=1, so that CS’=0. The diodes D1
D1 D2 and D2 are now forward biased. Then, we find
Enabl that the base and collector of T2 are grounded
e T4 Vo through the ON-diodes. This puts both T3 and
CS CS T4 in the OFF-state and the impedance of the
1K
output stage becomes very high. This is the third
high-Z state.
TRI-STATE Logic Gates
In such a state, several gates can be OR-ed together. of the tri-state.
Practical application of the tri-state buffers are mainly used in Bus lines to
transfer data from one register to other Register
Tri-state
buffers
Bus ines
R-A As FiG That DATA from Register A can
be transferred to any other required
section through the common bus lines
which are shared by Register B.

Tri-state
buffers

R_B B
TRI-STATE Logic Gates

The Register A can be enabled or disabled by using the


chip-select terminal. Those tri-state buffers you want to
operate are enabled, and Those you don’t want to be
operated are disabled. Suppose the tri- state gates
associated with Registers A and B are enabled, and some
others disabled. Then DATA will flow from A to B through
the common bus lines, but it will not flow into those gates,
which are disabled.
T.T.L. PERFORMANCE CHARACTERISITCS

We have several performance characteristics for TTL.


Propagation delay time: it is the low speed and high
speed of logic circuit. At shorter propagation delay, higher
the speed of circuit and higher the frequency at which it can
operate.
 Propagation delay time: it is the time interval b/w
application of an input pulse and the occurrence of the
resulting output pulse. We have two ways for measurement
of propagation delay time.
T (PHL): it is the time b/w a specified reference point on
the input pulse and a corresponding reference point on the
resulting output pulse.
T.T.L. PERFORMANCE CHARACTERISITCS

Power dissipation: it is the product of supply voltage and the


average supply current.

Low-power TTL: its switching speed is 33n sec with 1mW power
consumption.

High-speed TTL: with faster switching speed than standard TTL


(6ns) but significantly higher power dissipation (22mW).

Shottky TTL: These gates operated more quickly (3ns) but had
higher power dissipation (19mW).

Low-power shottky to provide a good combination of speed


(9.5ns) and reduced power consumption (2mW). Probably the most
common type of TTL since these was used as glue logic in
microprocessors
Emitter
Coupled Logic
Emitter Coupled Logic

It is named for BJT that are coupled with there emitters (joined).

It has traditionally the faster of logic families with propagation delay of 1
or 2ns

So we can call this type ”advanced short key teach” in this preventing
the transistor to go into the deep saturation so thus eliminating the
storage delays.

So this is a accomplish that in ECL families by sing logic levels are so
close to each other because that transistor are not driven into saturation
when switch turning from low to high.
Emitter Coupled Logic

Logic Values:
In ECL circuitry both 0 & 1 are also negative levels are 0 = -1.7V and 1 = -0.9V
figure shows fundamental compensation of ECL Logic Gates so this is
current pair switching circuit so current drawn by negative supply flows through
Q1 and Q2 However it is basically a difference amplifier so its operation by
using diodes can be modified

Figure shows the ECL logic gates. R1 R2


1kohm 1kohm
Some analysis views this circuit
as a current-switching analysis
because the bases voltages of Q1
Vin -1.3v
& Q2 determine whether current
drawn by the negative supply R3
flows through Q1or Q2. However, 1kohm

it is basically called “differential


amplifier” -5.2V
V1

Note:- Fundamental gate in ECL Family is OR and NOR


Emitter Coupled Logic In Detail Structure

Set of differential amplifiers consisting of transistor T1, T2 and T3. Which


drive two emitter-follower stages comprising transistors T4 and T5 to
deliver complementary outputs Z and Z’ As The T3 has load resistor 300Ω
For ideal Op-Am configuration, the load of T2 must also be of 300 Ω
R 300Ω
The main feature of ECL
T5 gates is that the collector
terminals of its transistors
Y
T4 are grounded, and a DC
supply voltage of –5.2v is
applied to the emitters. This
B
A T1 T2 T3 negative supply voltage
-VR
z z makes the calculations
X slightly difficult, since mostly
1.5 k familiar with +ve supply
VBE = -5.2v 1.18 k 1.5 k voltages
WORKING PRINCIPLE OF THE ECL OR-NOR Gate

As ECL is basically a differential amplifier, working in as active region.


So the voltage swing (200mv ) is very low. Also ,It dissipate a large
amount of power, as the circuit draw heavy collector current at all times
of operation . There is No OFF state of ECL gate to reduce the power
loses, It is the fastest gate ,Typically the speed of few giga hartz

R 300Ω
T5
Y T4

T1
B T2 T3
A -

X
VR z z
1.5
1.18 1.5
VBE = k
k
k
-5.2v

Note:- Now CMOS have the speed of 1.5 GH and more


WORKING PRINCIPLE OF THE ECL \
Voltage levels Analysis at various nodes of Circuit
Logi-0 Level of ECL
Consider fig, the circuit connections and
R + 300Ω node voltages in detail.
0.85v- Let the input A be at logic 0 level. This
Y T4
+ makes T2 OFF and T3 ON.
VBE4=0.7v
- The Voltage at node X can be calculated by
A T2 OFF T3
zassuming VBE3 =0.7v, where VBE3 is the
5.2V + VR –(1.15v)
VBE3=0.7v
Vx=--
X
I
- base-to-emitter voltage of transistor T3,
1.85v 1.18 k -5.2V 1.5 k assume it to operate in the active region. Find

Vx= -VR – VBE3=-1.15-0.5=-1.85V


As the supply –5.2v. So, the V drop across the 1.18KΩof the differential pair is
V1.18K=-VX – (-VEE)=-1.85 – ( -5.2) =
3.35V
Therefore, the current through the 1.18k resistors is given by:
I=3.35/1.18=2.84mA
This current flowing through the collector of T3 will produce a drop of 0.85v
across the 300-ohms collector resistor of T3. Thus, the node Y is at –0.85v
with respect to ground under this condition. Assuming T4 to be ON this time,
the voltage output at node Z(emitter of T4) is: VZ= -0.85-0.7=-1.5v
WORKING PRINCIPLE OF THE ECL \
Voltage levels Analysis at various nodes of Circuit
Logi-0 Level of ECL
R + 300Ω
0.85v In the logic-0 level, all the transistors
-Y
+
T4 operate in their active region rather
VBE4=0.7v
- than in cut-off and saturation. Then,
5.2V A T2 T3
VBE
+
3=0.7v
VR–(1.15v)
z that the transistor T2 (orT1) in indeed
Vx=--
X
I
- in logic 0 may now be ascertained by
1.18 1.5
1.85v
k
-5.2V
k considering the fact that with voltage
at A

VA= -1.5v and VX= -1.85v


VBE1=VBE2= -1.5 – (-1.85)= 0.3v

As the Min. BE voltage to conduct is 0.4 to 0.5,so T1 and T2 are


indeed in the OFF state
WORKING PRINCIPLE OF THE ECL \
Voltage levels Analysis at various nodes of Circuit
Logi-1 Level of ECL
logic-1 condition being applied to
R + 300Ω
0.85v input A. This makes T1 (or T2) ON,
-Y
T4 and the collector current switches to
+
VBE4=0.7v
- R form the 300-ohms resistor. With
T3
5.2V A T2
VBE
+
3=0.7v
VR–(1.15v)
z T3 OFF. Its collector voltage VY is at
Vx=--
X
I
- ground potential, as no current is
1.5
1.85v 1.18
k
-5.2V
k now flowing through the 300-Ω
resistor. Again, with T4 in the active
region, VBE4 = 0.7V.

Since T4 is an emitter-follower, The output voltage VZ=VBE4=0.7V..


Thus, the output voltage for logic 1 at point A given by VZ= -0.7V

So, for the ECL-OR-NOR gate, the logic levels are given by
logic-0 level= -1.5V Logic-1 level= -0.7V.
Output swing of an ECL gate is only
Vout-swing= -0.7 – ( -1.5)=0.8V
ECL Noise margin
R + 300
-YΩ
0.85 T
v VBE4+
=0 4
-
A T T
5.2
+ VR–.7v z
V
2 3VBE 3=0.7v (1.15v)
Vx=--
X
I - 1.5
1.85v 1.18 -
k k
5.2
V Nose margin is calculated as under

OFF-state voltage at A, VOFF =0.3V

Cut-in voltage of the transistor, VBEC = 0.5V

Therefore, Nose margin = 0.5 - 0.3= 0.2 V

Hence ECL gates have very low noise


immunity
ECL
Case study

R2
1kohm R1
1kohm -1.7v
B1 -1.3v
B2
Vin Q1
Q2 -1.3v
=-1.7v (OFF)
(ON) D1 D2
- 2.1v +
R3 0.8V
1kohm -
VB1X R3 VB2X
1kohm

-5.2V -5.2v
V2

VB1x=VB1 - VX=- 1.7 - ( - 5.2 v) =3.5 V


VB2X=VB2 - VX=- 1.3 - ( - 5.2 V) =3.9 V

When Vin is low (-1.7v), Q1 is off andQ2 is on, because base to emitter
junction of Q2 is “most” forward- biased
ECL
Case study
(c) When Vin is high (-0.9v), Q1is on and Q2 is off, because base-to-emitter junction
of Q1 is “most” forward-biased
VB1x=VB1 - VX = - 0.9v - ( - 5.2 v) = 4.3 V
R2
1kohm R1
VB2X= VB2 - VX= - 1.3 - ( - 5.2 V) =3.9 V
1kohm -0.9v B1 -1.3v
B2

Vin Q1 (on)
Q2 -1.3v
=-0.9v D3 D1
(off)
2.1v
R3
R3 1kohm
1kohm

-5.2v
-5.2V
V2

Because its base-to-emitter voltage is only -1.7v – (-2.1v)=0.4v. When


Vin is 1 (-0.9v), Q1 is ON (but not saturated) is on and Q2 is off,
because Total voltage tending to forward-bias the base-to-emitter of
Q1 is 4.3v & that for Q2 is 3.9v. The emitters are at -0.9v -0.8v=1.7v.
The Current IE flowing in R3 can be found from =(Vin-VBE(on) +
5.2v)/R3
ECL
Case study

Two input ECL NOR / OR gates

R2
1kohm R1
1kohm
Q3

Vout NOR
Vin Q1b
Q1a Q2 -1.3v
Av Bv 1kohm

2.1v Q4
12V
R3
1kohm
1kohm

-5.2V Vout OR
V2 12V
ECL
Case study
When A&B are both below, Q2 Conducts, the NOR output is high &
the OR output is low

R2
1kohm R1
1kohm
Q3

Vout NOR=-0.9v
Vin Q1b
A=-1.7v Q1a Q2 -1.3v
Bv 1kohm

2.1v Q4
B= -1.7v 12V
R3
1kohm
1kohm

-5.2V Vout OR=-1,7v


V2 12V
ECL
Case study
When at the least one input is high the OR output is high is high and
NOR output is low Input & Output Characteristics

R2
1kohm R1
1kohm
Q3

Vout NOR=-1.7v
Vin Q1b
A=-1.7v Q1a Q2 -1.3v
Bv 1kohm

2.1v Q4
B= -0.9v 12V
R3
1kohm
1kohm
-5.2V Vout OR=-0.9v
V2 12V
ECL

ECL Nor gates in modem circuits have internal pull-down resistor


connected between each input and the negative supply.

These resisters provide paths for the leakage current to prevent the
build up the charge on stray capacitance when inputs are open.

Thus unused inputs can be left unconnected. The pulls down resistors
effectively hold unconnected inputs low.

Since an ECL output is produced at an emitter follower, so the output


impedance is too small, typically 7ohm. ECL has very fan outs and
relatively unaffected by capacitive load.

Some ECL gates are available with multiple outputs derived from multiple-
emitter transistor in the emitter follower output
ECL Subfamilies and Specification:

Motorola introduced ECL in 1962 with product line market as its


MECL-I series, followed in1966 by in 1966 by its MECL- II series
.These lines are now obsolete, having been replaced MECL III series
carrying MC1600 numbers , an MECL 10k series carrying MC100
numbers, and most MECL 10k series with MC10H000 numbers.

ECL subfamilies do not include as wide range of general purpose of


logic gates as do TTL and CMOS families. The most significant
enhancements in 10KH series are (1) A 100% improvements in speed
(compared to 10K series); (2) Replacements of the resistor R3 in both
figures by using transistor current source, which maintain the constant
current (3) An Improvement internal regular voltage to the supply -1.3V
compare to sub families
Comparison of the typical speed-power relations ECL
subfamilies & logic families

Model Name Propagation delay Power Per gate Speed-Power


Product
MECL, 10KH series 1 ns 25 mW 25 pJ

10100,10500 2 ns 25 mW 50 pJ

10200,10600 1.5 ns 60 mW 37 pJ

MECL III 1 ns 60 mW 60 pJ

ASTTL 1.7 ns 8 mW 13.6 pJ

ALSTTL 4 ns 1.2 mW 4.8 pJ

HCMOS 8 ns 0.17mW(At 100khz) 1.4 pJ


ECL Comparison

Advantages
It has traditionally the fastest of logic families with
propagation delay of 1 or 2nS
Disadvantages
It provides the common mode rejection
One disadvantage is It is difficult to achieve good
noise immunity when logic level close in values.
They greater power consumption than other families
NMOS (N-type Metal-
oxide Semiconductor)
Logic gates
NMOS (N-type Metal-oxide Semiconductor) Logic gates

This family makes use of NMOS FET for constructing logic gates. And
In NMOS all components (Resistor & capacitor) are formed by NMOS
transistors.
So, it is all transistor circuit configurations so that’s why it have very
high packing density and providable at very low cost

NMOS INVERTOR
Depletion
Here Transistor T1[Enhance type] is the
+VDD MOSFET main switching device, and T2[Depletion
type] acts as its load resistor.Let gate of
Enhancemen T2
t MOSFET T2 is shorted to its source, making
VGS=0. This keeps the transistor in the
Vo=A’ ohmic region of the characteristics and T2
T1 will act as a load resistor
NMOS (N-type Metal-oxide Semiconductor) Logic gates

NMOS INVERTOR
Depletion
+VDD MOSFET

Enhancemen T2
t MOSFET

Vo=A’

T1

When input A=0, T1 is OFF and Vo = +VDD(logic 1).


When A=1(+VDD ). T1 conducts and Vo=0V so it can say
that circuit perform inversion
NMOS (N-type Metal-oxide Semiconductor) Logic gates

NMOS NAND GATE


T1,T2 are enhancement type and T3 which act as a load
resistance, is of the depletion type.

Let A=B=0 Transistors T1 and T2


Depletion will remain OFF. Then, Output
+VDD MOSFET
Z=VDD=1 same situation will remain
Enhancemen T3 in case of A=0&B=1or A=1&B=0.
t MOSFET
 If A=B=1 then both T1 & T2
Vo=A’ conduct and the output Z=0. this
T1 situation is of the NAND operation
and it is conclude that is a positive
logic NAND operation.
NMOS (N-type Metal-oxide Semiconductor) Logic gates

NMOS NOR GATE


T1,T2 are enhancement type and T3 which act as a load resistance, is
of the depletion type.
Here the logic 0
conduct the transistor in parallel.
represent 0V and logic
1 represent +VDD.
When 0V is applied at
+VDD
Depletion
MOSFET the inputs of the
Enhancement T3
transistors, they remain
MOSFET
OFF, and when VDD is
Vo=Z
applied at the inputs,
the transistors conduct.
So when A=B=0 Z=1,
A=B=1, Z=0
NMOS (N-type Metal-oxide Semiconductor) Logic gates

NMOS AND OR Invert Gate


Z = AB+CD
+VDD

T5
 T1 & T2 form one
AND gate and T3,
T3 C
T4 Form another
A
AND gate and the
D
parallel combination
B of these pairs will
produce an out Z
CMOS (PMosFET) LOGIC FAMILY
CMOS short for complementary metal oxide
semiconductor.
CMOS is a widely used type of semiconductor. CMOS
semiconductor use both NMOS (negative polarity)
and PMOS (positive polarity) circuits.
CMOS chip require less power than chips using
transistor. This makes them particularly attractive for
use in battery-power devices, such as portable
computers. Personal computer also contains a small
amount of battery-powered
CMOS memory to hold the date, time, and system
setup parameters
CMOS LOGIC FAMILY
VDD

Q1 Q2

CIRCUIT
DIAGRAM
OUT put
CMOS Q3
NAND GATE
Input A

Q4

In put B
CMOS LOGIC FAMILY
CMOS NAND GATE
Notice how transistors Q1 and Q3 resemble the series-connected
complementary pair from the inverter circuit. Both are controlled by the
same input signal (input A), the upper transistor turning off and the
lower transistor turning on when the input is “High” (1) and visa-versa.
Notice also how transistor Q2 and Q4 are similarly controlled by the
same input signal (input B), and how they will also exhibit the same
on/off behavior for the same input logic levels. The upper transistors of
both pairs (Q1andQ2) have their source and drain terminals paralleled,
while the lower transistors (Q3 and Q4) are series-connected. What is
means is that the output will go “High” (1) if either top transistor
saturates, and will go “low” (0) only if both lower transistors saturate.
The following sequence of illustrations shows the behavior of this NAND
gate for all four possibilities of in put logic levels (00, 01, 10, and 11).
CMOS LOGIC FAMILY
VDD

Q1 Q2

ON ON

OUTput=1
Q3

A=0
OFF

Q4

OFF
B=0
CMOS LOGIC FAMILY
VDD

Q
1 Q
2

ON ON

OUTput=1
Q
3

A=0
OFF

Q
4

OFF
B=1
CMOS LOGIC FAMILY
V
D D

Q
1 Q
2

ON ON

OUTput=
1
Q
3

A=
1
OFF

Q
4

OFF
B=
0
CMOS LOGIC FAMILY
V
D D

Q
1
Q
2

ON ON

OUTput=1
Q
3

A=1
OFF
Q
4

OFF
B=1
CMOS LOGIC FAMILY
As with the TTL NAND gate, the CMOS NAND gate circuit may be used as the starting
point for the creation of A B D gate. All that needs to be added is another stage of
transistors to invert the out put signal.
VDD

Q1 Q2
Q5
ON ON

Q3 O/P
Q6
A=1
OFF
Q4

OFF
B=1

NAND Inverter