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Integrated Circuit Design Techniques for

Ultra Low Power Consumption





Outline
Introduction
Traditional Low Power Techniques
MT-CMOS
Power Gating
Clock Gating
Subthreshold operation
Synchronous design
Asynchronous design
Conclusion


INTRODUCTION
The need to limit power consumption is increasing

At the same time modern ICs have high chip density
and high speed

So many low power design techniques have been
developed.

MTCMOS
MTCMOS is a variation of CMOS chip technology which
has transistors with multiple threshold voltage in order to
optimize delay and power

Low V
th
gates for speed.

High V
th
gates for low leakage.

POWER-GATING
Power gating is a technique used in integrated circuit
design to reduce power consumption, by shutting of the
flow of current to blocks of the circuit that are not
currently in use.
An externally switched power supply is a very basic form
of power gating to achieve long term leakage power
reduction.
CLOCK GATING
Clock gating is a popular technique used in many synchronous
circuits for reducing dynamic power dissipation .
Multi-supply voltage (MSV)
To provide higher flexibility in controlling the power and
performance trade-off.
In region-based MSV, circuits are partitioned into "voltage
islands" where each island occupies a contiguous physical
space and operates at one supply voltage..
1.8 v
0.9 v
SUBTHRESHOLD LOGIC

Where the
supply
voltage is
less than the
threshold
voltage of
transistor
Energy dissipated in Subthreshold
Operation
Total Active Energy
E
opt
= Minimum E
tot
= E
switch
+ E
leak

Switching energy: E
switch

Leakage energy : E
leak
E
opt
normally occurs in subthreshold region if speed is not
constrained.
Switching Energy= 1/2CVDD
Active leakage energy=VDDIleaktdelay

Voltage Scaling
As VDD is
lowered the total
active energy
decreases.



















SYNCHRONOUS DESIGN

Challenges with the clocked design
Chip partitioned into multiple timing domains
Clock Skew
Design being synchronous, single slow component or logic
slows down the whole chip.
Clock routing and buffering consumes large part of the Chip
Power
PVT variations





Clock skew

Clock skew is the
difference in
arrival time of the
clock signal to
different parts of a
circuit.



PVT variations
Process variations are
variations in the
dimensions of the
devices.
The power supply is not
constant and hence the
propagation delay varies
in a chip. The voltage
drop is due to nonzero
resistance in the supply
wires.
Temperature affects the
propogation delay.
Advantages of Asynchronous
No Clock Skew problem
Higher Performance
Increased Power Efficiency
Greater tolerance to variation in operating conditions
Greater Component Modularity

Handshaking Muller C circuit
In asynchronous circuit,
clock signal is replaced by
some form of handshaking.
It uses the 4 phase handshake
for communication.


Muller C circuit
Asynhronous Design Approach
It doesnt use a
common clock
signal, completion
signals for each
logic are to be
locally generated.
So called self timed
circuits.


Simulation Results
CONCLUSION
Flexible interfaces of asynchronous & absence of global
signal better suited for complex system design as in SoC

Energy efficient

As technology advances, less costly for complex designs

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