Combinational Circuits
1
Designing Combinational
Logic Circuits
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Combinational Circuits
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Combinational vs. Sequential Logic
Combinational Sequential
Output = f ( I n )
Output = f ( I n, Previous I n )
Combinational
Logic
Circuit
Out In
Combinational
Logic
Circuit
Out
In
State
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Combinational Circuits
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Static CMOS Circuit
At every point in time (except during the switching
transients) each gate output is connected to either
V
DD
or V
ss
via a lowresistive path.
The outputs of the gates assume at all times the value
of the Boolean function, implemented by the circuit
(ignoring, once again, the transient effects during
switching periods).
This is in contrast to the dynamic circuit class, which
relies on temporary storage of signal values on the
capacitance of high impedance circuit nodes.
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Combinational Circuits
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Static Complementary CMOS
V
DD
F(In1,In2,…InN)
In1
In2
InN
In1
In2
InN
PUN
PDN
PMOS only
NMOS only
PUN and PDN are dual logic networks
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Combinational Circuits
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NMOS Transistors
in Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
X Y
A B
Y = X if A and B
X
Y
A
B
Y = X if A OR B
NMOS Transistors pass a “strong” 0 but a “weak” 1
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Combinational Circuits
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PMOS Transistors
in Series/Parallel Connection
X
Y
A B
Y = X if A AND B = A + B
X
Y
A
B
Y = X if A OR B = AB
PMOS Transistors pass a “strong” 1 but a “weak” 0
PMOS switch closes when switch control input is low
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Combinational Circuits
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Threshold Drops
V
DD
V
DD
÷ 0 PDN
0 ÷ V
DD
C
L
C
L
PUN
V
DD
0 ÷ V
DD
 V
Tn
C
L
V
DD
V
DD
V
DD
÷ V
Tp

C
L
S
D S
D
V
GS
S
S D
D
V
GS
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Combinational Circuits
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Complementary CMOS Logic Style
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Combinational Circuits
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Example Gate: NOR
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Combinational Circuits
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Combinational Circuits
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Combinational Circuits
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Example Gate: NAND
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Combinational Circuits
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Combinational Circuits
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Stick Diagrams
Contains no dimensions
Represents relative positions of transistors
In
Out
V
DD
GND
Inverter
A
Out
V
DD
GND
B
NAND2
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Combinational Circuits
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Combinational Circuits
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NOR GATE IN DEPLETION LOAD
TOPOLOGY
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Combinational Circuits
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Combinational Circuits
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Complex CMOS Gate
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Combinational Circuits
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Complex CMOS Gate
OUT = D + A • (B + C)
D
A
B C
D
A
B
C
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Combinational Circuits
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Constructing a Complex Gate
C
(a) pulldown network
SN1
SN4
SN2
SN3
D
F
F
A
D
B
C
D
F
A
B
C
(b) Deriving the pullup network
hierarchically by identifying
subnets
D
A
A
B
C
V
DD
V
DD
B
(c) complete gate
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Combinational Circuits
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Stick diagram
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Combinational Circuits
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Minimize areaEulers path
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Combinational Circuits
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Combinational Circuits
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Stick Diagramsminimize area
Eulers pathEXAMPLES
C
A B
X = C • (A + B)
B
A
C
i
j
j
V
DD X
X
i
GND
A B
C
PUN
PDN
A
B
C
Logic Graph
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Two Versions of C • (A + B)
X
C A B A B C
X
V
DD
GND
V
DD
GND
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Consistent Euler Path
j
V
DD X
X
i
GND
A B
C
A B C
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OAI22 Logic Graph
C
A B
X = (A+B)•(C+D)
B
A
D
V
DD X
X
GND
A B
C
PUN
PDN
C
D
D
A
B
C
D
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Example: x = ab+cd
GND
x
a
b
c
d
V
DD x
GND
x
a
b
c
d
V
DD x
(a) Logic graphs for (ab+cd)
(b) Euler Paths {a b c d}
a c d
x
V
DD
GND
(c) stick diagram for ordering {a b c d}
b
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MultiFingered Transistors
One finger
Two fingers (folded)
Less diffusion capacitance
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XOR CMOS Gate
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Properties of Complementary CMOS Gates
Snapshot
High noise margins :
V
OH
and V
OL
are at V
DD
and GND , respectively.
No static power consumption :
There never exists a direct path between V
DD
and
V
SS
( GND ) in steadystate mode .
Comparable rise and fall times:
(under appropriate sizing conditions)
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Combinational Circuits
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CMOS Properties
Full railtorail swing; high noise margins
Logic levels not dependent upon the relative
device sizes; ratioless
Always a path to Vdd or Gnd in steady state;
low output impedance
Extremely high input resistance; nearly zero
steadystate input current
No direct path steady state between power
and ground; no static power dissipation
Propagation delay function of load
capacitance and resistance of transistors
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Combinational Circuits
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Ratioed Logic
V
DD
V
SS
PDN
In
1
In
2
In
3
F
R
L
Load
Resistive
N transistors + Load
• V
OH
= V
DD
• V
OL
=
R
PN
R
PN
+ R
L
• Assymetrical response
• Static power consumption
•
• t
pL
= 0.69 R
L
C
L
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Active Loads
V
DD
V
SS
In
1
In
2
In
3
F
V
DD
V
SS
PDN
In
1
In
2
In
3
F
V
SS
PDN
Depletion
Load
PMOS
Load
depletion load NMOS pseudoNMOS
V
T
< 0
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Combinational Circuits
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PseudoNMOS
V
DD
A B C D
F
C
L
V
OH
= V
DD
(similar to complementary CMOS)
k
n
V
DD
V
Tn
–
( )
V
OL
V
OL
2
2
 –
\ .

 
k
p
2
 V
DD
V
Tp
–
( )
2
=
V
OL
V
DD
V
T
–
( )
1 1
k
p
k
n
 – – (assuming that V
T
V
Tn
V
Tp
) = = =
SMALLER AREA & LOAD BUT STATIC POWER DI SSI PATI ON!!!
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Combinational Circuits
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RATIOED LOGIC
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Improved Loads
V
DD
V
SS
PDN1
Out
V
DD
V
SS
PDN2
Out
A
A
B
B
M1 M2
Differential Cascode Voltage Switch Logic (DCVSL)
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DCVSL Example
B
A A
B
B B
Out
Out
XORNXOR gate
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Combinational Circuits
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Transistor Sizing
C
L
B
R
n
A
R
p
B
R
p
A
R
n
C
int
B
R
p
A
R
p
A
R
n
B
R
n
C
L
C
int
2
2
2 2
1
1
4
4
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Combinational Circuits
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Transistor Sizing a Complex
CMOS Gate
OUT = D + A • (B + C)
D
A
B C
D
A
B
C
1
2
2 2
4
4
8
8
6
3
6
6
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Combinational Circuits
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Switch Delay Model
A
R
eq
A
R
p
A
R
p
A
R
n
C
L
A
C
L
B
R
n
A
R
p
B
R
p
A
R
n
C
int
B
R
p
A
R
p
A
R
n
B
R
n
C
L
C
int
NAND2
INV
NOR2
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Combinational Circuits
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Input Pattern Effects on Delay
Delay is dependent on
the pattern of inputs
Low to high transition
both inputs go low
– delay is 0.69 R
p
/2 C
L
one input goes low
– delay is 0.69 R
p
C
L
High to low transition
both inputs go high
– delay is 0.69 2R
n
C
L
C
L
B
R
n
A
R
p
B
R
p
A
R
n
C
int
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Delay Dependence on Input Patterns
0.5
0
0.5
1
1.5
2
2.5
3
0 100 200 300 400
A=B=1÷0
A=1, B=1÷0
A=1 ÷0, B=1
time [ps]
V
o
l
t
a
g
e
[
V
]
Input Data
Pattern
Delay
(psec)
A=B=0÷1 67
A=1, B=0÷1 64
A= 0÷1, B=1 61
A=B=1÷0 45
A=1, B=1÷0 80
A= 1÷0, B=1 81
NMOS = 0.5µm/0.25 µm
PMOS = 0.75µm/0.25 µm
C
L
= 100 fF
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Combinational Circuits
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FanIn Considerations
D C B A
D
C
B
A
C
L
C
3
C
2
C
1
Distributed RC model
(Elmore delay)
t
pHL
= 0.69 R
eqn
(C
1
+2C
2
+3C
3
+4C
L
)
Propagation delay deteriorates
rapidly as a function of fanin –
quadratically in the worst case.
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Combinational Circuits
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t
p
as a Function of FanIn
t
pL
H
t
p
(
p
s
e
c
)
fanin
Gates with a
fanin
greater than
4 should be
avoided.
0
250
500
750
1000
1250
2 4 6 8 10 12 14 16
t
pH
L
quadratic
linear
t
p
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Combinational Circuits
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t
p
as a Function of FanOut
2 4 6 8 10 12 14 16
t
p
NOR2
t
p
(
p
s
e
c
)
eff. fanout
All gates
have the
same drive
current.
t
p
NAND2
t
p
INV
Slope is a
function of
“driving
strength”
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Combinational Circuits
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t
p
as a Function of FanIn and FanOut
Fanin: quadratic due to increasing
resistance and capacitance
Fanout: each additional fanout gate
adds two gate capacitances to C
L
t
p
= a
1
FI + a
2
FI
2
+ a
3
FO
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Combinational Circuits
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Fast Complex Gates:
Design Technique 1
Transistor sizing
as long as fanout capacitance dominates
Progressive sizing
In
N C
L
C
3
C
2
C
1
In
1
In
2
In
3
M1
M2
M3
MN
Distributed RC line
M1 > M2 > M3 > … > MN
(the FET closest to the
output is the smallest)
Can reduce delay by more than
20%; decreasing gains as
technology shrinks
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Combinational Circuits
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Fast Complex Gates:
Design Technique 2
Transistor ordering
C
2
C
1
In
1
In
2
In
3
M1
M2
M3
C
L
C
2
C
1
In
3
In
2
In
1
M1
M2
M3
C
L
critical path critical path
charged
1
0÷1
charged
charged
1
delay determined by time to
discharge C
L
, C
1
and C
2
delay determined by time to
discharge C
L
1
1
0÷1
charged
discharged
discharged
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Fast Complex Gates:
Design Technique 3
Alternative logic structures
F = ABCDEFGH
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Fast Complex Gates:
Design Technique 4
Isolating fanin from fanout using buffer
insertion
C
L
C
L
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Combinational Circuits
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Fast Complex Gates:
Design Technique 5
Reducing the voltage swing
linear reduction in delay
also reduces power consumption
But the following gate is much slower!
Or requires use of “sense amplifiers” on the
receiving end to restore the signal level
(memory design)
t
pHL
= 0.69 (3/4 (C
L
V
DD
)/ I
DSATn
)
= 0.69 (3/4 (C
L
V
swing
)/ I
DSATn
)
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Combinational Circuits
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PassTransistor
Logic
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PassTransistor Logic
I
n
p
u
t
s
Switch
Network
Out
Out
A
B
B
B
• N transistors
• No static consumption
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Combinational Circuits
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Threshold Drops
V
DD
V
DD
÷ 0 PDN
0 ÷ V
DD
C
L
C
L
PUN
V
DD
0 ÷ V
DD
 V
Tn
C
L
V
DD
V
DD
V
DD
÷ V
Tp

C
L
S
D S
D
V
GS
S
S D
D
V
GS
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Example: AND Gate
B
B
A
F = AB
0
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NMOSOnly Logic
V
DD
In
Out
x
0.5µm/0.25µm
0.5µm/ 0.25µm
1.5µm/ 0.25µm
0 0.5 1 1.5 2
0.0
1.0
2.0
3.0
Time [ns]
V
o
l
t
a
g
e
[
V
]
x
Out
In
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Combinational Circuits
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NMOSonly Switch
A = 2.5 V
B
C = 2.5 V
C
L
A = 2.5 V
C = 2.5 V
B
M
2
M
1
M
n
Threshold voltage loss causes
static power consumption
V
B
does not pull up to 2.5V, but 2.5V  V
TN
NMOS has higher threshold than PMOS (body effect)
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Combinational Circuits
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NMOS Only Logic:
Level Restoring Transistor
M
2
M
1
M
n
M
r
Out
A
B
V
DD
V
DD
Level Restorer
X
• Advantage: Full Swing
• Restorer adds capacitance, takes away pull down current at X
• Ratio problem
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Combinational Circuits
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Restorer Sizing
0 100 200 300 400 500
0.0
1.0
2.0
W / L
r
=1.0/0.25
W / L
r
=1.25/0.25
W / L
r
=1.50/0.25
W / L
r
=1.75/0.25
V
o
l
t
a
g
e
[
V
]
Time [ps]
3.0
•Upper limit on restorer size
•Passtransistor pulldown
can have several transistors in
stack
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Combinational Circuits
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Solution 2: Single Transistor Pass Gate with
V
T
=0
Out
V
DD
V
DD
2.5V
V
DD
0V
2.5V
0V
WATCH OUT FOR LEAKAGE CURRENTS
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Combinational Circuits
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Complementary Pass Transistor Logic
A
B
A
B
B B B B
A
B
A
B
F=AB
F=AB
F=A+B
F=A+B
B B
A
A
A
A
F=A©BÝ
F=A©BÝ
OR/NOR
EXOR/NEXOR AND/NAND
F
F
PassTransistor
Network
PassTransistor
Network
A
A
B
B
A
A
B
B
Inverse
(a)
(b)
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Combinational Circuits
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Solution 3: Transmission Gate
A
B
C
C
A B
C
C
B
C
L
C = 0 V
A = 2.5 V
C = 2.5 V
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Resistance of Transmission Gate
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DESIGNING USING TG
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Transmission Gate XOR
A
B
F
B
A
B
B
M1
M2
M3/M4
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Delay in Transmission Gate Networks
V
1 V
i1
C
2.5 2.5
0 0
V
i V
i+1
C
C
2.5
0
V
n1 V
n
C
C
2.5
0
In
V
1
V
i V
i+1
C
V
n1 V
n
C
C
In
R
eq
R
eq
R
eq
R
eq
C C
(a)
(b)
C
R
eq
R
eq
C C
R
eq
C C
R
eq
R
eq
C C
R
eq
C
In
m
(c)
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Delay Optimization
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Combinational Circuits
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Transmission Gate Full Adder
A
B
P
C
i
V
DD
A
A A
V
DD
C
i
A
P
A
B
V
DD
V
DD
C
i
C
i
C
o
S
C
i
P
P
P
P
P
Sum Generation
Carry Generation
Setup
Similar delays for sum and carry
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Combinational Circuits
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Dynamic Logic
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Combinational Circuits
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Dynamic CMOS
In static circuits at every point in time (except
when switching) the output is connected to
either GND or V
DD
via a low resistance path.
fanin of n requires 2n (n Ntype + n Ptype)
devices
Dynamic circuits rely on the temporary
storage of signal values on the capacitance of
high impedance nodes.
requires on n + 2 (n+1 Ntype + 1 Ptype)
transistors
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Dynamic Gate
In
1
In
2
PDN
In
3
M
e
M
p
Clk
Clk
Out
C
L
Out
Clk
Clk
A
B
C
M
p
M
e
Two phase operation
Precharge (Clk = 0)
Evaluate (Clk = 1)
on
off
1
off
on
((AB)+C)
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Combinational Circuits
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Conditions on Output
Once the output of a dynamic gate is
discharged, it cannot be charged again until
the next precharge operation.
Inputs to the gate can make at most one
transition during evaluation.
Output can be in the high impedance state
during and after evaluation (PDN off), state is
stored on C
L
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Combinational Circuits
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Properties of Dynamic Gates
Logic function is implemented by the PDN only
number of transistors is N + 2 (versus 2N for static complementary
CMOS)
Full swing outputs (V
OL
= GND and V
OH
= V
DD
)
Nonratioed  sizing of the devices does not affect
the logic levels
Faster switching speeds
reduced load capacitance due to lower input capacitance (C
in
)
reduced load capacitance due to smaller output loading (Cout)
no I
sc
, so all the current provided by PDN goes into discharging C
L
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Combinational Circuits
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Properties of Dynamic Gates
Overall power dissipation usually higher than static
CMOS
no static current path ever exists between V
DD
and GND
(including P
sc
)
no glitching
higher transition probabilities
extra load on Clk
PDN starts to work as soon as the input signals
exceed V
Tn
,
Needs a precharge/evaluate clock
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Combinational Circuits
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Issues in Dynamic Design 1:
Charge Leakage
C
L
Clk
Clk
Out
A
M
p
M
e
Leakage sources
CLK
V
Out
Precharge
Evaluate
Dominant component is subthreshold current
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Combinational Circuits
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Solution to Charge Leakage
C
L
Clk
Clk
M
e
M
p
A
B
Out
M
kp
Same approach as level restorer for passtransistor logic
Keeper
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Combinational Circuits
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Issues in Dynamic Design 2:
Charge Sharing
C
L
Clk
Clk
C
A
C
B
B=0
A
Out
M
p
M
e
Charge stored originally on
C
L
is redistributed (shared)
over C
L
and C
A
leading to
reduced robustness
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Combinational Circuits
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Charge Sharing Example
C
L
=50fF
Clk
Clk
A
A
B
B
B
!B
C
C
Out
C
a
=15fF
C
c
=15fF
C
b
=15fF
C
d
=10fF
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Combinational Circuits
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Charge Sharing
M
p
M
e
V
DD

Out

A
B = 0
C
L
C
a
C
b
M
a
M
b
X
C
L
V
DD
C
L
V
out
t
( )
C
a
V
DD
V
Tn
V
X
( )
–
( )
+ =
or
AV
out
V
out
t
( )
V
DD
–
C
a
C
L
 V
DD
V
Tn
V
X
( )
–
( )
– = =
AV
out
V
DD
C
a
C
a
C
L
+

\ .

 
– =
case 1) if AV
out
< V
Tn
case 2) if AV
out
> V
Tn
B
=
0
Clk
X
C
L
C
a
C
b
A
Out
M
p
M
a
V
DD
M
b
Clk
M
e
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Combinational Circuits
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Solution to Charge Redistribution
Clk
Clk
M
e
M
p
A
B
Out
M
kp
Clk
Precharge internal nodes using a clockdriven transistor
(at the cost of increased area and power)
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Issues in Dynamic Design 3:
Backgate Coupling
C
L1
Clk
Clk
B=0
A=0
Out1
M
p
M
e
Out2
C
L2
In
Dynamic NAND
Static NAND
=1
=0
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Backgate Coupling Effect
1
0
1
2
3
0 2 4 6
Time, ns
Clk
In
Out1
Out2
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Issues in Dynamic Design 4: Clock
Feedthrough
C
L
Clk
Clk
B
A
Out
M
p
M
e
Coupling between Out and
Clk input of the precharge
device due to the gate to
drain capacitance. So
voltage of Out can rise
above V
DD
. The fast rising
(and falling edges) of the
clock couple to Out.
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Clock Feedthrough
0.5
0.5
1.5
2.5
0 0.5 1
Clk
Clk
In
1
In
2
In
3
In
4
Out
In &
Clk
Out
Time, ns
Clock feedthrough
Clock feedthrough
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Other Effects
Capacitive coupling
Substrate coupling
Minority charge injection
Supply noise (ground bounce)
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Cascading Dynamic Gates
Clk
Clk
Out1
In
M
p
M
e
M
p
M
e
Clk
Clk
Out2
V
t
Clk
In
Out1
Out2
AV
V
Tn
Only 0 ÷ 1 transitions allowed at inputs!
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Domino Logic
In
1
In
2
PDN
In
3
M
e
M
p
Clk
Clk
Out1
In
4
PDN
In
5
M
e
M
p
Clk
Clk
Out2
M
kp
1 ÷ 1
1 ÷ 0
0 ÷ 0
0 ÷ 1
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Why Domino?
Clk
Clk
In
i
PDN
In
j
In
i
In
j
PDN
In
i
PDN
In
j
In
i
PDN
In
j
Like falling dominos!
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Properties of Domino Logic
Only noninverting logic can be implemented
Very high speed
static inverter can be skewed, only LH transition
Input capacitance reduced – smaller logical effort
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Designing with Domino Logic
M
p
M
e
V
DD
PDN
Clk
I n
1
I n
2
I n
3
Out1
Clk
M
p
M
e
V
DD
PDN
Clk
I n
4
Clk
Out2
M
r
V
DD
Inputs = 0
during precharge
Can be eliminated!
EE141
Combinational Circuits
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Footless Domino
The first gate in the chain needs a foot switch otherwise second stage
cannot precharge
Precharge is rippling – shortcircuit current
A solution is to delay the clock for each stage
V
DD
Clk M
p
Out
1
In
1
1 0
V
DD
Clk M
p
Out
2
In
2
V
DD
Clk M
p
Out
n
In
n
In
3
1 0
0 1 0 1 0 1
1 0 1 0
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Differential (Dual Rail) Domino
A
B
M
e
M
p
Clk
Clk
Out = AB
!A
!B
M
kp
Clk
Out = AB
M
kp
M
p
Solves the problem of noninverting logic
1 0
1 0
on
off
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Charge sharing problem
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Multiple output domino
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Compound domino
O1 = A B C, O2 = D E F and O3 = G H,
O = A B C D E F + GH.
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npCMOS
In
1
In
2
PDN
In
3
M
e
M
p
Clk
Clk
Out1
In
4
PUN
In
5
M
e
M
p
Clk
Clk
Out2
(to PDN)
1 ÷ 1
1 ÷ 0
0 ÷ 0
0 ÷ 1
Only 0 ÷ 1 transitions allowed at inputs of PDN
Only 1 ÷ 0 transitions allowed at inputs of PUN
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NORA Logic
In
1
In
2
PDN
In
3
M
e
M
p
Clk
Clk
Out1
In
4
PUN
In
5
M
e
M
p
Clk
Clk
Out2
(to PDN)
1 ÷ 1
1 ÷ 0
0 ÷ 0
0 ÷ 1
to other
PDN’s
to other
PUN’s
WARNING: Very sensitive to noise!
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