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Instruction Set Architecture

Isaac Hanson
FINF
Instruction Set Architecture (ISA)
 Instruction set architecture of a machine fills
the semantic gap between the user and the
machine.
 It also serves as the starting point for the
design of a new machine or modification of
an existing one.
 In this discussion we will look at the main
features of an instruction set architecture and
learn how to design one.
Topics for discussion
 Classification of ISA
 Memory addressing
 Operations in the instruction set
 Type and size of operands
 Encoding an instruction set
 Role of compilers

Prior knowledge assumed
 Instruction: Label Operator Operands
 Example: LOOP: MOVL R1,R2
 Interpretation: Move the contents of register R1
(source operand) to R2 (destination operand).
 Operands can be registers, memory or absolute
values (immediate).
 Instruction cycle: Fetch, Decode, Execute, Store
 Basic memory and register addressing
 Registers Program Counter (PC), Instruction
Register (IR)
High Level Language
Program
Assembly Language
Program
Compiler
lw $15, 0($2)
lw $16, 4($2)
sw $16, 0($2)
sw $15, 4($2)
temp = v[k];
v[k] = v[k+1];
v[k+1] = temp;
Machine Language
Program
Assembler
1000110001100010000000000000000
1000110011110010000000000000100
1010110011110010000000000000000
1010110001100010000000000000100
How to Speak to a Computer
Instruction
Fetch
Obtain instruction from program storage
Instruction
Decode
Determine required actions and instruction size
Operand
Fetch
Locate and obtain operand data
Execute
Compute result value or status
Result
Store
Deposit results in storage for later use
Next
Instruction
Determine successor instruction
The Instruction Execution Cycle
Instruction
Fetch
Obtain instruction from program storage
Instruction
Decode
Determine required actions and instruction size
Operand
Fetch
Locate and obtain operand data
Execute
Compute result value or status
Result
Store
Deposit results in storage for later use
Next
Instruction
Determine successor instruction
The Instruction Execution Cycle
 operations
 how many?
 which ones
 operands
 how many?
 location
 types
 how to specify?
 instruction format
 size
 how many formats?
y = x + b
operation
source operands
destination operand
(add r1, r2, r5)
Key ISA decisions
We will learn in this course how to make these decisions
Classifying ISA
 Stack architecture: Operands are implicit.
They are on the top of the stack. For
example, a binary operation, pops top two
elements of the stack, applies the operation
and pushes the result back on the stack.
 Accumulator architecture: One of the
operands is implicitly the accumulator.
Usually one of the source operand and the
destination operand is assumed to be the
accumulator.
Classifying ISA (Contd.)
 General purpose register architecture:
Operands are explicit : either memory
operands or register operands. Any
instruction can access memory. ISA design is
orthogonal.
 Load/store architecture: Only load /store
instructions can access memory. All other
instructions use register. Also called register-
register architecture.

Classifying ISA (Contd.) - Sample
code
STACK Accumulator GP Register Load/ Store
Push A Load A Load R1,A Load R1,A
Push B Add B Add R1,B Load R2,B
Add Store C Store C,R1 Add R3,R1,R2
Pop C Store C,R3
Cont’d………..
The Figure shows the code sequence for C=A+B for the fore classes of
Instruction sets. Note that the Add instruction has implicit operands for stack
and accumulator architecture, and explicit operands for register architecture.
It is assumed that A,B, and C all belong in memory and that the value of A
and B cannot be destroyed.
The figure shows typical combinations of memory operands and the total
operands per typical ALU instruction with examples of computers
Advantages and disadvantages of the three most common types of general-purpose
register computers
Memory Addressing
 ISA design must define how memory addresses are
interpreted and specified in the instructions.
 Most machines (ISAs) are byte addressed. That is, a
byte (8 bits) is the smallest memory size that has a
unique address. Other sizes are: half word, word,
double word...
 There are two different conventions for ordering bytes
within a word: Little Endian and Big Endian.
 Little Endian: The byte with address XXX…00 is the
least significant byte in the word.
 Big Endian: The byte with address XXX…00 is the most
significant byte in the word.
Cont’d….
Memory Addressing
 Independent of whether the architecture is register-
register or allows any operand to be a memory
reference, it must define how memory addresses
are interpreted and how the are specified
 The measurements presented here are largely, but
not completely independent
 In some cases the measurements are significantly
affected by the compiler technology.
Addressing modes
 Addressing mode was one of the ways designers attempted to close
the gap between HLL and the machine language. How? By providing
modes that a compiler can directly use to map many of the HLL
features such as array indexing, base register addressing, position
independent coding (PC-relative).
 Examples: Indexed mode array access, autoincrement and
autodecrement to allow processing of array elements in sequence and
so on.
 Some popular addressing modes: Register, Immediate, Displacement,
register-indirect, indexed, absolute, memory-indirect, autoincrement,
and autodecremement.
ADDRESSING MODES
Choice of addressing modes
 You can study the measurements related to usage
of the various addressing modes.
 For example, if the displacement mode is used, you
may further study the distribution of the how far the
displacement is.
 You may then select the modes depending on their
usage, and the specific attributes of the mode
depending on experimental result with a select set of
benchmarks.
 Displacement, register-deferred and immediate are
the popular ones among the architectures.
Addressing Modes
 An architecture addressing modes are the set of
syntaxes and methods that instructions use to
specify a memory address
 For operands or results
 As a target address for a branch instruction
 When a microprocessor accesses memory, to either
read or write data, it must specify the memory
address it needs to access
 Several addressing modes to generate this address
are known, a microprocessor instruction set
architecture may contain some or all of those
modes, deepening on its design
 In the following examples we will use the LDAC
instruction (loads data from a memory location into
the AC (accumulator) microprocessor register)
Direct mode
 Instruction includes the A memory address
 LDAC 5 – accesses memory location 5, reads the data
(10) and stores the data in the microprocessor‟s
accumulator
 This mode is usually used to load variables and operands
into the CPU
Address A Opcode
Instruction Memory
Operand
Indirect mode
 Starts like the direct mode, but it makes
an extra memory access. The address
specified in the instruction is not the
address of the operand, it is the address
of a memory location that contains the
address of the operand.
 LDAC @5 or LDAC (5), first retrieves the
content of memory location 5, say 10, and
then CPU goes to location 10, reads the
content (20) of that location and loads the
data into the CPU (used for relocatable
code and data by operating systems)
Address A Opcode
Instruction Memory
Pointer to operand
operand
Register direct mode
 It specifies a register instead a memory address
 LDAC R – if register R contains an value 5, then the value
5 is copied into the CPU‟s accumulator
 No memory access
 Very fast execution
 Very limited address space
Register Address R Opcode
Instruction
Registers
Operand
Register indirect mode
 LDAC @R or LDAC (R) – the register contains the
address of the operand in the memory
 Register R (selected by the operand), contains value 5
which represents the address of the operand in the
memory (10)
 One fewer memory access than indirect addressing
Register Address R Opcode
Instruction Memory
Operand
Registers
Pointer to
operand
Immediate mode
 The operand is not specifying an address, it
is the actual data to be used
 LDAC #5 loads actually value 5 into the
CPU‟s accumulator
 No memory reference to fetch data
 Fast, no memory access to bring the operand

Implicit addressing mode
 Doesn‟t explicitly specify an operand
 The instruction implicitly specifies the operand
because always applies to a specific register
 This is not used for load instructions
 As an example, consider an instruction CLAC, that
is clearing the content of the accumulator in a
processor and it is always referring to the
accumulator
 This mode is used also in CPUs that do use a
stack to store data; they don‟t specify an operand
because it is implicit that the operand must come
from the stack
Addressing Modes contd…
Summary of the usage of memory addressing mode
Displacement addressing mode
 Effective Address = A + (content of R)
 Address field hold two values
 A = base value
 R = register that holds displacement
 or vice versa

Register R
Opcode
Instruction
Memory
Operand
Pointer to
Operand
Registers
Address A
+
Displacement Mode
 The major question that arises for a
displacement-style addressing mode is that
of the range of displacements used.
 Based on the use of various displacement
sizes, a decision of what sizes to support can
be made.
 Choosing the displacement field sizes is
important because they directly affect the
instruction length

Immediate or Literal Addressing Mode
 Immediates can be used in arithmetic operations, operations, in
comparison (primarily for branches, and in moves where a
constant is wanted in a register
 The last case occurs for constants written in the code-which tend
to be small and for address constants, which tend to be large
 For the use of immediates it is important to know whether they
need to be supported for all operations or only a subset
 Another important instruction set measurement is the range of
values for immediate. Like displacement values, the size of
immediate values affects instruction length
Relative addressing mode
 It is a particular case of the displacement addressing, where the register
is the program counter; the supplied operand is an offset; Effective
Address = A + (PC)
 The offset is added to the content of the CPU‟s program counter register
to generate the required address
 The program counter contains the address of next instruction to be
executed, so the same relative instruction will produce different
addresses at different locations in the program
 Consider that the relative instruction LDAC $5 is located at memory
address 10 and it takes two memory locations; the next instruction is at
location 12, so the operand is actually located at (12 +5) 17; the
instruction loads the operand at address 17 and stores it in the CPU‟s
accumulator
 This mode is useful for short jumps and relocatable code

Indexed addressing mode
 Works like relative addressing mode; instead
adding the A to the content of program
counter (PC), the A is added to the content of
an index register
 If the index register contains value 10, then
the instruction LDAC 5(X) reads data from
memory at location (5+10) 15 and stores it in
the accumulator
 Good for accessing arrays
 Effective Address = A + IndexReg
 R++

Based addressing mode
 Works the same with indexed addressing
mode, except that the index register is
replaced by a base address register
 A holds displacement
 R holds pointer to base address
 R may be explicit or implicit
 e.g. segment registers in 80x86
Addressing Modes Summary
TYPES AND SIZES OF OPERANDS
 How is the type of an operand designated?
 Normally, encoding in the opcode designates the type of an
operand
 Desktop and Server:
 Integer, single-precision floating point(32 bits), character ….
 The type of operand effectively gives its size
 Common operands types include Character ( 8 bits, 16 bits or one
word)
 Floating point ( a word or double word)
 Character( 8 bits for ASCII or 16 bits for Unicode
 Integer in two‟s complement





Operations in the instruction set
 Data transfer instructions.
 Arithmetic and logic instructions.
 Instructions for control flow: conditional and
unconditional branches, jumps, procedure calls and
procedure returns.
 System calls.
 Floating point instructions.
 Decimal instructions.
 String instructions.
 Graphics instructions.
Operations in Instruction set
Instruction of flow control
 We can distinguish four different types of
control flow change:
 Conditional branches
 Jumps
 Procedure call
 Procedure returns

ENCODING AN INSTRUCTION SET
 When encoding the instructions, the number of registers and
the number of addressing modes both have a significant
impact on the size of instruction
 The architect must balance several competing forces when
encoding the instruction set
 The desire to have as many registers and addressing modes
as possible
 The impact of the size of the register and addressing mode
fields on the average instruction size and hence on the
average program size
 A desire to have instructions encoded into lengths that will be
easy to handle in a pipeline implementation


Cont’d…..
 What to do…..
 Operator of the instruction is encoded into opcode.
 When there are large number of addressing modes and more
than one memory operands are allowed in an instruction, each
operand must have an address specifier.
 Otherwise if it is like the load/store machine, the operands can
be encoded along with the opcode itself.
 The number of addressing modes and number of registers have
a significant effect on instruction length. why?
 Finally, you would like the length of the instruction to be integral
number of words.
Variations in instruction encoding
 Variable: Can support any number of operands. Number of
operands is a part of the opcode. Each operand has address
specifier. Example: VAX (1 - 53 bytes)
 Fixed: Fixed format always has the same number of operands. How
they are decoded may differ with opcode. Example: SPARC, MIPS,
PowerPC. (For SPARC - 4 bytes)
 Hybrid: Multiple formats of fixed length. Format specified as a part
of the opcode. EX: IBM 370, Intel 80X86 series. (Intel 7 different
formats of 1 - 5 bytes)
 See Figure 2.17
The role of compilers
High-level

Front-end
Optimization
Global Optimizer
Code Generator
Transform HLL to common
intermediate form
Procedure inlining and
loop transformations
Global and local opt
and register allocation
machine dependent opt.
The role of compilers (contd.)
 Front-end: One per language. Once the
source code is transformed into a common
intermediate code, the rest of the phases are
the same for any HLL.
 High level optimization involves working on
the source code. Example: inline expansion
of function.
 Local optimization: Within a sequence of
code. The straight line section of the code.
The role of compilers (contd.)
 Global Optimization: Extend local
optimization across branches and introduce a
set of transformations aimed at optimizing
loops. “Loop optimization”
 Register allocation: is a very important
function. Recent register allocation
techniques are based on graph coloring.
 Machine-dependent optimizations exploits
some architectural features.
Compiler technology and ISA
 Today‟s compiler technology (in the form of
optimization and others) helps in making
such architectures as load/store a viable
solution.
 AS a ISA designer, one may help the
compiler writer generate efficient code. How?
What are the features in ISA that can help
compilation?
ISA features to support efficient
compiler /code
 Regularity: Three components of instruction set : operation, data
types and addressing modes - should be orthogonal.
 Two aspects of an architecture are said to be orthogonal if they
are independent of each other.
 Example: VAX „s arithmetic operations are equally applicable to
register or memory operands.
 Provide primitives and not solutions: Features that match a
particular HLL feature are often not usable by other HLL or other
statements. Example: Index register to support arrays. Instead a
general purpose register would serve the purpose and other
situations well.
ISA features...
 Simplify trade-off among alternatives: A
HLL statement may be translated into several
different equivalent set of instructions.
 Which is better? The longer or shorter sequence?
With cache and pipelining this tradeoff becomes
complex.
 Example: In register-memory architecture, how
many times a memory variable has be referenced
before it can be moved into a register?
ISA features … (contd.)
 Provide instructions that bind quantities
known at compile time as constants - If
something is known at compile time resolve it at
compile time.
 Counter Example: CALLS of VAX architecture.
 CALLS is procedure call in VAX „s ISA. Even though
the list of registers to be saved on transfer control to
the procedure is known at compile-time, the register
saving process is included in the semantics of
CALLS! So cannot be substituted with instruction at
compile-time.
Summarizing the ISA features
1) Decide the general class of ISA.
2) How is the memory going to be addressed?
3) What are the addressing modes?
4) What are the allowed operations?
5) The type of operands?
6) How are you going to encode the
instructions?
7) Add features that will help compiler generate
efficient code.