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Lecture 5: IC Fabrication
The Transistor Revolution
First transistor
Bell Labs, 1948
© Rabaey: Digital Integrated Circuits
2nd
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Lecture 5: IC Fabrication
The First Integrated Circuits
Bipolar logic
1960’s
ECL 3-input Gate
Motorola 1966
© Rabaey: Digital Integrated Circuits
2nd
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Lecture 5: IC Fabrication
Intel 4004 Micro-Processor
1971
1000 transistors
1 MHz operation
© Rabaey: Digital Integrated Circuits
2nd
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Lecture 5: IC Fabrication
Moore’s Law
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Electronics, April 19, 1965.
© Rabaey: Digital Integrated Circuits
2nd
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Lecture 5: IC Fabrication
Silicon IC processing
 Similar to photographic printing
 Expose the silicon wafer through a mask
 Process the silicon wafer
 Repeat sequentially to pattern all the layers
 Layout: A set of masks that tell a fabricator what to
pattern
 For each layer in your circuit
 Layers are metal, drain/source implants, gate, etc.
 You draw the layers
 Subject to vendor-supplied spacing rules
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Lecture 5: IC Fabrication
The wafer
 Czochralski process
 Melt silicon at 1425 °C
 Add impurities (dopants)
 Spin and pull crystal
 Slice into wafers
 0.25mm to 1.0mm thick
 Polish one side
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Lecture 5: IC Fabrication
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Lecture 5: IC Fabrication
Crystal and wafer
Wand
(a finished 250lb crystal)
A polished wafer
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Lecture 5: IC Fabrication
4X reticle
Wafer
The mask
 Illuminate reticle on wafer
 Typically 4× reduction
 Typical image is 25×25mm
 Limited by focus
 Step-and repeat across wafer
 Limited by mechanical
alignment



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Lecture 5: IC Fabrication
Reference: FULLMAN KINETICS
Lithography
 Patterning is done by exposing photoresist with light
 Requires many steps per “layer”

 Example: Implant layer
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Lecture 5: IC Fabrication
Grow Oxide Layer
Reference: FULLMAN KINETICS
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Lecture 5: IC Fabrication
Reference: FULLMAN KINETICS
Add Photoresist
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Lecture 5: IC Fabrication
Reference: FULLMAN KINETICS
Mask
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Lecture 5: IC Fabrication
Reference: FULLMAN KINETICS
Animation
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Lecture 5: IC Fabrication
Reference: FULLMAN KINETICS
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Lecture 5: IC Fabrication
Reference: FULLMAN KINETICS
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Lecture 5: IC Fabrication
Reference: FULLMAN KINETICS
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Lecture 5: IC Fabrication
Reference: FULLMAN KINETICS
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Lecture 5: IC Fabrication
9/03 IEEE spectrum
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Lecture 5: IC Fabrication
Patterning
 How we pattern and
expose the resist
 To make the patterns
we want on the silicon
IEEE Spectrum, 7/99, p. 41
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Lecture 5: IC Fabrication
9/03 IEEE spectrum
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Lecture 5: IC Fabrication
Detailed process sequence

1. Grow epi layer
 Ultra-pure single-crystal
silicon


2. Implant n-well
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Lecture 5: IC Fabrication
Detailed process sequence (con’t)

3. Define active area


4. Grow field oxide
 For isolation
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Lecture 5: IC Fabrication
Detailed process sequence (con’t)



5. Grow gate oxide


6. Pattern polysilicon
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Lecture 5: IC Fabrication
Detailed process sequence (con’t)

7. Form pFETs


8. Form nFETs
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Lecture 5: IC Fabrication
Detailed process sequence (con’t)

9. Deposit LTO by CVD
 LTO is low-temperature
oxide
 CVD is chemical vapor
deposition

10. Deposit Metal1
 Usually aluminum
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Lecture 5: IC Fabrication
Detailed process sequence (con’t)
11. Via definition
 Deposit LTO
 Make via cuts

12. Deposit Metal2
 Usually aluminum

13. Overglass (not shown)
 Coat entire chip with Si
3
N
4
 Make pad openings in Si
3
N
4
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Lecture 5: IC Fabrication
An inverter
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Lecture 5: IC Fabrication
Figure courtesy
Yan Borodovsky,
Intel
A Pentium cutaway
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Lecture 5: IC Fabrication
National 0.18µm process cutaway
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Lecture 5: IC Fabrication
Advanced Metallization - Copper
Copper versus Aluminum
~ 40% lower resistivity
~ 10× less electromigration
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Lecture 5: IC Fabrication
Interconnect Impact on Chip

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Lecture 5: IC Fabrication
10 100 1,000 10,000 100,000
Length (u)
N
o

o
f

n
e
t
s
(
L
o
g

S
c
a
l
e
)
Pentium Pro (R)
Pentium(R) II
Pentium (MMX)
Pentium (R)
Pentium (R) II
Nature of Interconnect
Local Interconnect
Global Interconnect
S
Local
= S
Technology
S
Global
= S
Die
S
o
u
r
c
e
:

I
n
t
e
l

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Lecture 5: IC Fabrication
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Lecture 5: IC Fabrication
Permittivity
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Lecture 5: IC Fabrication
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Lecture 5: IC Fabrication
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Lecture 5: IC Fabrication
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Lecture 5: IC Fabrication
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Lecture 5: IC Fabrication
Projections
Simulated distribution of dopant
atoms in a 0.05 m nFET
red: acceptor atom
blue: donor atom
All figures from IEEE Spectrum, 7/99
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Lecture 5: IC Fabrication
An AMD 50nm transistor
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Lecture 5: IC Fabrication
Frequency
P6
Pentium ® proc
486
386
286
8086
8085
8080
8008
4004
0.1
1
10
100
1000
10000
1970 1980 1990 2000 2010
Year
F
r
e
q
u
e
n
c
y

(
M
h
z
)

Lead Microprocessors frequency doubles every 2 years
Doubles every
2 years
Courtesy, Intel
© Rabaey: Digital Integrated Circuits
2nd
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Lecture 5: IC Fabrication
Power Dissipation
P6
Pentium ® proc
486
386
286
8086
8085
8080
8008
4004
0.1
1
10
100
1971 1974 1978 1985 1992 2000
Year
P
o
w
e
r

(
W
a
t
t
s
)

Lead Microprocessors power continues to increase
Courtesy, Intel
© Rabaey: Digital Integrated Circuits
2nd
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Lecture 5: IC Fabrication
Power density
4004
8008
8080
8085
8086
286
386
486
Pentium® proc
P6
1
10
100
1000
10000
1970 1980 1990 2000 2010
Year
P
o
w
e
r

D
e
n
s
i
t
y

(
W
/
c
m
2
)

Hot Plate
Nuclear
Reactor
Rocket
Nozzle
Power density too high to keep junctions at low temp
Courtesy, Intel
© Rabaey: Digital Integrated Circuits
2nd
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Lecture 5: IC Fabrication
Productivity Trends
1
10
100
1,000
10,000
100,000
1,000,000
10,000,000
2
0
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3

1
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3

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10
100
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
Logic Tr./Chip
Tr./Staff Month.
x
x x
x
x x
x
21%/Yr. compound
Productivity growth rate
x
58%/Yr. compounded
Complexity growth rate
10,000
1,000
100
10
1
0.1
0.01
0.001
L
o
g
i
c

T
r
a
n
s
i
s
t
o
r

p
e
r

C
h
i
p

(
M
)

0.01
0.1
1
10
100
1,000
10,000
100,000
P
r
o
d
u
c
t
i
v
i
t
y

(
K
)

T
r
a
n
s
.
/
S
t
a
f
f

-

M
o
.

Source: Sematech
Complexity outpaces design productivity
C
o
m
p
l
e
x
i
t
y

Courtesy, ITRS Roadmap
© Rabaey: Digital Integrated Circuits
2nd
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Lecture 5: IC Fabrication
Cost of Integrated Circuits
 NRE (non-recurrent engineering) costs
 design time and effort, mask generation
 one-time cost factor
 Recurrent costs
 silicon processing, packaging, test
 proportional to volume
 proportional to chip area
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Lecture 5: IC Fabrication
NRE Cost is Increasing
© Rabaey: Digital Integrated Circuits
2nd
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Lecture 5: IC Fabrication
Die Cost
Single die
Wafer
From http://www.amd.com
Going up to 12” (30cm)
© Rabaey: Digital Integrated Circuits
2nd