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Flag & MSW

MSW:

Pins of 80286 • COD/INTA#: Distinguishes instruction fetch cycles from memory data read cycles. Also distinguishes Interrupt acknowledgement cycles from I/O cycles. COD/INTA# M/IO# S1# S0# Bus cycle 1 1 0 1 Instruction Fetch 0 1 0 1 MEMR 0 1 1 0 MEMW 1 0 0 1 IOR 1 0 1 0 IOW 0 0 0 0 INTA X X 1 1 Invalid .

Pins of 80286 (Contd.) • CAP: A 12V capacitor must be connected between this pin and ground. This is to filter the output of the internal substrate bias generator. • PEACK#: Processor extension acknowledge output pin is used to give acknowledgement to the device like co-processor that the processor is fetching the data requested by it. .. • PREQ: Processor extension request input pin is used by the device like co-processor to place a request for fetching the data required for execution.

.Pins of 80286 (Contd. A low value on BUSY# indicates that the co-processor is busy in execution and the 80286 must wait until a high value appears on it. . A value on ERROR# indicate that the co-processor has encountered an error during execution.) • BUSY# and ERROR#: These are input pins used to indicate the present operating condition of the device like co-processor.

80286 Memory Interface in Protected Mode .

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Descriptor Format 63 47 INTEL Reserved P DPL S E ED/C R/W A 48 Base (B23-B16) 32 31 Base (B15-B0) 16 15 Limit (L15-L0) 0 .

offset must be <limit ED=1 Grow-down segment. offset>limit 41 Writable (W) W=0 Data segment may not be written to W=1 Data segment may be written to 43 Executable (E) E=1 Code segment descriptor 42 Confirming (C) C=0 Privilege level of code segment is ignored C=1 Privilege level of code segment is observed 41 Readable (R) R=0 Code segment may not be read R=1 Code segment may be read 40 Accessed (A) A=0 Segment has not been accessed A=1 Segment has been accessed 46-45 Type Field Definition E 48 .63 INTEL Reserved 47 P DPL S ED/C R/W A Base (B23-B16) 32 31 Base (B15-B0) 16 15 Limit (L15-L0) 0 Bit Position 47 Name Function Present (P) P=1 Segment in mapped into physical memory P=0 No mapping to physical memory exists Descriptor privilege Level (DPL) Segment privilege attribute used in privilege tests 44 Segment Descriptor (S) S=0 System segment descriptor S=1 Code or Data segment descriptor 43 Executable (E) E=0 Data segment descriptor 42 Expansion Direction (ED) ED=0 Grow-up segment.

Address Translation Registers Hidden Part Descriptor Registers (Loaded by CPU) Visible Part 15 0 Selector 47 CS- 40 39 16 15 0 Access Rights Base Limit Selector DS- Access Rights Base Limit Selector ES- Access Rights Base Limit Selector SS- Access Rights Base Limit Access Rights Base Limit LDTR .

Segment Register / LDTR 16-bit selector Address Translation Registers 16-bit offset GDTR 13-bit Index TI LDTR 2-bit RPL X8 24 Bits 24 Bits Base Base Base TI = 0 Descriptors TI = 1 Descriptors OR + Base Base Base Base 64 Bits 24-Bit Base Address GDTR Base Base GDT 64 Bits LDT + Physical Address 24-Bit Base 16-Bit Limit 16-Bit Selector .

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BP. CX. DX. PUSHA Pushes all the GP Registers of 80286 on to the stack in the following order AX. MEM and executes the following algorithm: if (REG < [MEM]) or (REG > [MEM+sizeof(REG)]) then INT 5 exception will be raised [mem] denotes the contents of the memory location mem and sizeof(reg) is two if the register is 16 bits wide. . SP. DI The value of SP is the value before actual push of SP. SI. BX.Instructions BOUND BOUND REG.

AX CLTS Clears the Task Switched Flag in the Machine Status Register. SI. BX. POPA Pops the top 8 words off the stack into GP Registers in the following order DI. CX.Instructions Contd. DX.. This is a privileged operation and is generally used only by operating system code. SP. BP. LGDT Loads a value from an operand into the Global Descriptor Table (GDT) register LLDT Loads a value from an operand into the Local Descriptor Table Register (LDTR) .

the Zero Flag is set. If the segment is writable.Instructions Contd. otherwise it is cleared. VERW Verifies the specified segment selector is valid and is writable at the current privilege level.. SLDT Stores the Local Descriptor Table (LDT) Register into the specified operand SGDT Stores the Global Descriptor Table (GDT) Register into the specified operand VERR Verifies the specified segment selector is valid and is readable at the current privilege level. . the Zero Flag is set. If the segment is readable. otherwise it is cleared.

The VERR AX instruction tests the descriptor selected by the AX register VERW (Verify Write access) Verifies the specified segment selector is valid and is writable at the current privilege level. If the segment is writable. This instruction is used to prevent the CPU from accessing memory that may be temporarily in use by the coprocessor. ESC Provides access to the data bus for other resident processors. otherwise it is cleared.Instructions Contd… WAIT CPU enters wait state until the coprocessor signals it has finished its operation. otherwise it is cleared. the Zero Flag is set. The VERW AX instruction tests the descriptor selected by the AX register . VERR (Verify Read access) Verifies the specified segment selector is valid and is readable at the current privilege level. the Zero Flag is set. If the segment is readable.

Instructions Contd… LAR (Load Access Rights) LAR instruction reads the segment descriptor and places a copy of the access rights byte into 16-bit register. BX instruction loads AX with the access rights byte from the descriptor selected by the selector value found in BX register. MOV BX. CS LSL AX. This instruction is used to get the access rights so that it can be checked before a program uses the segment of memory described by the descriptor. BX The LSL AX. BX The LAR AX. CS LAR AX. . MOV BX. BX instruction loads AX with the segment limit from the descriptor selected by the selector value found in BX register. LSL (Load Segment Limit) LSL instruction loads the specified register with the segment limit of the descriptor.

80386 Features • • • • • • • • Multitasking Memory Management Software protection Large Memory system 4GB addressing capacity & 64TB Virtual Memory Virtual Memory with or without Paging Modes: Real. Protected and Virtual 8086 80386 can switch between Protected and Real modes without resetting • 8086/80186/80286 programs are upward compatible to the 80386 .

33 and 40 MHz  Queue: 6 Byte . 16. 20.80386 Variants 80386 DX 80386 SX  Full-version  132-pin PGA (Pin Grid Array)  Data bus – 32 Bit  Address bus – 32 Bit  Addressing capacity: 4GB  Clock: 12. 25 and 33 MHz  Queue: 16 Byte  Reduced bus version  100-pin FP (Flat Pin)  Data bus – 16 Bit  Address bus – 24 Bit  Addressing capacity: 16MB  Clock: 25.

80386 DX Architecture .

80386 Pin Description 2X CLOCK CLK2 Address Bus A2-A31 BE3# 32-Bit Data D0-D31 32-Bit Address BE2# Data Bus BE1# Byte Enables BE0# Bus Control ADS# NA# BS16# READY# W/R# 80386 D/C# M/IO# Bus Cycle Definition LOCK# Bus Arbitration HOLD HLDA PEREQ BUSY# ERROR# Co-Processor Signals INTR Interrupts NMI RESET Vcc GND Power Connections .

80386 Memory system Bank 3 Bank 2 Bank 1 1G X 8 1G X 8 1G X 8 Bank 0 1G X 8 16 Bits 16 Bits 32 Bits .

80386 Registers .

Segment Descriptor Bit Position 63 Base (B31-B24) 47 E D / C P DPL S E G R / W D A 0 A V L Limit (L19-L16) Base (B23-B16) 48 32 31 Base (B15-B0) 16 15 Limit (L15-L0) 0 Name Function 52 Available (AVL) Available field for user or OS 53 0 Bit must be zero (0) for compatibility with future processors 54 Default operation size (D) (Recognized in Code segment descriptors only) D=0 16-Bit segment D=1 32-Bit segment 55 Granularity (G) G=0 Segment length is Byte granular G=1 Segment length is page granular .

DS 16-bit selector 32-bit offset SI Addressed Data + 15 DS Index 0 TI 63 4 Other Bits RPL GDT OR LDT 0 8-Bit Access Rights 32-Bit Base 20-Bit Limit Hidden part of segment register Segment Base X8 Physical Memory Descriptor (Loaded into Hidden part of segment register) + 80386 Physical Address Computation GDTR Base Descriptor Table Base OR LDTR Base Physical Memory .

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Paging mechanism Selector Index TI RPL Offset Index / Pointer Register 32 13 4K Page X8 Access Rights & Other Bits Limit + GDTR / LDTR + Linear Address Paging Mechanism (optional) 4K Page Physical Address Page Frame Address 4K Page 4K Page Base address Segment Descriptor from GDT / LDT 4K Page 4K Page .

210) With the base information of page frame obtained from an entry in page table and lower 12 bits of the linear address. of tables (no. of page tables = 4 KB X 210 X 210 = 4 GB . the desired information can be obtained from 4KB page frame. of pages = 4 KB X no. The memory required for address translation = Memory for page directory + Memory for page tables = 4 KB + 4 MB The physical memory with paging mechanism = size of each page X no. the memory required for each table is 4KB and the memory required for storing all such tables will 4 MB.PAGING Contd… 31 Linear Address from Segment Unit 12 11 22 21 Directory Table 0 Offset 12 10 10 + + CR0 CR1 Page Frame + Page Table (n) CR2 CR3 Page Directory Since each page table has 1024 entries each of size 4 Bytes. of entries in each page table (210) X no. of entries per page table X no. as detailed below Memory for page tables = size of each entry in page table (4 Bytes) X no. of entries in page directory.

Being integrated on-chip allows it to execute math instructions about 3 times faster than that in 80386-387 combination. .80486 Processor • • • • • It is a 32-bit processor It has 32-bit Data and 32-bit Address buses It is available in two versions SX & DX It’s queue is 32-byte It has on-chip 8 KB Data and Instruction Cache (SRAM) • It has on-chip improved MMU used for paging and Virtual memory management • It has on-chip FPU (Floating Point Unit) or Math coprocessor (only in DX version).

Parity (even) is generated by 486 for each byte data during memory write operations. the same in 386 needs 2 clock cycles. . The frequency can be varied dynamically from max. • It has internal parity generator/detector. thus data integrity is maintained. or vice-versa.80486 Features Contd… • It is frequency scalable when it is operated in 2X clock mode. The frequency change doesn’t affect register content of CPU. back to min. • Tightly coupled pipelining allows 486 to complete execution in one clock cycle.

80486 DX Architecture .

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• Data cache: 8KB & Instruction cache: 8KB • Branch prediction logic allows efficient execution of programs • Two modes of operation: Real & Protected . Address bus: 32 Bit • It has Superscalar Architecture (1 Floating point processor and 2 integer processors (U & V)). • Fast Numeric coprocessor. 5 times faster than 80486 numeric coprocessor • Dual integer processor (U & V) that often allows 2 instructions per clock.PENTIUM • Data bus: 64 Bit.

Architecture of PENTIUM .

it contains a 256KB or 512KB Level 2 cache • 4 more address lines (total 36) gives Pentium Pro to access 64GB of directly addressable space. .PENTIUM PRO • • • • It is an improved version of Pentium It is a faster than Pentium It employs Faster floating point unit It’s modified architecture can schedule up to 5 instructions for execution • In addition to 8KB Data cache & 8KB Instruction cache (Level 1).

Pentium Pro Processor External Bus System 256K or 512K Level 2 Cache Bus Interface Unit (BIU) Level 1 8K Instruction Cache Fetch & Decode Unit Level 1 8K Data Cache Dispatch & Execution Unit Retire Unit Instruction pool Pentium Pro Architecture Fetch & Decode Unit .

PENTIUM PRO Processor External Bus System Instruction Pool 256K or 512K Level 2 Cache Bus Interface Unit (BIU) Level 1 8K Instruction Cache Reservation Station (RS) Integer Unit (U Pipe) Floating Point Unit Level 1 8K Data Cache Integer Unit (V Pipe) Address generation unit Jump Unit Dispatch & Execution Unit Fetch & Decode Unit Dispatch & Execution Unit Retire Unit Instruction pool Pentium Pro Architecture Address generation unit .

microarchitecture techniques such as  Pipelining (8086 onwards)  Caches (80486 onwards)  Branch Prediction Logic (Pentium onwards)  Superscalar Execution (Pentium onwards)  Out-of-order Execution (Pentium Pro onwards) were used .Processor performance • To improve processor performance / utilization.

Hyper-Threading Technology .

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Hyperthreading .Multithreading .