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Jitter on leading
edge 0.86 psec
Start
Reference Clock
Stop
500pS
Tw
Receiver
TAC
1/4
Driver
11-bit ADC
PMT
2 Ghz PLL
REF_CLK
4x1Ghz PLL
Receiver
Stretcher
1/4
Driver
11-bit Counter
PMT
CK5Ghz
2 Ghz PLL
REF_CLK
50ns
100ns
150ns
200ns
250ns
300ns
Primary Goal:
To build 2-Ghz VCO, key module of PLL that generates the TDC reference
signal
Cycle-to-Cycle Time-jitter < 1 ps
To evaluate IHP SG25H1/M4M5 Technology for our applications
To gain experiences on using Cadence tools (Virtuoso Analog Environment)
Circuit Design (VSE)
Simulation (Spectre)
Chip Layout (VLE, XLE, VCAR)
DRC and LVS Check (Diva, Assura, Calibre)
Parasitic Extraction (Diva)
Post Layout Simulation (Spectre)
GDSII Stream out
Validation
Tape Out
Fref
CP
I1
PD
Uc
LF
VCO
F0
I2
1
N
Temperature: 27C-55C
Supply:
VDD=2.5V
VControl
Best
Temperature: 27C
Supply:
VDD=2.5V
@100KHz offset
Best
Typical
Worst
-89.94 dBc/Hz
-89.58 dBc/Hz
-89.90 dBc/Hz
(1)
T=27C
f0 = 2 GHz
phase noise:
dBc/Hz@100K offset
Vcontrol
(V)
Itail
(mA)
Vpp
(mV)
Icc
(mA)
Pw
(mW)
Phase
Noise
Best
1.54
10.90
635
33.92 85.0
-89.75
Typical
1.60
8.83
573
27.63 67.5
-89.54
Worst
1.68
7.48
524
22.31 56.0
-89.18
dBc/Hz@100K offset
Vcontrol
(V)
Itail
(mA)
Vpp
(mV)
Icc
(mA)
Pw
(mW)
Phase
Noise
Best
1.56
10.50
628
34.48
86.3
-89.15
Typical
1.64
8.63
571
28.05
70.0
-88.72
Worst
1.70
7.38
521
22.57
56.5
-88.56
Analog_extracted
Schematic
Post Layout
Post Layout
Schematic
Vcontrol
27C
55C
-89.40 dBc/Hz
(Sch: -89.75)
-88.90 dBc/Hz
(Sch: -89.15)
Conclusion
(1) VCO time-jitter met our requirement.
(2) Post layout simulation matched
schematic simulation very well.
(3) Some problems we have encountered
with pcell library, layout, DRC, LVS and
auto-routing functionalities.
(4) Ready for October Submission.