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FET

Prepared by Nidhi Patel

Advantages of FET over BJT


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Unipolar device i. e. operation depends on only


one type of charge carriers (h or e)
Voltage controlled Device (gate voltage controls
drain current)
Very high input impedance (109-1012 )
Source and drain are interchangeable in most
Low-frequency applications
Low Voltage Low Current Operation is possible
(Low-power consumption)
Less Noisy as Compared to BJT
No minority carrier storage (Turn off is faster)
Very small in size, occupies very small space in
ICs

FET construction
major part of the structure is the n-type material that forms the
channel between the embedded layers of p-type material
The n-type channel is connected through an ohmic contacts
drain (D) and source (S)
The two p-type materials are connected together and to the
gate (G) terminal
In the absence of any applied potentials the JFET has two p-n
junctions under no-bias conditions

Working of FET

Water analogy of FET

JFET in the VGS = 0 V and VDS > 0 V.

Varying reverse-bias potentials across the p-n


junction of an n-channel JFET.

Characteristic of FET

Pinch-off (VGS = 0 V, VDS = VP)

ID versus VDS for VGS = 0 V

Regions in FET

VGS < 0

Break down regions for VGS < 0

Transfer characteristics

Working of FET

FET small signal model low frequency

iD= f(VGS,VDS)

id = gm vgs+ (1/rd)vds

1/rd = drain conductance

Gate current is zero hence G to S


junction is represented as open circuit
and no current is drawn from FET, the
reason is i/p resistance is very high
o/p resistance is rd
Small signal model for sinusoidal i/p
of FET consider RMS values of Vgs, Vds
and Id

FET small signal model high frequency

Since Cds is small compared to Cgs, the drain-source


capacitance may be ignored in most analysis and design
situations

FET fixed biasing

If the resistance rd is sufficiently large


(at least 10;1) compared to RD,

AC equivalent ckt

FET self bias

VDD

AC equivalent ckt

FET voltage divider bias

AC equivalent ckt

MOSFET

Figure:nChannelEnhancementMOSFETshowingchannellengthLandchannelwidthW.

Depletion-type MOSFET.

n-Channel depletion-type MOSFET with


VGS = 0V and an applied voltage VDD.

Symbols for
(a) n-channel depletion-type MOSFETs
and
(b) p-channel depletion-type
MOSFETs.

Drain and transfer characteristics for an nchannel depletion-type MOSFET

ENHANCEMENT-TYPE MOSFET

n-Channel enhancement-type MOSFET.

Channel formation in the n-channel


enhancement type MOSFET

Change in channel and depletion


region with increasing level of VDS
for a fixed value of VGS

Drain and transfer characteristics of an nchannel enhancement-type MOSFET

Symbols for
(a)n-channel enhancement-type
MOSFETs and (b) p-channel
enhancement-type MOSFETs

CD amplifier

AC equivalent ckt

FET Mid-frequency Analysis:

VDD

A common source (CS) amplifier is shown


to the right.

RD
R1

ii

+
vs

Rs

+
vs

short the DC supply voltage (superposition)


replace the FET with the hybrid- model
The resulting mid-frequency circuit is shown below.
is

Ci

R2
RSS

io

vi = v

gmv

rd

RD

RL

vo
_

_
mid-frequency CE amplifier circuit

Analysis of the CS mid-frequency circuit above yields:


A vi =

vo
= -g m R 'L , where R L' = rd R D R L
vi

A vs =

Zi =

vi
= R Th , where R Th = R 1 R 2
ii

AI =

Zo =

vo
io

AP =

= rd R D
seen by R L

vo
Zi
= A vi

vs
R s + Zi

io
= A vi
ii

+
RL

Co

vi

+
RTh

io
D

ii

The mid-frequency circuit is drawn as follows:


the coupling capacitors (Ci and Co) and the
bypass capacitor (CSS) are short circuits

VDD

Zi

R L

po
= A vi A I
pi

CSS

vo
_

VDD

FET Amplifier Configurations and


Relationships:

VDD

RD
R1

io
D

ii
Rs

vs

Ci

RL
R2

vi

CS

Co

C SS

RSS

vo
_

_
Common Source (CS) Amplifier
ii
Rs

S
+

RD

RSS

RL

R1

A vi

-g m R

R 'L

rd R D R L

Zi

R Th

Zo

rd R D

io

G
vi

C2

R2

vo
_

VCC

A vs
Common Gate (CG) Amplifier

VDD

AI

VDD

R1

AP

ii
+
vs
_

Rs

+
vi

'
L

g mR

CD
g m R 'L
1 g m R 'L

'
L

rd R D R L
R SS

R SS R L

1
gm

R Th

Co

Ci

+
vs

CG

Ci

Co

R2
R SS

_
Common Drain (CD) Amplifier (also called source follower)

Zi

R
+
Z
i
s
Z
A vi i
R L

Zi
A vi

R
+
s

Zi
Z

A vi i
R L

A vi A I

A vi A I

A vi

R SS

A vi

1
gm

Z i

R s + Zi
Zi
RL

A vi

A vi A I

where R Th = R 1 R 2

io

rd R D

+
RL

vo
_

Note: The biasing circuit is the same for each amp.