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ASIC DESIGN FOR LOW

POWER APPLICATIONS
Represented by
B.Nethra
11k41a04c5

May 18, 2004

MS Defense: Uppalapati

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Talk Outline
 Motivation
 Background
 Prior

Work
 Proposed Design Flow
 Results
 Conclusion and Future Work

May 18, 2004

MS Defense: Uppalapati

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2004 MS Defense: Uppalapati 3 .Motivation  Increasing gate count + increasing clock frequency = increasing POWER  Portable equipment runs on battery  Power consumption due to glitches can be 30 – 70% May 18.

2004 1980 P6 Pentium® 486 1990 Year 2000 MS Defense: Uppalapati 2010 4 .Motivation: Chip Power Density Source: Intel Sun’s Surface Power Density (W/cm2) 10000 Rocket Nozzle 1000 Nuclear Reactor 100 8086 Hot Plate 10 4004 8008 8085 386 286 8080 1 1970 May 18.

2004 MS Defense: Uppalapati 5 .Motivation (cont’d…)  Present day Application Specific Integrated Circuit (ASIC) chips employ standard cell based design style • A quick way to design circuits with millions of gates  Existing glitch reduction techniques demand gate re-design: not suitable for a cell-based design May 18.

Problem Statement  To devise a glitch suppressing methodology after the technology mapping phase • • Without requiring cell redesign Without violating circuit delay constraints May 18. 2004 MS Defense: Uppalapati Design Entry Technology Mapping Layout 6 .

Talk Progress  Motivation  Background  Prior Work  Proposed Design Flow  Results  Conclusion and Future Work May 18. 2004 MS Defense: Uppalapati 7 .

.. VLSI Design ’97] Reduced constraint set linear program [Raja et al.Prior Work  Existing glitch reduction techniques • • •  Low power design by hazard filtering [Agrawal. PATMOS ’01] Cell selection [Zhang et al. 2004 MS Defense: Uppalapati 8 .. VLSI Design ’03] CMOS circuit design for minimum dynamic power and highest speed [Raja et.. VLSI Design ’04] Optimization of cell based design • • Cell library optimization [Masgonty et al. DAC ’01)] May 18. al.

Agrawal.  Re-design all gates in the circuit for inertial delay > differential delay  3 2 Filtering Effect of a gate May 18.Prior Work: Hazard Filtering Reference: V. D. “Low Power Design by Hazard Filtering”. VLSI Design 1997 Glitch is suppressed when the inertial delay of gate exceeds the differential input delays. 2004 MS Defense: Uppalapati 9 .

Prior Work: Cell Library Optimization Reference: J. PATMOS ‘01   Limited logic functions with greater cell sizing can result in 20 . Arm and P. M. 2004 MS Defense: Uppalapati 10 . Cserveny. “Low-Power LowVoltage Standard Cell Libraries with a Limited Number of Cells”.25% savings in power Transistor sizing for • •   Multiple driving strength Balanced rise and fall times Power optimized by minimizing parasitic capacitances Limitations: • • Discrete set of varieties Optimization of cells cannot be circuit-specific May 18. D. Masgonty. Pfister. C. S.

Zhang. “Cell Selection from Technology Libraries for Minimizing Power”. DAC ‘01     Mixed Integer Linear Program (MILP) to select from different realizations of cells such that power consumption is minimized without violating delay constraints • Sum of dynamic and leakage power is minimized • • Supply voltages Threshold voltages A set of variables for each cell to support different • Sizes Achieved 79% power saving on an average Limitation: depends on diversity of the cell library May 18. Z.Prior Work: Cell Selection Reference: Y. 2004 MS Defense: Uppalapati 11 . Hu and D. Chen. X.

Talk Progress  Motivation  Background  Prior Work  Proposed Design Flow  Results  Conclusion and Future Work May 18. 2004 MS Defense: Uppalapati 12 .

New Glitch Removing Solution  Balanced the differential delays at cell inputs: • Using delay elements called Resistive Feedthrough cells  Automated the delay element • Generation • Insertion into the circuit May 18. 2004 MS Defense: Uppalapati 13 .

Proposed Design Flow Modified linear program  Resistive feed though cell generation:  • Fully automated • Scalable to large ICs  Layout generation of modified netlist • Can use any place-and-route tool May 18. Mapping Remove Glitches Layout 14 . 2004 MS Defense: Uppalapati Design Entry Tech.

First Attempt – Did not work: Modified Linear Program  Changes from Raja’s linear program: • •    Gate delays – constants Wire delays – only variables Constrained solution space Large number of buffers inserted Buffers consume power • may exceed the power saved May 18. 2004 Circuit # gates # bufs 4-bit ALU 90 36 c432 240 120 C499 618 396 C880 383 217 C1355 546 414 C2670 1193 162 MS Defense: Uppalapati 15 .

RC Delay Model   Used to find the resistance value for a given delay Delay depends on load capacitance •   Number of fan-outs R Vin SPECTRE simulations done for varying R and CL values CL is varied in steps of transistor pairs May 18. 2004 MS Defense: Uppalapati CL 16 .

2004 MS Defense: Uppalapati 17 .RC Delay Model (cont’d…)  CL varies during transition •   Model not perfectly linear Measured data stored as a 3D lookup table Average of signal rise and fall delays TP = TPLH + TPHL 2  Linear interpolation between two points May 18.

Detailed Design Flow Design Entry Find delays from LP Tech. Mapping Find resistor values from lookup table Remove Glitches Generate feed through cells and modify netlist Layout May 18. 2004 MS Defense: Uppalapati 18 .

2004 MS Defense: Uppalapati 19 .Experimental Procedure  Extract cell delays from initial layout •  LP solver: CPLEX in AMPL •  C program to generate the input files Physical design of feed through cells and insertion of fictitious buffers •  SPECTRE simulation PERL script Place-and-Route • Silicon Ensemble from Cadence May 18.

2004 MS Defense: Uppalapati 20 .Power Estimation  Logic level • Event-driven delay simulator to count the • transitions Power α # transitions × # fanouts  Post layout • SPECTRE simulator to measure current • through the power rail Average power calculated by integration May 18.

2004 MS Defense: Uppalapati 21 .THANK YOU May 18.