You are on page 1of 26

High Speed Sigma-delta

ADC for CMOS Image


Sensor
Rohish Kumar Reddy Mitta(r0224923)
Promoter - Georges Gielen
Supervisor -Thai Ha Le

Outline
Introduction to CMOS image sensors
Types of A/D converters
Incremental converter
Incremental ADC
Need for MASH structure for high order consideration

Introduction to CMOS image sensors


The

[canon]
Courtesy:el Gamal ,cmos image sensors

The pixel readout circuit


There are two basic types of pixel read out sensors which
are being used
o 4T read out
o 3T read out

El gamal ,CMOS sensors

4T read out
The basic 4T pixel architecture
consists
A pinned diode configuration
A reset transistor
A transfer gate to move
charge from the photodiode to
the floating diffusion sense
node
A source follower transistor
A row select transistor

wikipedia

3T read out

wikipedia

3-T APS pixel includes


a reset transistor
a source follower transistor to
isolate the sense node from the
large column bus capacitance
a row select transistor
The current source component of
the follower amplifier is shared by a
column of pixels.
Readout is performed one row at a
time. Each row of pixels is reset
after it is read out to the column
capacitors
via the row access transistors and
column amplifiers.

4T is most commonly used pixel configuration


The pixel uses CDS (Correlated Double Sampling)
A method to measure electrical values such as voltages or
currents that allows removing an undesired offset. It is
used often when measuring sensor outputs.
The output of the sensor is measured twice: once in a
known condition and once in an unknown condition. The
value measured from the known condition is then
subtracted from the unknown condition to generate a value
with a known relation to the physical quantity being
measured.

Why we need CDS for the image sensors


Read out circuit of the image sensors

El gamal

ADC Types
There are many variations of ADCs which can be brought
down to
o Single Sampling e.g., Flash ADC ,SAR ADC
o Multiple Sampling e.g., Oversampling ADC like ADC

The signal form the Image sensor are basically


DC in nature and the adc must operate for the
near DC signal for the conversion

Single Sampling ADC

Single sampling ADC


FLASH ADC

SAR ADC

wikipedia

Single Sampled ADC cannot be used for high


resolution
The Single sampled adc uses a lot of Passive component
which cannot be integrated into IC with perfect matching .
The imperfections in the passives will give erroneous
signal giving out wrong outputs
Since the passives are used a lot there is going to be a lot
of noise induced by the passives

Multiple sampling ADC


Sigma Delta A/D converters are the typical examples of the
oversampling ADCs.

wikipedia
RESET

Signal

Incremental Sigma Delta ADC

Incremental Sigma Delta ADC


The advantages of incremental sigma delta ADC over
conventional adc
o After every N sample conversion the ADC is reset thus
eliminating the errors and noise induced by previous
computation in the integrator.
o The noise in the system is reduced by resetting the ADC.
o This reduction in the noise and offset reduces the
requirement of high resolution ADC quantizer.
o This configuration helps in reducing dependency in
temperature variations and process variation during
fabrication .
o Thus they can always be used for column ADCs which are
commonly used in image sensors

Incremental Sigma delta


There are two types of incremental sigma delta
configuration
o Feedback
o Feedforward

Considering the multiple order Sigma Delta ADC

Feedback Incremental Sigma Delta ADC

The Quantizer signal is complete dependent on the value of the V2.

FeedForward Architecture

The Quantizer output is the culmination of the output of every integrator.

Designing the digital filter


The resolution of the adc depends on the

Computing more samples


More orders

The 2 order ADC output at second integrator

The input

-VrefV2Vref

-Vin+
Thus by this inference the resolution increases by the
implementation .

To increase the resolution of the ADC


The resolution of the adc architecture increases by
o
o

Increasing the number of samples


Increasing the order of the ADC

Thus we come to introduce the MASH architecture for the


design of high resolution adc

The MASH architecture

d1

DAC

d1

DAC

Problems with MASH ADC


Mismatch in the analog loops and the digital loop
matching.
A different analysis is required in assigning the constants
for the stability of the system
SMASH(sturdy MASH) architecture is required

Conclusion
The incremental sigma delta adc architecture was studied.
Have to look into deep understanding of MASH and
SMASH adc at the Digital filtering end so that the
mismatching can be removed and looked into for designing
a high resolution fast adc for image sensor application.

Thank you