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Sequential Logic

SEQUENTIAL LOGIC

Memory Elements

Latches: S-R Latch, D Latch

Flip-flops: S-R flip-flop, D flip-flop, J-K flip-flops, T flip-flops

Asynchronous Inputs

Finite State Machines

Memory

Memory Unit

Read/Write Operations

Memory Arrays

2011 Sem 1

Sequential Logic

INTRODUCTION (1/2)

Combinational

Sequential

Combinational Circuit

Sequential Circuit

Each output depends on both

present inputs and state.

on the immediate (present)

inputs.

inputs : :

Combinational

Logic

::

outputs

inputs : :

Combinational

Logic

::

outputs

Memory

2011 Sem 1

Sequential Logic

INTRODUCTION (2/2)

Synchronous: outputs change only at specific time

Asynchronous: outputs change at any time

Bistable (2 stable states)

Monostable or one-shot (1 stable state)

Astable (no stable state)

Latches and flip-flops.

They differ in the methods used for changing their state.

2011 Sem 1

Sequential Logic

indefinitely, or change value on command from its inputs.

Memory

element

command

stored value

Characteristic table:

2011 Sem 1

Command

(at time t)

Q(t)

Q(t+1)

Set

Reset

Memorise /

No Change

0

1

0

1

Sequential Logic

Q(t+1) or Q+: next state

Memory

element

command

clock

Positive pulses

Positive edges

2011 Sem 1

stored value

the clock frequency (or rate) is 1/x

Hz. For example, a 2 GHz PC has

a clock period of 0.5 nanosecond.

Clock period

Negative edges

Sequential Logic

Memory

element

command

clock

Positive pulses

Positive edges

2011 Sem 1

stored value

about 3 x 108 metres per second.

In half a nanosecond, light travels

15 cm.

Clock period

Negative edges

Sequential Logic

Pulse-triggered

Edge-triggered

Pulse-triggered

Latches

ON = 1, OFF = 0

Positive pulses

Positive edges

Negative edges

Edge-triggered

Flip-flops

Positive edge-triggered (ON = from 0 to 1; OFF = other time)

Negative edge-triggered (ON = from 1 to 0; OFF = other time)

2011 Sem 1

Sequential Logic

Next state depends on current state and inputs

Many computations can be specified as FSMs

Example: counter

2011 Sem 1

Sequential Logic

ELEMENTS OF A FSM

A finite

set of states

Zero or more of the states are FINAL state

States are related to one another by state

transitions

A finite

set of inputs

A finite set of outputs

2011 Sem 1

Sequential Logic

10

EXAMPLE

Final State

Input

Retire

State

Leave == 0

Death

Graduate

er

ov

Age == 6

n

tio

ca

Va

Ag

e

re

Bo

==

65

Start State

Heart attack

Bored

Born

2011 Sem 1

Education

Work

Sequential Logic

Play

State Transition

11

Move / B

Release / C

Press / A

A:

X = current_mouse_position();

B:

X = current_mouse_position();

Draw line from X to Y;

C:

12

NSlite: When this signal is asserted, the light on the north-south road is

green; when this signal is deasserted the light on the north-south road is

red.

EWlite: When this signal is asserted, the light on the east-west road is

green; when this signal is deasserted the light on the east-west road is

red.

NScar: Indicates that a car is over the detector placed in the roadbed in

front of the light on the north-south road (going north or south).

EWcar: Indicates that a car is over the detector placed in the roadbed in

front of the light on the east-west road (going east or west).

The traffic light should change from one direction to the other only if

a car is waiting to go in the other direction; otherwise, the light

should continue to show green in the same direction as the last car

that crossed the intersection.

2011 Sem 1

Sequential Logic

13

STATE DIAGRAM

Two states:

2011 Sem 1

Sequential Logic

14

Memory elements

2011 Sem 1

Sequential Logic

15

Two complementary outputs: Q and Q'.

When Q = HIGH, we say latch is in SET state.

When Q = LOW, we say latch is in RESET state.

For active-high input S-R latch (also known as NOR gate latch)

S = HIGH and R = LOW Q becomes HIGH (SET state)

Both R and S are LOW No change in output Q

Both R and S are HIGH Outputs Q and Q' are both LOW

(invalid!)

2011 Sem 1

Sequential Logic

16

10100 R

Q 11000

10001 S

Q' 0 0 1 1 0

S

1

0

0

0

1

R

0

0

1

0

1

Q Q'

1 0

initial

1 0 (afer S=1, R=0)

0 1

0 1 (after S=0, R=1)

0 0

invalid!

Block diagram:

2011 Sem 1

Q'

Sequential Logic

17

S

Q'

NC

NC

1

0

1

0

1

1

1

0

0

0

1

0

S R

0

0

1

1

2011 Sem 1

0

1

0

1

No change. Latch

remained in present state.

Latch SET.

Latch RESET.

Invalid condition.

Q'

Q(t+1)

No change

Q(t)

0

Reset

1

Set

indeterminate

Sequential Logic

Q(t+1) = S + R' Q

S R = 0

18

S-R latch.

S

EN

EN

Q'

Q'

2011 Sem 1

Sequential Logic

19

the S-R latch.

EN

EN

Q'

2011 Sem 1

Sequential Logic

Q'

20

When EN is high,

D = HIGH latch is SET

D = LOW latch is RESET

Characteristic table:

2011 Sem 1

Sequential Logic

21

FLIP-FLOPS (1/2)

devices.

called the clock.

negative (falling) edge of the clock signal.

Clock signal

Positive edges

2011 Sem 1

Negative edges

Sequential Logic

22

FLIP-FLOPS (2/2)

S

C

R

C

Q'

C

Q'

Q'

S

C

R

C

Q'

C

Q'

Q'

2011 Sem 1

Sequential Logic

23

S-R FLIP-FLOP

S = HIGH and R = LOW Q becomes HIGH (SET state)

Both R and S are LOW No change in output Q

Both R and S are HIGH Invalid!

S

C

R

Q'

CLK

Q(t+1)

Comments

0

0

1

1

0

1

0

1

Q(t)

0

1

?

No change

Reset

Set

Invalid

= clock transition LOW to HIGH

2011 Sem 1

Sequential Logic

24

S-R FLIP-FLOP

CLK

SET

RESET

Q

2011 Sem 1

Sequential Logic

25

D FLIP-FLOP

clock pulse,

D = HIGH Q becomes HIGH (SET state)

D = LOW Q becomes LOW (RESET state)

D

CLK

CLK

Q(t+1)

Q'

1

0

1

0

C

R

formed with an S-R flip-flop.

2011 Sem 1

Comments

Set

Reset

Sequential Logic

26

D FLIP-FLOP

CLK

2011 Sem 1

Sequential Logic

27

D FLIP-FLOP vs D LATCH

CLK for FF

Connect to EN for latch

D

Q for

D-flip-flop

Enabled!

Q for

D-latch

2011 Sem 1

Sequential Logic

28

D FLIP-FLOP

To transfer logic-circuit outputs X, Y, Z to flip-flops Q1, Q2 and

Q3 for storage.

D

CLK

X

Combinational

logic circuit

CLK

D

Transfer

CLK

Q1 = X*

Q'

Q

Q2 = Y*

Q'

Q

Q3 = Z*

Q'

2011 Sem 1

Sequential Logic

29

NAND gates.

No invalid state.

K = HIGH and J = LOW Q becomes LOW (RESET state)

Both J and K are LOW No change in output Q

Both J and K are HIGH Toggle

2011 Sem 1

Sequential Logic

30

J

Q

Pulse

transition

detector

CLK

Q'

Characteristic table:

J

CLK

Q(t+1)

Comments

0

0

1

1

0

1

0

1

Q(t)

0

1

Q(t)'

No change

Reset

Set

Toggle

2011 Sem 1

Sequential Logic

J K

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

Q(t+1)

0

0

1

1

1

0

1

0

31

Positive edge detection

2011 Sem 1

Sequential Logic

32

Positive edge detection

2011 Sem 1

Sequential Logic

33

T FLIP-FLOP

tying both inputs together.

T

Pulse

transition

detector

CLK

CLK

Q'

Q'

Characteristic table:

T

CLK

Q(t+1)

Comments

0

1

Q(t)

Q(t)'

No change

Toggle

Q T

0

0

1

1

0

1

0

1

Q(t+1)

0

1

1

0

2011 Sem 1

Sequential Logic

34

Frequency Divider

CLK

Frequency = f

CLK

Q

Frequency = f / 2

2011 Sem 1

Sequential Logic

35

Frequency Divider

What

2011 Sem 1

Sequential Logic

36

A 4 bit counter

A BCD

CLK

CLK is at frequency f: 1010101010101010101010101010101010

D is at frequency f/2: 110011001100110011001100110011001111

C is at frequency f/4: 111100001111000011110000111100001111

B is at frequency f/8: 1111111100000000111111110000000011111111

A is at frequency f/16: 11111111111111110000000000000000

Recall our truth table! Count down

2011 Sem 1

Sequential Logic

37

2011 Sem 1

Sequential Logic

ABCD

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

38

2011 Sem 1

Sequential Logic

ABCD

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

39

2011 Sem 1

Sequential Logic

ABCD

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

40

cycle

2011 Sem 1

Sequential Logic

ABCD

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

41

Decimal counter

cycle

the previous cycle

2011 Sem 1

Sequential Logic

ABCD

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

0000

0001

0010

0011

0100

0111

42

A

B

CLK

Frequency = f

CLK

Frequency = f / 3

A

B

2011 Sem 1

Sequential Logic

43

sequential logic

Output

Synchronous

2011 Sem 1

counters

Sequential Logic

45

Step 1: Formulate the problem either as a truth table or a finite state machine

Present State

Next State

2011 Sem 1

Sequential Logic

46

Will

current state bits

3 JK flip-flops for A, B, and C, respectively

2011 Sem 1

Sequential Logic

47

inputs

Q

Present State

Next State

J K

0 0

0 0

0KB1

0 1

X

1 0

1 X0

1 01

1 1

0

1

0

1

0

1

0

1

Q(t+1)

JA

KA

JB

2011 Sem 1

Sequential Logic

JC

0

0

1

1

1

0

1

0

1

X

1

X

KC

X

1

X

1

48

Step 3: K-map

A

BC

00 01 11

10

BC

00 01 11

10

JA = BC

BC

KA = BC

00 01 11

10

00 01 11

10

JB = C

2011 Sem 1

BC

KB = C

Sequential Logic

49

BC

00 01 11

10

BC

10

JC = 1

2011 Sem 1

00 01 11

KC = 1

Sequential Logic

50

2011 Sem 1

Sequential Logic

51

Present State

Q T

Next State

TA

TB

TC

2011 Sem 1

Sequential Logic

0

0

1

1

0

1

0

1

Q(t+1)

0

1

1

0

52

A

BC

00 01 11

10

BC

00 01 11

10

TB = C

TA = BC

A

BC

00 01 11

10

TC = 1

2011 Sem 1

Sequential Logic

53

A

CLK

CLK

CLK

CLK

2011 Sem 1

Sequential Logic

54

Output

the current state

Most

2011 Sem 1

Sequential Logic

55

0

1

states

2011 Sem 1

Sequential Logic

56

Present

State

Input

Next

State

JA

KA

JB

KB

2011 Sem 1

Sequential Logic

J K

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

Q(t+1)

0

0

1

1

1

0

1

0

57

Step 3: K-map

A

BX

00 01 11

10

BX

00 01 11

JA = B

BX

KA = BX

00 01 11

10

BX

00 01 11

10

JB = X

2011 Sem 1

10

KB = AX + AX

=A X

Sequential Logic

58

IMPLEMENTATION OF FSM

CLK

CLK

K

CLK

2011 Sem 1

Sequential Logic

59

these inputs are transferred to the flip-flops output only on the

triggered edge of the clock pulse.

independent of the clock; example: preset (PRE) and clear

(CLR) [or direct set (SD) and direct reset (RD)].

are LOW.

2011 Sem 1

Sequential Logic

60

asynchronous inputs.

PRE

PRE

J

CLK

Q'

Q

Pulse

transition

detector

Q'

CLR

CLR

CLK

PRE

CLR

J = K = HIGH

2011 Sem 1

Preset

Sequential Logic

Toggle

Clear

61

METASTABILITY (1/3)

In reality, nothing is instantaneous. Critical timing parameters must be observed.

CLOCK

tco

DATA

ts setup time

th hold time

tco clock to output time

(propagation delay)

OUTPUT

ts

2011 Sem 1

th

Sequential Logic

62

METASTABILITY (2/3)

If setup and hold times are violated, flip-flop may

oscillate in an indeterminate state between 0

and 1

This is called metastability

Introduces error in the circuits operation

Cannot be absolutely avoided in practice

Use flip-flop chain

2011 Sem 1

Sequential Logic

63

METASTABILITY (3/3)

Input

Output

CLK

zero (but never zero) as the number of flip-flops

connected in series is increased.

2011 Sem 1

Sequential Logic

64

TRI-STATE MULTIPLEXERS

High-impedance means the circuit

is not connected

A tri-state buffer:

When enabled, connects input to

output

When disabled disconnects input

from output by entering a highimpedance state

2011 Sem 1

Sequential Logic

65

Definitions:

1 byte = 8 bits

1 word: in multiple of bytes, a unit of transfer between main

memory and registers, usually size of register.

1 KB (kilo-bytes) = 210 bytes; 1 MB (mega-bytes) = 220 bytes;

1 GB (giga-bytes) = 230 bytes; 1 TB (tera-bytes) = 240 bytes.

cost, non-volatile.

properties.

2011 Sem 1

Sequential Logic

66

Memory hierarchy

Fast, expensive

(small numbers),

volatile

registers

main memory

disk storage

magnetic tapes

2011 Sem 1

Sequential Logic

Slow, cheap

(large numbers),

non-volatile

67

A register file is a circuit with several registers, and

selection lines to choose on which register to operate

next

Operations: read and write

Features:

- Fast

- Simple addressing

- Multiported

(multiple reads and writes

concurrently)

2011 Sem 1

Sequential Logic

68

WR

Write data

CLK

CLK

CLK

CLK

Register

Number

4-bit register

Decoder

Read data

2011 Sem 1

Sequential Logic

69

MEMORY (1/2)

Data transfer

Processor

Up to 2k

addressable

locations.

Address

MAR

Memory

0

1

2

3

4

5

MDR

Control lines

(R/W, etc.)

2011 Sem 1

Sequential Logic

70

MEMORY (2/2)

A memory unit stores binary information in groups of bits

called words.

lines provide the information to be stored (written) into

the memory, while data output lines carry the information

out (read) from the memory.

(among the 2k words available) to be selected for reading

or writing.

a single control line Read/Write) specifies the direction of

transfer of the data.

2011 Sem 1

Sequential Logic

71

MEMORY UNIT

n data

input lines

n

k address lines

Memory unit

2k words

n bits per word

Read/Write

n

n data

output lines

2011 Sem 1

Sequential Logic

72

READ/WRITE OPERATIONS

Write operation:

Transfers the address of the desired word to the address lines.

Transfers the data bits (the word) to be stored in memory to the

data input lines.

Activates the Write control line (set Read/Write to 0).

Read operation:

Transfers the address of the desired word to the address lines.

Activates the Read control line (set Read/Write to 1).

Memory Enable Read/Write

Memory Operation

0

X

None

1

0

Write to selected word

1

1

Read from selected word

2011 Sem 1

Sequential Logic

73

MEMORY CELL

Static RAMs use flip-flops as the memory cells.

Dynamic RAMs use capacitor charges to represent data. Though simpler in

circuitry, they have to be constantly refreshed.

A single memory cell of the static RAM has the following logic and

block diagrams:

Select

Select

R

Input

Output

BC

Output

Read/Write

Read/Write

Logic diagram

2011 Sem 1

Input

Block diagram

Sequential Logic

74

Logic construction

of a 43 RAM (with

decoder and OR

gates):

2011 Sem 1

Sequential Logic

75

combined to form larger memory.

RAM 1K x 8

Input data 8

Address 10

Chip select

Read/write

DATA (8)

ADRS (10)

CS

RW

(8)

Output data

2011 Sem 1

Sequential Logic

76

Address

Lines

11 10

Lines

09

Input data

8 lines

DATA (8)

(8)

ADRS (10)

CS

1K x 8

RW

2x4

decoder

S0

S1

0

1

2

3

1024 2047

DATA (8)

(8)

ADRS (10)

CS

1K x 8

RW

2048 3071

Read/write

01023

DATA (8)

(8)

ADRS (10)

CS

1K x 8

RW

4K 8 RAM.

3072 4095

DATA (8)

(8)

ADRS (10)

CS

1K x 8

RW

2011 Sem 1

Sequential Logic

Output

data

77

A0

A1

21bit

addresses

19bitinternalchipaddress

A19

A20

2bit

decoder

512K x 8

memory chip

19-bit

address

512kX8

memorychip

8-bit data

input/output

Chip select

2011 Sem 1

D3124

D2316

D 158

D70

2M 32 memory module

Using 512K 8 memory chips.

Sequential Logic

78

END

2011 Sem 1

Sequential Logic

79

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