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# CS2100 Computer Organisation

Sequential Logic

SEQUENTIAL LOGIC

Memory Elements
Latches: S-R Latch, D Latch
Flip-flops: S-R flip-flop, D flip-flop, J-K flip-flops, T flip-flops
Asynchronous Inputs
Finite State Machines
Memory
Memory Unit
Memory Arrays

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Sequential Logic

INTRODUCTION (1/2)

## Two classes of logic circuits

Combinational
Sequential

Combinational Circuit

Sequential Circuit
Each output depends on both
present inputs and state.

## Each output depends entirely

on the immediate (present)
inputs.
inputs : :

Combinational
Logic

::

outputs

inputs : :

Combinational
Logic

::

outputs

Memory

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INTRODUCTION (2/2)

## Two types of sequential circuits:

Synchronous: outputs change only at specific time
Asynchronous: outputs change at any time

## Multivibrator: a class of sequential circuits

Bistable (2 stable states)
Monostable or one-shot (1 stable state)
Astable (no stable state)

## Bistable logic devices

Latches and flip-flops.
They differ in the methods used for changing their state.

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Sequential Logic

## Memory element: a device which can remember value

indefinitely, or change value on command from its inputs.
Memory
element

command

stored value

Characteristic table:

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Command
(at time t)

Q(t)

Q(t+1)

Set

Reset

Memorise /
No Change

0
1

0
1

Sequential Logic

## Q(t) or Q: current state

Q(t+1) or Q+: next state

Memory
element

command

clock

Positive pulses

Positive edges
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stored value

## If clock period is x seconds, then

the clock frequency (or rate) is 1/x
Hz. For example, a 2 GHz PC has
a clock period of 0.5 nanosecond.
Clock period

Negative edges

Sequential Logic

Memory
element

command

clock

Positive pulses

Positive edges
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stored value

## The speed of light in vacuum is

about 3 x 108 metres per second.
In half a nanosecond, light travels
15 cm.
Clock period

Negative edges

Sequential Logic

## Two types of triggering/activation

Pulse-triggered
Edge-triggered

Pulse-triggered
Latches
ON = 1, OFF = 0

Positive pulses

Positive edges

Negative edges

Edge-triggered
Flip-flops
Positive edge-triggered (ON = from 0 to 1; OFF = other time)
Negative edge-triggered (ON = from 1 to 0; OFF = other time)

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## Built with combinational logic and memory (stores the state)

Next state depends on current state and inputs
Many computations can be specified as FSMs
Example: counter

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ELEMENTS OF A FSM
A finite

set of states

## One of the state is a special START state

Zero or more of the states are FINAL state
States are related to one another by state
transitions
A finite

set of inputs
A finite set of outputs
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EXAMPLE
Final State

Input
Retire

State

Leave == 0

Death

er
ov

Age == 6

n
tio
ca
Va

Ag
e

re
Bo

==
65

Start State

Heart attack

Bored

Born

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Education

Work

Sequential Logic

Play

State Transition

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## FSM control for rubber banding

Move / B

Release / C

Press / A

A:

X = current_mouse_position();

B:

X = current_mouse_position();
Draw line from X to Y;

C:

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## Two output signals:

NSlite: When this signal is asserted, the light on the north-south road is
green; when this signal is deasserted the light on the north-south road is
red.
EWlite: When this signal is asserted, the light on the east-west road is
green; when this signal is deasserted the light on the east-west road is
red.

## Two inputs: NScar and EWcar.

NScar: Indicates that a car is over the detector placed in the roadbed in
front of the light on the north-south road (going north or south).
EWcar: Indicates that a car is over the detector placed in the roadbed in
front of the light on the east-west road (going east or west).

The traffic light should change from one direction to the other only if
a car is waiting to go in the other direction; otherwise, the light
should continue to show green in the same direction as the last car
that crossed the intersection.

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STATE DIAGRAM
Two states:

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Memory elements

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## Two inputs: S and R.

Two complementary outputs: Q and Q'.
When Q = HIGH, we say latch is in SET state.
When Q = LOW, we say latch is in RESET state.

For active-high input S-R latch (also known as NOR gate latch)

## R = HIGH and S = LOW Q becomes LOW (RESET state)

S = HIGH and R = LOW Q becomes HIGH (SET state)
Both R and S are LOW No change in output Q
Both R and S are HIGH Outputs Q and Q' are both LOW
(invalid!)

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## Active-high input S-R latch:

10100 R

Q 11000

10001 S

Q' 0 0 1 1 0

S
1
0
0
0
1

R
0
0
1
0
1

Q Q'
1 0
initial
1 0 (afer S=1, R=0)
0 1
0 1 (after S=0, R=1)
0 0
invalid!

Block diagram:

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Q'

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## Characteristic table for active-high input S-R latch:

S

Q'

NC

NC

1
0
1

0
1
1

1
0
0

0
1
0

S R
0
0
1
1

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0
1
0
1

No change. Latch
remained in present state.
Latch SET.
Latch RESET.
Invalid condition.

Q'

Q(t+1)
No change
Q(t)
0
Reset
1
Set
indeterminate

Sequential Logic

Q(t+1) = S + R' Q
S R = 0

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S-R latch.
S

EN

EN

Q'

Q'

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the S-R latch.

EN

EN

Q'

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Q'

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## GATED D LATCH (2/2)

When EN is high,
D = HIGH latch is SET
D = LOW latch is RESET

## Hence when EN is high, Q follows the D (data) input.

Characteristic table:

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FLIP-FLOPS (1/2)

devices.

## Output changes state at a specified point on a triggering input

called the clock.

## Change state either at the positive (rising) edge, or at the

negative (falling) edge of the clock signal.
Clock signal
Positive edges

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Negative edges

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FLIP-FLOPS (2/2)

S

C
R

C
Q'

C
Q'

Q'

S

C
R

C
Q'

C
Q'

Q'

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S-R FLIP-FLOP

## R = HIGH and S = LOW Q becomes LOW (RESET state)

S = HIGH and R = LOW Q becomes HIGH (SET state)
Both R and S are LOW No change in output Q
Both R and S are HIGH Invalid!

S

C
R

Q'

CLK

Q(t+1)

0
0
1
1

0
1
0
1

Q(t)
0
1
?

No change
Reset
Set
Invalid

## X = irrelevant (dont care)

= clock transition LOW to HIGH
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S-R FLIP-FLOP

CLK

SET

RESET
Q

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D FLIP-FLOP

## D flip-flop: Single input D (data). On the triggering edge of the

clock pulse,
D = HIGH Q becomes HIGH (SET state)
D = LOW Q becomes LOW (RESET state)

D
CLK

CLK

Q(t+1)

Q'

1
0

1
0

C
R

## A positive edge-triggered D flip-flop

formed with an S-R flip-flop.
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Set
Reset

## = clock transition LOW to HIGH

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D FLIP-FLOP

CLK

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D FLIP-FLOP vs D LATCH
CLK for FF
Connect to EN for latch

D
Q for
D-flip-flop
Enabled!

Q for
D-latch

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D FLIP-FLOP

## Application: Parallel data transfer.

To transfer logic-circuit outputs X, Y, Z to flip-flops Q1, Q2 and
Q3 for storage.
D

CLK
X

Combinational
logic circuit

CLK

D
Transfer

CLK

Q1 = X*

Q'
Q

Q2 = Y*

Q'
Q

Q3 = Z*

Q'

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## J-K flip-flop: Q and Q' are fed back to the pulse-steering

NAND gates.

No invalid state.

## J = HIGH and K = LOW Q becomes HIGH (SET state)

K = HIGH and J = LOW Q becomes LOW (RESET state)
Both J and K are LOW No change in output Q
Both J and K are HIGH Toggle

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## J-K flip-flop circuit:

J
Q

Pulse
transition
detector

CLK

Q'

Characteristic table:
J

CLK

Q(t+1)

0
0
1
1

0
1
0
1

Q(t)
0
1
Q(t)'

No change
Reset
Set
Toggle

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J K

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Q(t+1)
0
0
1
1
1
0
1
0
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## Pulse detection circuit

Positive edge detection

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## Pulse detection circuit

Positive edge detection

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T FLIP-FLOP

## T flip-flop: Single input version of the J-K flip-flop, formed by

tying both inputs together.
T
Pulse
transition
detector

CLK

CLK
Q'

Q'

Characteristic table:
T

CLK

Q(t+1)

0
1

Q(t)
Q(t)'

No change
Toggle

Q T
0
0
1
1

0
1
0
1

Q(t+1)
0
1
1
0

## Q(t+1) = T Q' + T' Q

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Frequency Divider
CLK

Frequency = f
CLK

Q
Frequency = f / 2

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Frequency Divider
What

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## does this do?

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A 4 bit counter
A BCD

CLK
CLK is at frequency f: 1010101010101010101010101010101010
D is at frequency f/2: 110011001100110011001100110011001111
C is at frequency f/4: 111100001111000011110000111100001111
B is at frequency f/8: 1111111100000000111111110000000011111111
A is at frequency f/16: 11111111111111110000000000000000
Recall our truth table! Count down
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ABCD
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
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ABCD
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
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ABCD
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
40

cycle

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ABCD
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
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Decimal counter

cycle

## Both bit A and C to be set to 0 when A and D are both 1 in

the previous cycle

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ABCD
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
0000
0001
0010
0011
0100
0111
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## Frequency Divider (Odd)

A
B

CLK

Frequency = f
CLK
Frequency = f / 3
A
B

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sequential logic

Output

Synchronous

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counters

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## Example: 3-bit binary counter

Step 1: Formulate the problem either as a truth table or a finite state machine
Present State

Next State

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Will

## use one flip-flop for each of the

current state bits
3 JK flip-flops for A, B, and C, respectively

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inputs
Q

Present State

Next State

J K

0 0
0 0
0KB1
0 1
X
1 0
1 X0
1 01
1 1

0
1
0
1
0
1
0
1

Q(t+1)

JA

KA

JB

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Sequential Logic

JC

0
0
1
1
1
0
1
0

1
X
1
X

KC
X
1
X
1

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Step 3: K-map
A

BC

00 01 11

10

BC

00 01 11

10

JA = BC

BC

KA = BC

00 01 11

10

00 01 11

10

JB = C

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BC

KB = C

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BC

00 01 11

10

BC

10

JC = 1

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00 01 11

KC = 1

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Present State

Q T

Next State

TA

TB

TC

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0
0
1
1

0
1
0
1

Q(t+1)
0
1
1
0

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A

BC

00 01 11

10

BC

00 01 11

10

TB = C

TA = BC
A

BC

00 01 11

10

TC = 1

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A

CLK

CLK

CLK

CLK

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Output

## is both a function of an input and

the current state

Most

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0
1

states

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## Truth table for flip-flop inputs

Present
State

Input

Next
State

JA

KA

JB

KB

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Sequential Logic

J K

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Q(t+1)
0
0
1
1
1
0
1
0

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Step 3: K-map
A

BX

00 01 11

10

BX

00 01 11

JA = B

BX

KA = BX

00 01 11

10

BX

00 01 11

10

JB = X

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10

KB = AX + AX
=A X
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IMPLEMENTATION OF FSM

CLK

CLK
K

CLK
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## S-R, D and J-K inputs are synchronous inputs, as data on

these inputs are transferred to the flip-flops output only on the
triggered edge of the clock pulse.

## Asynchronous inputs affect the state of the flip-flop

independent of the clock; example: preset (PRE) and clear
(CLR) [or direct set (SD) and direct reset (RD)].

are LOW.

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## A J-K flip-flop with active-low PRESET and CLEAR

asynchronous inputs.
PRE

PRE
J

CLK

Q'

Q
Pulse
transition
detector
Q'

CLR

CLR
CLK
PRE
CLR

J = K = HIGH
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Preset
Sequential Logic

Toggle

Clear
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METASTABILITY (1/3)
In reality, nothing is instantaneous. Critical timing parameters must be observed.
CLOCK

tco

DATA

ts setup time
th hold time
tco clock to output time
(propagation delay)

OUTPUT

ts
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th
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METASTABILITY (2/3)
If setup and hold times are violated, flip-flop may
oscillate in an indeterminate state between 0
and 1
This is called metastability
Introduces error in the circuits operation
Cannot be absolutely avoided in practice

## Make sure clock period is long enough

Use flip-flop chain

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METASTABILITY (3/3)

Input

Output

CLK

## The probability of metastability gets closer and closer to

zero (but never zero) as the number of flip-flops
connected in series is increased.

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TRI-STATE MULTIPLEXERS

## Tri-state = high, low, highimpedance

High-impedance means the circuit
is not connected

A tri-state buffer:
When enabled, connects input to
output
When disabled disconnects input
from output by entering a highimpedance state

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## Memory stores programs and data.

Definitions:
1 byte = 8 bits
1 word: in multiple of bytes, a unit of transfer between main
memory and registers, usually size of register.
1 KB (kilo-bytes) = 210 bytes; 1 MB (mega-bytes) = 220 bytes;
1 GB (giga-bytes) = 230 bytes; 1 TB (tera-bytes) = 240 bytes.

## Desirable properties: fast access, large capacity, economincal

cost, non-volatile.

properties.

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Memory hierarchy
Fast, expensive
(small numbers),
volatile
registers
main memory
disk storage
magnetic tapes

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Slow, cheap
(large numbers),
non-volatile

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## A register is an array of D-flip-flops

A register file is a circuit with several registers, and
selection lines to choose on which register to operate
next
Features:
- Fast
- Multiported
concurrently)

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WR

Write data

CLK

CLK

CLK

CLK

Register
Number

4-bit register

Decoder

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MEMORY (1/2)

Data transfer
Processor

Up to 2k
locations.

MAR

Memory

0
1
2
3
4
5

## n-bit data bus

MDR

Control lines
(R/W, etc.)

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MEMORY (2/2)
A memory unit stores binary information in groups of bits
called words.

## The data consists of n lines (for n-bit words). Data input

lines provide the information to be stored (written) into
the memory, while data output lines carry the information

## The address consists of k lines which specify which word

(among the 2k words available) to be selected for reading
or writing.

## The control lines Read and Write (usually combined into

a single control line Read/Write) specifies the direction of
transfer of the data.
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MEMORY UNIT

## Block diagram of a memory unit:

n data
input lines
n

Memory unit
2k words
n bits per word

n

n data
output lines

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Write operation:
Transfers the data bits (the word) to be stored in memory to the
data input lines.
Activates the Write control line (set Read/Write to 0).

Memory Operation
0
X
None
1
0
Write to selected word
1
1

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MEMORY CELL

## Two types of RAM

Static RAMs use flip-flops as the memory cells.
Dynamic RAMs use capacitor charges to represent data. Though simpler in
circuitry, they have to be constantly refreshed.

A single memory cell of the static RAM has the following logic and
block diagrams:
Select

Select
R

Input

Output

BC

Output

Logic diagram
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Input

Block diagram
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## MEMORY ARRAYS (1/4)

Logic construction
of a 43 RAM (with
decoder and OR
gates):

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## An array of RAM chips: memory chips are

combined to form larger memory.

RAM 1K x 8
Input data 8
Chip select

DATA (8)
CS
RW

(8)

Output data

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Lines
11 10

Lines
09

Input data
8 lines

DATA (8)
(8)
CS
1K x 8
RW

2x4
decoder
S0
S1

0
1
2
3

1024 2047
DATA (8)
(8)
CS
1K x 8
RW

2048 3071

01023

DATA (8)
(8)
CS
1K x 8
RW

4K 8 RAM.

3072 4095
DATA (8)
(8)
CS
1K x 8
RW

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Output
data

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## MEMORY ARRAYS (4/4)

A0
A1

21bit

A19
A20

2bit
decoder

512K x 8
memory chip

19-bit

512kX8
memorychip

8-bit data
input/output

Chip select

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D3124

D2316

D 158

D70

2M 32 memory module
Using 512K 8 memory chips.
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END

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