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Original Title: Low Noise Amplifier

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RF Receiver

Antenna

BPF1

LNA

BPF2

Demodulator

RF front end

LO

Low-Noise Amplifier

First gain stage in receiver

Amplify weak signal

Dominate input-referred noise of front end

NFsubsequent 1

NF frontend NFLNA

GLNA

Impedance matching

Efficient power transfer

Better noise performance

Stable circuit

3

Noise performance

Power transfer

Impedance matching

Power consumption

Bandwidth

Stability

Linearity

Noise Figure

Definition

SNRin

Sin N in

NF

As a function of device

N device G N source

NF

G N source

NF of Cascaded Stages

Sin/Nin

Sout/Nout

G 1 , N1 ,

NF1

G i, N i,

NFi

GK, NK,

NFK

NF2 1 NF3 1

NFK 1

NF 1 NF1 1

...

G1

G1G2

G1G2 ...GK 1

Overall NF dominated by NF1

[1] F. Friis, Noise Figure of Radio Receivers, Proc.

IRE, Vol. 32, pp.419-422, July 1944.

6

k

Flicker noise V ( f ) WLC f

ox

Dominant at low frequency

2

g

Vg

Id

Vi

: empirical constant

2/3 for long channel

much larger for short channel

PMOS has less thermal noise

Input-inferred noise

Vi 2 ( f ) 4kT

g m WLCox f

7

Noise Approximation

Noise spectral

density

1/f noise

Thermal noise

dominant

Thermal noise

Band of interest

Frequency

8

Rs

Vs

2

jXs

jXL

V

RL

Vs

Pdel

RL

Rs jX s RL jX L

Pmax

VsVs*

PL R R , X X 0

s

L

s

L

4 Rs

Impedance matching

Load and source impedances conjugate pair

Real part matched to 50 ohm

9

Available Power

and source resistors

10

Reflection Coefficient

Rs

Vs

jXs

V IZ L

jXL

V

RL

I I * ( Z L Z L* )

Pdel

2

Pmax

VsVs* (V IZ s )(V IZ s )*

aa*

4 Rs

4 Rs

(V IZ s* )(V * I *Z s )

Pref Pmax Pdel

bb*

4 Rs

V IZ s

a

2 Rs

V IZ s*

b

2 Rs

b Z L Z s*

a ZL Zs

11

Reflection Coefficient

No reflection

Maximum power transfer

12

S-Parameters

Parameters for two-port system analysis

Suitable for distributive elements

Inputs and outputs expressed in powers

Transmission coefficients

Reflection coefficients

13

S-Parameters

a1

b2

S21

S11

S22

S12

b1

b1 S11a1 S12 a2

a2

b2 S 21a1 S 22 a2

14

S-Parameters

b1

S11

a1 a 20

the output matched

b2

S21

a1 a 20

loss

b1

S12

a2 a10

isolation

b2

S22

a2 a10

the input matched

15

S-Parameters

I1

Z1

Vs1

V1

I2

V2

Z2

Vs2

V1 I1Z1*

S11

V1 I1Z1 V

V2 I 2 Z 2* Re( Z1 )

S21

V1 I1Z1 Re( Z 2 ) V

V1 I1Z1* Re( Z 2 )

S12

V2 I 2 Z 2 Re( Z1 ) V

V2 I 2 Z 2*

S22

V2 I 2 Z 2 V

s 2 0

s 2 0

s 1 0

s 1 0

16

Stability Condition

Necessary condition

1 | S22 |2 | S11 |2 | S |2

K

1

2 | S12 S21 |

where

Stable iff

| S |2 L L 1

where

| S11 |2 | S 22 |2

L | S12 S 21 |

2

17

Rs

io

No flicker noise

ro = infinity

Cgd = 0

Reasonable for appropriate

bandwidth

Vs

Rs 4kTRs

Vs

Assume

Vgs

gmVgs

Effective transconductance

io g m Z in

Gmeff

Vs Rs Zin

4kTg

m

18

Power Gain

Voltage input

Current output

ii

g m Z in

2

G

| Gmeff |

*

VsVs

Rs Z in

*

o o

g m 1 ( jC gs )

gm

Rs 1 ( jC gs )

1 jRs C gs

T 1

g

2

2

1 ( Rs C gs )

Rs

2

m

19

Power ratio @ output

Device noise + input-induced noise

Input-induced noise

N device G N in

NF

1

G N in

4kT g m

g m2

4kTRs

1 2 ( RsC gs ) 2

1

(1 2 Rs2C gs2 )

Rs g m

2

1

Rs g m

Rs g m

( g m / C gs ) 2

gm

T

C gs

20

iin

iout

Ai

iin

iout T

Ai

1

TT

iin T

Device

iout

Ai

fT

0dB

frequency

21

i2

i1

V1

i1

Rg

Cgs

V1

Cgs

Cgd

V2

i2

Cgd

Vgs

ri rds

Cdb

V2

rds

Cdb

Rg: Gate resistance

ri: Channel charging

resistance

gmVgs

22

T Calculation

i1

Rg

Cgs

V1

i2

Cgd

Vgs

ri rds

Cdb

i1

Rg

Cgs

gmVgs

V1

Cgd

i2

Vgs

ri

gmVgs

s (Cgs C gd ) s 2 riCgsCgd

I1

Y11

2

I2

Y21

2

23

Set:

Y11 ( j T )

Y21 ( j T )

1

Solve for T

gm

T

gm

Cgs C gd

IEEE J. Solid-State Circuits, vol. 34, pp. 277 - 285, March 1999.

24

Noise Performance

2

NF 1

Rs g m 2

Rs g m

T

Low frequency

Rsgm >> ~ 1

gm >> 1/50 @ Rs = 50 ohm

Power consuming

CMOS technology

gm/ID lower than other tech

T lower than other tech

25

No impedance matching

Capacitive input impedance

Output not matched

Power transfer

S11=(1-sRCgs)/(1+sRCgs)

S21=2Rgm/(1+sRCgs), R=Rs=RL

Power consumption

High power for NF

High power for S21

26

Resistive termination

Series-shunt feedback

Common-gate connection

Inductor degeneration

27

Resistive Termination

io

Rs

Vs

RI

4kTgm

4kT/Rs 4kT/RI

Is

Rs

RI

Vgs

gmVgs

gm

G

1 / Rs 1 / RI j Cgs

Noise figure

2

Rs Rs 1

1

2

NF 1

g m Rs 2

RI

g m Rs RI

T

28

Previous example

2

NF 1

Rs g m 2

Rs g m

T

Resistive-termination

2

Rs

Rs

2

1 g m Rs 2

NF 1

RI g m Rs

RI

T

Introduced by input

resistance

Signal attenuated

29

Noise performance

Low-frequency approximation

Input matched Rs = RI = R

4

NF 2

gm R

Attenuate signal

Introduce noise due to RI

NF > 3 dB (best case)

30

Series-Shunt Feedback

RF

Rs

Vs

RL

( RF RL )(1 g m Ra sRaC gs )

Rin

1 g m ( RL Ra ) s ( Ra RF RL )C gs

Ra

Rs

Cgs

Vs

Broadband matching

Rout

iout

RF

Vgs

gmVgs

RL

(1 g m Ra )( RF Rs )

1 ( g m sC gs )( Rs Ra )

sC gs ( Ra RF Rs RF Ra Rs )

1 ( g m sC gs )( Rs Ra )

Could be noisy

Ra

31

Common-Gate Structure

Rs

RL

Rs 4kTRs

Vgs gmVgs

Vs

Geff

I out

Vs

gm

1 g m Rs sRs C gs

Rs 4kTRs

Vs

4kTgm

RL

Vgs

RL

gm

gmVgs

4kTgm

32

Input impedance

Yin=gm+sCgs

Input-impedance matching

Low frequency approximation

Direct without passive components

1/gm=Rs=50 ohm

33

2

G Geff

g m2

(1 g m Rs ) 2 2 ( Rs Cgs ) 2

N device G N in

NF

1

G N in

4kT g m

g m2

4kTRs

(1 g m Rs ) 2 2 ( RsCgs ) 2

1

(1 g m Rs ) 2 2 Rs2C gs2

Rs g m

2

1 4 2

T

Signal attenuated

34

Rs = RL = R = 50 ohm

Z in Z s* 1 g m Rs sRsC gs

S11

Z in Z s 1 g m Rs sRsC gs

sRsC gs

2 sRsCgs

S21 2 RLGeff

2 RL g m

1 g m Rs sRsC gs

2

2 sC gs

35

Summary CG Structure

Noise performance

No extra resistive noise source

Independent of power consumption

Impedance matching

Broadband input matching

No passive components

Power consumption

gm=1/50

Power transfer

Independent of power consumption

36

Rs

Vs

Rs

Lg

Zin

iin

Ls

Vs

iout

Lg

Vin

Cgs

Vgs

gmVgs

Ls

1

Vin I in sLg I in

( I in g mVgs ) sLs

sC gs

1

1

I in sLg I in

( I in g m I in

) sLs

sC gs

sC gs

1

g m Ls

I in s ( Lg Ls )

sC gs C gs

Zin

37

Rs

Zin

Vs

Ls

Cgs

gmLs/Cgs

Zin=Rs

iout

Lg

Vgs

gmVgs

1

g m Ls

Z in s ( Lg Ls )

sC gs C gs

IM{Zin}=0

1

( Lg Ls )C gs

RE{Zin}=Rs

g m Ls

Rs

C gs

2

0

38

Effective Transconductance

Rs

Zin

Ls

gmLs/Cgs

Vs

Geff

iout

Lg

Cgs

Vgs

gmVgs

I out g m ( sC gs )

Vs

Rs Z in

gm

1 s ( RsC gs g m Ls ) s 2C gs ( Lg Ls )

39

G Geff

g m2

[1 2C gs ( Lg Ls )]2 2 ( RsC gs g m Ls ) 2

Calculate NF at 0

NF

N device G N in

1

G N in

= 0 @ 0

4kT g m

g m2

4kTRs 2

( RsC gs g m Ls ) 2

2 ( RsCgs g m Ls ) 2

Rs g m

40

I

Rs

Vs

Stored power

Q

Lost power

Ls

gmLs/Cgs

I I * C

1

*

II R

CR

Lg

Cgs

1

1

Qin

CR C gs ( Rs g m Ls / C gs )

1

1

( Rs C gs g m Ls ) 2Rs C gs

41

1

Qin

( RsC gs g m Ls )

NF

1

2 ( RsCgs g m Ls ) 2

Rs g m

1

1

Rs g m Qin2

gmLs/Cgs = Rs

Decrease NF

gmLs/Cgs = 0

Conflict between

Power transfer

Noise performance

42

Further Discussion on NF

Frequency @ 0

NF

1

2 ( RsC gs g m Ls ) 2

Rs g m

4( g m Ls ) 2

1

1

Rs g m C gs ( Lg Ls )

4 Ls

1

Lg Ls

2 ~= 1/Cgs/(Lg+Ls)

Input impedance

matched to Rs

RsCgs=gmLs

Ls Rs T

calculation and design

Large Lg and small Ls

Ls Lg 1 02C gs

43

Rs = RL = R = 50 ohm

2

Z in Z s* 1 s C gs ( Lg Ls ) sg m Ls sRsCgs

S11

Z in Z s 1 s 2C gs ( Lg Ls ) sg m Ls sRsCgs

1 s 2Cgs ( Lg Ls )

1 s ( g m Ls RsC gs ) s 2C gs ( Lg Ls )

S 21 2Geff RL

@ 20

2 g m RL

1 s ( RsCgs g m Ls ) s 2Cgs ( Lg Ls )

1

( Lg Ls )C gs

S11 0; S 21

1

Qin

( RsC gs g m Ls )

2 g m RL

R

j 2 g m RLQin j T L

j0 ( Rs C gs g m Ls )

0 Rs

44

Rs

Vs

Lg

Ls

I in Vs 2 Rs ;

I o g mVgs g m I in j0C gs

Vo

T

1/ 2

Av

j

Vs

0 Rs (Yo Yo )

45

Power Consumption

P I DVDD

Cox W

(Vgs VT ) 2 VDD

2 L

2

Cgs CoxWL

3

W

g m Cox (Vgs VT )

L

g m2 L2 3

W

2

Cox

Vgs VT

C gs 2

L

g m Ls

Rs

C gs

gm

RsC gs

Ls

g m2 L2

L2 Rs2

L2 Rs2

VDD

P

VDD

C gsVDD

2

3C gs

3 Ls

3 L2s 02 ( Lg Ls )

2

L

1 T

L2VDD

1 L2 Rs2

VDD

P

C gsVDD

2 3

3

3 0 ( Lg Ls ) 3 0 Ls (1 Lg / Ls )

2 2

T

46

Power Consumption

L2 Rs2

1

P 2 3

0 Ls (1 Lg / Ls )

NF

4 Ls

1

Lg Ls

Technology constant

L: minimum feature size

: mobility, avoid mobility saturation region

Standard specification

Rs: source impedance

0: carrier frequency

Circuit parameter

Lg, Ls: gate and source degeneration inductance

47

Summary of ID Structure

Noise performance

No resistive noise source

Large Lg

Impedance matching

Matched at carrier frequency

Applicable to wideband application, S11<-10dB

Power transfer

Narrowband

Increase with gm

Power consumption

Large Lg

48

Cascode

LL

Vbias

Rs

Vs

M2

@ high frequency

Vo

Vd1

Lg

M1

Ls

Reduced feedback effect

of Cgd

Improve noise

performance

49

LL

Rs

Rs

Vo

Lg

Vs

Ls

Vo

Cgs

M1

Vs

Lg

Ls

Vgs

gmVgs

LL

50

M4

Vbias

Rs

Vs

Lb1

Cb1

Input

bias

Vdd

Lvdd

Lb2

Cb2 V

out

Ld

Lout

Output

bias

M2

M3

Tm

Cm

Lg

M1

Lgnd

Ls

Off-chip

matching

[3] D. Shaeffer and T. Lee, A 1.5-V, 1.5-GHz CMOS low noise amplifier, IEEE J. Solid51

State Circuits, vol. 32, pp. 745 759, May 1997.

Supply

filtering

Lvdd

M4

Ld

Vbias

Rs

Vs

Lb1

Cb1

Lout

M2

M3

Tm

Cm

Lg

M1

Lgnd

Ls

Unwanted

parasitics

[3] D. Shaeffer and T. Lee, A 1.5-V, 1.5-GHz CMOS low noise amplifier, IEEE J. Solid52

State Circuits, vol. 32, pp. 745 759, May 1997.

Circuit Details

Two-stage cascoded structure in 0.6 m

First stage

W1 = 403 m determined from NF

Ls accurate value, bondwire inductance

Ld = 7nH, resonating with cap at drain of M2

Second

4.6 dB gain

W3 = 200 m

53

54

NF = 1 + K/gm

gm = gm1 + gm2

RB

IREF

VRF

IB1

M2

RX

Ns

Off-chip

matching

M1

Cs

CB

M4

CX

Vout1

M5

VB1

NL

Off-chip

matching

M7

M3

M6

[4] A. Karanicolas, A 2.7-V 900-MHz CMOS LNA and Mixer, IEEE J. Solid-State

Circuits, vol. 31, pp 1939 1944, Dec. 1996.

55

Simplified view

56

M8

RB

IREF

VRF

IB1

M2

RX

Ns

M1

Cs

CB

M4

CX

Vout1

M5

NL

VB1

M7

M3

M6

Bias

feedback

[4] A. Karanicolas, A 2.7-V 900-MHz CMOS LNA and Mixer, IEEE J. Solid-State

Circuits, vol. 31, pp 1939 1944, Dec. 1996.

57

M8

RB

IREF

VRF

IB1

M2

RX

Ns

M1

Cs

CB

M4

CX

Vout1

M5

NL

VB1

M7

M3

M6

Bias

feedback

[4] A. Karanicolas, A 2.7-V 900-MHz CMOS LNA and Mixer, IEEE J. Solid-State

Circuits, vol. 31, pp 1939 1944, Dec. 1996.

58

VA

M8

RB

IREF

VRF

IB1

M2

RX

Ns

M1

Cs

CB

DC output = VB1

M4

CX

Vout1

M5

NL

VB1

M7

M3

M6

Bias

feedback

Circuits, vol. 31, pp 1939 1944, Dec. 1996.

59

60

would:

selectivity

Achieve a good noise performance

61

LNA Architecture

The cascode architecture

provides a good input

output isolation

Transistor M2 isolates the

R1

Miller capacitance

Input Impedance is obtained

using the source

M3

degeneration inductor Ls

R2

Gate inductor Lg sets the

resonant frequency

LG

The tuning granularity is

Input to LNA

achieved by the output

matching network

VDD

LD

M2

M1

Matching

Network

Output to

Mixer

LS

62

Matching Network

The output matching tuning

network is composed of a

varactor and an inductor.

The LC network is used to

convert the load impedance

into the input impedance of

the subsequent stage.

A well designed matching

network allows for a maximum

power transfer to the load.

By varying the DC voltage

applied to the varactor, the

output frequency is tuned to a

different frequency.

63

The input return loss

S11 is less than 10dB

at a frequency range

between 1.4 GHz and

2GHz

64

Simulation results - NF

The noise figure is 1.8

dB at 1.4 GHz and rises

to 3.4 dB at 2 GHz.

Noise Figure

65

is tuned by 2.5 MHz.

The output return loss at 1.77 GHz is 44.73 dB and the output return

loss at 1.7725 GHz 45.69 dB.

66

The output return loss at 2 GHz is 26.47 dB and the output return

loss at 1.9975 GHz 26.6 dB.

S22 at 2 GHz

67

The overall gain of

the LNA is 12 dB

68

The third order input intercept is 3.16 dBm

-1 dB compression point ( the output level at which the actual gain

departs from the theoretical gain) is 12 dBm

IIP3

69

k

Flicker noise V ( f ) WLC f

ox

Dominant at low frequency

2

g

Vg

Id

Vi

: empirical constant

2/3 for long channel

much larger for short channel

PMOS has less thermal noise

Input-inferred noise

k

Vi ( f ) 4kT

g m WLCox f

2

70

Modifications

Thermonoise

gm

I ( f ) 4kT g do 4kT

2

d

= 2/3 in long channel

= 2 to 3 (or higher!) in short

channel NMOS (less in PMOS)

71

72

73

Fliker noise

Traps at channel/oxide interface randomly

capture/release carriers

k

V (f)

fWLCox

2

g

I (f)

2

d

Kf

n

Kf

f

f

Parameterized by Kf and n

Provided by fab (note n 1)

Currently: Kf of PMOS << Kf of NMOS due to buried channel

74

Fluctuating channel potential couples

capacitively into the gate terminal, causing a

noise gate current

2

ing 4kTg do

Typically assumed to be 2

75

real

Input impedance

g m Ldeg

1

Z in ( s ) s ( Lg Ldeg )

sC gs

C gs

Set to be real and equal to source resistance:

1

( Lg Ldeg )C gs

2

0

g m Ldeg

C gs

Rs

76

I d2 ( f ) kT g do 1 2 c d d2 (4Q 2 1)

1

1 2 c d d2 (4Q 2 1)

4

gm

d

g do 5

c=-j0.55, =3, =6, gdo=2gm,

d = 0.32

0 ( Lg Ldeg )

1

Q

2 Rs0C gs

2 Rs

77

Noise factor

o

F 1

T

2Q

g do

1 2 c d (4Q 2 1) d2

gm

g do

1 2 c d (4Q 2 1) d2

K nf

2Q g m

Compare:

NF

0

N device G N in

2

2

1

0 4( Rs C gs ) 1

4

G N in

Rs g m

T 2Q

78

79

Example

Assume Rs = 50 Ohms, Q = 2, fo = 1.8 GHz, ft = 47.8

GHz

1

Q

From

2 Rs0C gs

1

1

C gs

442 fF

2 Rs0Q 2(50)2 1.8e9(2)

Ldeg

Rs C gs

gm

Rs

50

0.17nH

T 2 47.8e9

1

1

Lg 2

Ldeg 17.5nH

( Lg Ldeg )C gs

0 C gs

2

0

80

81

If we choose Vgs=1V

Idens = 175 A/m

From Cgs = 442 fF, W=274m

Ibias = IdensW = 48 mA, too large!

Solution 1: lower Idens => lower power,

lower fT, lower IIP3

Solution 2: lower W => lower power, lower

Cgs, higher Q, higher NF

82

83

g m 0.78

gm

0.68 d

g do 1.15

g do

2

0.68

0.43

5

5

g m 0.78mS

T

2 42.8 GHz

C gs

2.9 fF

We now need to re-plot the Noise Factor scaling coefficient

- Also plot over a wider range of Q

o

F 1

T

g do 1

1 2 c d (4Q 2 1) d2

g m 2Q

84

85

Recall

- Cuts power dissipation by a factor of 3!

- New value of W is one third the old one

W

274 m

91m

3

86

42.8 GHz

Ibias = IdensW =100A/m*91m=9.1mA

Power = 9.1 * 1.8 = 16.4 mW

Noise factor scaling coeff = 10

Noise factor = 1+ wo/wt * 10

= 1+ 1.8G/42.8G *10 = 1.42

Noise figure = 10*log(1.42) = 1.52 dB

Cgs=442/3=147fF

Ldeg=Rs/wt=0.19nH

Lg=1/(wo^2Cgs) Ldeg = 53 nH

87

In practice, use cascode to boost gain

Added benefit of removing Cgd effect

88

Differential LNA

Value of Ldeg is now much better controlled

Much less sensitivity to noise from other circuits

But:

Requires differential input at the chip

89

NMOS current adjusted to match the PMOS current

Note: not clear how the matching network is achieving a 50 Ohm match

Perhaps parasitic bondwire inductance is degenerating the PMOS or

NMOS transistors?

90

Combining inductive

degeneration and current reuse

Current reuse to save power

Larger area due to two degeneration

inductor if implemented on chip

NF: 2dB, Power gain: 17.5dB, IIP3: 6dBm, Id: 8mA from 2.7V power supply

Can have differential version

F. Gatta, E. Sacchi, et al, A 2-dB Noise Figure 900MHz Differential CMOS LNA,

IEEE JSSC, Vol. 36, No. 10, Oct. 2001 pp. 1444-1452

91

At AC, M1 and M2 are in cascade

S of M2 is AC shorted

Gm of M1 and M2 are multiplied.

Same biasing current in M1 & M2

LIANG-HUI LI AND HUEY-RU CHUANG, MICROWAVE JOURNAL from the February 2004 issue.

92

current of the main transistor has

the required information of its

nonlinearity

Auxiliary circuit is used to tune the

magnitude and phase of IM3

components

Addition of main and auxiliary

transistor currents results in

negligible IM3 components at

output

ia g m1va g v g v

2

m2 a

3

m3 a

ib g m 3vb3

i o ia ib

Sivakumar Ganesan, Edgar Snchez-sinencio, And Jose Silva-martinez

IEEE Transactions On Microwave Theory And Techniques, Vol. 54, No. 12, December 2006

93

MOS transistor in weak inversion acts like bipolar

Bipolar available in TSMC 0.18 technology (not a parasitic BJT)

Why not using that bipolar transistor to improve linearity ?

94

Inter-stage inductor with

parasitic capacitance form

impedance match network between

input stage and cascoded stage

boost gain lower noise figure.

affected

95

Folded cascode

Ld reduces or eliminates

Effect of Cgd1

Good fT

96

Source Degenerated LNA

Noise factor equations:

o

F 1

T

g do 1

1 2 c d (4Q 2 1) d2

g m 2Q

g do 1

K nf

1 2 c d (4Q 2 1) d2

g m 2Q

97

Targeted Specifications

Frequency

2.4 GHz ISM Band

Noise Figure

1.6 dB

IIP3

-8 dBm

Voltage gain20 dB

Power

< 10mA from 1.8V

98

A 0.18um CMOS Process

Process related

tox = 4.1e-9 m

= 3.9*(8.85e-12) F/m

= 3.274e-2 m^2/V.s

Vth = 0.52 V

Noise related

= gm/gdo

~ 2

~3

c = -j0.55

99

100

Insights:

gdo increases all the way with current

density Iden

gm saturates when Iden larger than

120A/m

Velocity saturation, mobility degradation ---short channel effects

Low gm/current efficiency

High linearity

with large Iden

101

102

Insights:

fT increases with Vod when Vod is small and

saturates after Vod > 0.3V --- short channel

effects

Cgs/W increases slowly after Vod > 0.2V

fT begins to degrade when Vod > 0.8V

gm saturates

Cgs increases

103

knf vs input Q and current density

inspection

design reference

104

Design trade-offs

For fixed Iden, increasing Q will reduce the

size of transistor thus reduce total power

---- noise figure will become larger

For fixed Q, reducing Iden will reduce

power, but will increase noise factor

For large Iden, there is an optimal Q for

minimum noise factor, but power may be

too high

105

Linearity plots :IIP3 vs. gate overdrive and transistor size

106

Insights:

MOS transistor IIP3 only, when embedded into

actual circuit:

Input Q will degrade IIP3

Non-linear memory effect will degrade IIP3

Output non-linearity will degrade IIP3

Generally, large overdrive means large IIP3

But the relationship between IIP3 and gate overdrive

is not monotonic

There is a local maxima around 0.1V overdrive

107

Step 4: Estimate fT

does not allow large gate over drive :

Vod ~ 0.2 V ~ 0.4 V

fT ~ 40 ~ 44 GHz

108

Calculate Device Size

Gm/W~0.4

109

Estimated IIP3:

IIP3(from curve) 20log(Q) = 8-12 = -4dBm

Specs require: -8 dBm

110

noise factor requirement

111

Gm=0.4*128 ~ 50 mS

fT = gm/(Cgs*2pi) = 48 GHz

112

Large deviation

113

114

specs and simulation results

Parameter

Noise Figure

Drain Current

Voltage gain

IIP3

P1dB

S11

Power supply

Target

1.6 dB

< 10mA

20 dB

-8 dBm

1.8 V

Simulated

0.8 dB

8 mA

21 dB

-6.4 dBm

-20dbm

-17 dB

1.8 V

115

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