Development of Reusable Environment

for
I2C Protocol

PRESENTED BY:

SANKULA SIVA SANKAR

S.S.G.KRISHNA YADAV .K
KANCHI SRILATHA
V.VAMSI KRISHNA
M.NIKLESH REDDY

Project Guide:
PADMANABAN

Aim:
To verify I2C master

Objectives:
1.To conduct a literature survey to understand the functionality of I2C.
2.To define specifications.
3.To develop the simulation model of the I2C master DUT.
4.To develop the reusable verification Environment.
5.To analyze functional & code coverage reports.

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Introduction:

The name stands for Inter - Integrated Circuit Bus

A Small Area Network connecting ICs and other electronic systems

Originally intended for operation on one

single board / PCB
Synchronous Serial Signal
Two wires carry information between
a number of devices
One wire use for the data
One wire used for the clock

Today, a variety of devices are available with I2C Interfaces

Microcontroller, EEPROM, Real-Timer, interface chips, LCD driver, A/D converter

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Features:

Data transfer between ICs and systems at relatively low rates

Classic I2C is rated to 100K bits/second
Fast Mode devices support up to 400K bits/second
A High Speed Mode is defined for operation up to 3.4M bits/second

Reduces Board Space and Cost By:

Allowing use of ICs with fewer pins and smaller packages
Greatly reducing interconnect complexity
Allowing digitally controlled components to be located close to their point of
use.

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I2C specification

Single master single slave

Synchronous

Bidirectional Serial Communication

7-bit addressing mode

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Master:

Initiates a transfer by generating

start and stop conditions
Generates the clock
Transmits the slave address
Determines data transfer direction

Slave:

Responds only when addressed

Timing is controlled by the clock line

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Top level diagram

MICRO
PROCESSOR

CLOC
K
RESE
T
ADDRES
S
DATA_IN
DATA_OUT

I2C
MASTER
CONTROLL
ER

SCL
SDA

R/W

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Pin Description
SIGNAL
NAME

SIGNAL
DIRECTION

DEFINITION

ACTIVE STATE

Clock

Input

Microprocessor
clock

N/A

Reset

Input

System reset

Active Low

Address

Input

Address bits
reading and
writing to
configuration
and data
registers

N/A

Data

Bi-directional

Data bus

N/A

RW

Input

SDA

Bi-directional

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SCL

1 = RD
0 = WR
I2C Data bus
line

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Uni-directional

I2C Clock line

N/A

N/A

Operation of I2C Bus

Start Condition

Slave address + R/W

Slave acknowledges with ACK

All data bytes

Each followed by ACK

Stop Condition

SDA
ACK from
Slave

ACK from
Receiver

SCL
Start
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Remember : Clock is produced by

Master
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Stop
9

WRITE OPERATION:

generate start command

write slave address + write bit
receive acknowledge from slave write data
receive acknowledge from slave
generate stop command

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Read operation:
generate start bit
Read slave address + read bit
receive acknowledge from slave
Read data
Send acknowledge to slave
write no acknowledge (NACK) to slave,
indicating end of transfer
generate stop signal

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TIMING DIAGRAM
CLK
RESE
T
R=1/W
=0
DATA_IN

D0

D1

D2

xxxx

xxxx

xxxx

ADD

A0

A1

A2

A3

A4

A5

xxxx

xxxx

xxxx

D7

D8

D9

DATA_OUT

Schedule:-Gantt chart

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Objectives

Phase-I

Survey

20-1-2015

specifications

27-1-2015

simulation

Will complete
by 6-2-2015

Phase-II

environment

14-2-2015

coverage

15-2-2015
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Deliverables

verify model and DUT

Test plan and valid test cases
Environment using System Verilog
Code and Functional Coverage
reports

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References

www.nxp.com
SPI vs I2C pdf
www.ti.com
www.opencores.org

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