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High Speed

Electrical Testing
Jim Choate
Intel Corporation

May 8, 2001

Agenda
Electrical Testing Goals
Test Modes
Electrical Testing Procedures
Problems to Avoid
Summary

May 8, 2001

Goals of the Electrical


Compliance Program
High Quality USB Products
Stable, Repeatable, Well Documented Tests
Documented Equipment Setups
Documented Test Procedures
Documented Test Assertions and Descriptions

Leverage USB FS/LS Electrical Tests


FS and LS Electrical Testing (LS for downstream ports)
Inrush
Drop and Droop
May 8, 2001

New Testing Areas


USB High Speed Electrical Testing Starts at a High Level
Electricals
High Speed Signal Quality
Time Domain Reflectometry
(TDR)
Receiver Sensitivity and
Squelch
J and K Voltage Levels
ChIRP

Disconnect thresholds
Packet Parameters
Suspend/Resume
High Speed Hub Parameters
Sync truncation
EOP dribble
etc

HS Electrical Test Spec On USB-IF Members Site


May 8, 2001

USB HS Electrical
Test Modes
High-speed Capable Devices/Hubs Must Support
Test Modes

May 8, 2001

General HS Electrical
Test Procedure
Connect Device Under Test To Test Port on Fixture
Configure DUT With Test Mode SW
Isolate DUT from Host with High Speed Relay
Make Appropriate Electrical Measurements

May 8, 2001

New Test Fixture(s)


Diff Probe

90 Ohms
Test Port

Initialization
Port

HS
HS Relay
Relay

Vbus1 Power
Vbus2
Vcc Selection
Selection
Ckt
Ckt

Data
Generator

Signal Quality
TDR
Receiver Sensitivity
ChIRP
J and K Levels
Disconnect threshold
Packet parameters
Suspend & Resume
Test Modes

Gnd

USB HS Test Fixture


May 8, 2001

New Test Fixture(s)


Isolation relay power
Diff Probe Test Point

Test Port

Test Switch

Init Port

To Device
Under Test

To Host
Controller

High Speed Device Signal


Quality Test Fixture
May 8, 2001

HS Signal Quality
Test Procedure
Oscilloscope

Put Device in Test Mode


Test_Packet

Test Mode

SW

Flip Test Fixture Relays


To Route Output to
Differential Probe
90 Ohm Termination
USB HS Test Fixture
Capture Waveform
on oscilloscope
90
Analyze data
HS
HS Relay
Relay

Data analysis is
performed by generating
an eye pattern
May 8, 2001

Device
Under
Test

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Eye Pattern Generation


Time vs. voltage test packet data is transferred
from scope to PC through GPIB

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Eye Pattern Generation


Signal analysis scripts determine data rate from
zero volt crossovers
Crossovers indicated at zero crossings below
Mean bit time calculated
Reference frame created
from mean

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Eye Pattern Generation


Reference frame position is optimized by
minimizing least squares error between
reference frame and actual crossovers
Reference points between
runs ignored
Optimized reference point

Actual crossover

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Eye Pattern Generation


hs plot
0.5
0.4
0.3
0.2
0.1
volts

Data is parsed into


bit time internals
using optimized
reference frame
Eye pattern created
from bit time
intervals

0
-0.1
-0.2
-0.3
-0.4
-0.5
tim e

0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5

May 8, 2001

1 bit time

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Passing Eye Pattern


Example of passing High Speed Eye - Host
Controller at TP2

May 8, 2001

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Failing Eye Patterns


Min/Max voltage level failure
Caused by out of spec HS
termination

May 8, 2001

Jitter failure
Caused by noise from
power supply

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HS Device Receiver Sensitivity


and Squelch Test Procedure
Data Generator

Test Mode

SW
DUT is Placed In
Test_SEO_NAK Test Mode
using Test Mode SW
The test fixture replaces
the host by switching the
connection to the Data
Generator
USB 2.0 Test Fixture
Data Generator
Generates IN Packets
Device Must Respond
for In Spec Packets
Device Must Not Respond
to Out of Spec Data
Generator Output

SMA

HS
HS Relay
Relay

May 8, 2001

Device under
test

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HS Device Receiver Sensitivity


and Squelch Test Results
Device response
to nominal
packets

Device response
to minimum
packets

Device must not


respond to
packets below
squelch threshold

Minimum Receiver sensitivity threshold

DG packet
May 8, 2001

Device Response

No Device Response
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TDR Test Procedure


TDR

Test Mode

SW
Device Under Test
Placed In Test_SEO_NAK
Mode
Relay Switches Idle Data
Lines to TDR
USB 2.0 Test Fixture
TDR Broadcasts
Test Signal
TDR Measures
Signal Reflections To
Determine Termination
And PCB Impedance

SMA

HS
HS Relay
Relay

May 8, 2001

Device Under
Test

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TDR Test Procedure


Determining connector reference location

TDR connected to test fixture


Test fixture disconnected from device under test
Voltage step occurs at connector end (open step)

Open voltage step indicates


connector
reference location

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TDR Test Procedure


Measuring TDR response

USB connector

ZHSTERM
80 to 100 Ohms
(yellow region)

ZHSTHRU
70 to 110 Ohms
(red cursors)
Excursion of ZHSTHRU passes
using exception window

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TDR Test Procedure


TDR Test Fails
Cause: Using a ribbon cable between the PCB & USB connector

Violates ZHSTHRU for > 800ps

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Other Test Modes


Test_J & Test_K
Port enters and remains in the high-speed
J or K state
Allows testing of output voltage and impedance
when each output is high or low

Test Force Enable


Allows testing disconnect

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Conclusions
High Speed Electrical Testing is Comprehensive
Electrical Testing
HS Signal Quality
TDR
Receiver Sensitivity
Suspend/Resume

Repeater Testing
Sync truncation, EOP dribble, etc

Well Documented Tests


Test Procedures
Test Specifications

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