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- 23.IJAEST Vol No 6 Issue No 1 Low Power ASIC Design for Automation in Various Industrial Applications 144 149

You are on page 1of 80

Chapter 9

9.1 Introduction

Digital Circuits

Fig. 9.1

Block diagram

of an

asynchronous

sequential

3

Digital Circuits

no clock pulse

difficult to design

delay elements: the propagation delay

must attain a stable state before the input is

changed to a new value

circuits unless it is absolutely necessary

Digital Circuits

The procedure

Assign Yi's (excitation variables), yi's (the

secondary variables)

Derive the Boolean functions of all Yi's

Plot each Y function in a map

Construct the state table

Circle the stable states

Digital Circuits

Examples

Fig. 9.2

Example of an

asynchronous

sequential

circuit

Y1 = xy1+ x'y2

Y2 = xy1' + x'y2

Digital Circuits

Fig. 9.3

Maps and

transition

table for the

circuit of

Fig. 9.2

the external variable for the columns

Y=y

Digital Circuits

The difference

when the triggering edge of the clock

asynchronous design: the internal state can

change immediately after a change in the input

y: the present state

Y: the next state

Digital Circuits

Digital Circuits

A flow table

symbolized with letters

Fig. 9.4

Example of

flow tables

it has only one stable state in each row

Digital Circuits 10

Fig. 9.5

Derivation of a

circuit specified

by the flow

table of Fig.

9.4(b)

Digital Circuits

11

Race conditions

value

00 11

00 10 11 or 00 01 11

a noncritical race

otherwise, a critical state

Digital Circuits

12

Noncritical race

Fig. 9.6

Examples of

non-critical

Digital Circuits

13

Critical race

Fig. 9.7

Examples of critical

races

Digital Circuits

14

at any one time

insert intermediate unstable states with a unique

state-variable change

A cycle

Digital Circuits

15

A cycle

Fig. 9.8

Examples of cycles

Digital Circuits

16

Stability Considerations

Fig. 9.9

Example of an

unstable circuit

Digital Circuits

17

the use of SR latches in asynchronous circuits

produces a more orderly pattern

reduce the circuit complexity

Digital Circuits

18

Fig. 9.10

SR latch with NOR gates

Digital Circuits

19

the state transition table

an unpredictable result when SR: 11 00

SR = 0 in operation

SR' + SR = S(R'+R) = S

Y = S + R'y when SR = 0

two cross-coupled NAND gate

S'R' = 0

Y = (S(Ry)')' = S'+ Ry when S'R' = 0

S'R' latch

Digital Circuits

20

Fig. 9.11

SR latch with NAND gates

Digital Circuits

21

Analysis example

Fig. 9.12

Examples

of a circuit

with SR

latch

Digital Circuits

22

feedback path with yi

S1 = x1y2

R1 = x'1x'2

S2 = x1x2

R2 = x'2y1

whether S'R'=0 for each NAND latch

S1R1 = x1y2x'1x'2 = 0

S2R2 = x1x2x'2y1 = 0

Digital Circuits

23

Ry for each NAND latch

Circle all stable states

Race example:

y1y2x1x2=1101

input x2 is changed to 0

if Y1 change to 0 before Y2

then y1y2x1x2=0100

instead of 0000

Fig. 9.13

Transition table for the circuit of Fig.

9.12

Digital Circuits

24

Analysis procedure:

Digital Circuits

25

For SR latch:

Digital Circuits

26

Implementation Example

inputs of each latch

Given a transition table

NOR latch

NAND latch

Digital Circuits

27

Fig. 9.14

Derivation of

a latch

circuit from a

transition

table

Digital Circuits

28

Implementing a Circuit with SR

Latches

derive a pair of maps for Si and Ri

and Ri

square

those Si and Ri

Digital Circuits

29

Debounce circuit

contact bounce and produce a single smooth

transition of the binary signal

Fig. 9.15

Debounce circuit

Digital Circuits

30

Design specifications

a gated latch

two inputs, G (gate) and D (data)

one output, Q

G = 1: Q follows D

G = 0 : Q remains unchanged

Digital Circuits

31

not allowed

Digital Circuits 32

Fig. 9.16

Primitive flow table

variables from the input variables associated with

the stable state

don't care condition for the next state and output

33

Digital Circuits

merged if there are non-conflicting states and

outputs in each of the columns

Digital Circuits

34

Fig. 9.17

Reduction of the primitive flow table

Digital Circuits

35

State assignment

a:0, b:1

Fig. 9.18

Transition table and output map for gated latch

Digital Circuits

36

the output

logic diagram

Fig. 9.19

Gated-latch logic diagram

Digital Circuits

37

SR latch implementation

Fig. 9.20

Circuit with SR latch

Digital Circuits

38

no momentary false outputs occur when the circuit

switches between stable states

00: 0

1 1: 1

0 1, 1 0: -

Fig. 9.21

Assigning output

values to unstable

states

Digital Circuits

39

outputs associated with unstable states can

be summarized follows:

Digital Circuits

40

Summary

state reduction

state assignment

output assignment

Simplify the Boolean functions of the excitation

and output variables and draw the logic diagram

Digital Circuits

41

Equivalent states

output and go to the same next states or to

equivalent next states

Digital Circuits

42

(a,b) imply (c,d)

(c,d) imply (a,b)

both pairs are equivalent

Digital Circuits

43

Implication Table

equivalence

Digital Circuits

44

Fig. 9.22

Implication table

Digital Circuits

45

(a,b), (c), (d,e,g), (f)

Digital Circuits

46

combinations of inputs or input sequences may

never occur

two incompletely specified states that can be

combined are said to be compatible

for each possible input they have the same output

whenever specified and their next states are

compatible whenever they are specified

determine all compatible pairs

find the maximal compatibles

find a minimal closed covering

Digital Circuits

47

Compatible pairs

Fig. 9.23

Flow and

implication

tables

Digital Circuits

48

Maximal compatibles

possible combinations of compatible states

merger diagram

Fig. 9.24

Merger diagram

Digital Circuits

49

any other state

a line: a compatible pair

a triangle: a compatible with three states

an n-state compatible: an n-sided polygon with all

its diagonals connected

Fig. 9.24

Merger diagram

Digital Circuits

50

closed

(a,c,d) (b,e,f)

the set

cover all the states

no implied states

another example

Digital Circuits

51

Fig. 9.25

Choosing a set

of compatibles

Digital Circuits

52

(a,b) (c,d,e)

but not closed

closed

Digital Circuits

53

Fig. 9.26

Three-row flow-table example

Digital Circuits

54

no stable state in row d

Fig. 9.27

Flow-table with an extra row

Digital Circuits

55

Transition Table

Fig. 9.28

Flow-table with an extra row

Digital Circuits

56

Fig. 9.29

Four-row flow-table example

Digital Circuits

57

Fig. 9.30

Choosing extra rows for the flow table

Digital Circuits

58

Fig. 9.31

State assignment

to modified flow

table

Digital Circuits

59

Multiple-row method

less efficient

multiple equivalent

states for each state

Fig. 9.32

Multiple-row assignment

Digital Circuits

60

9-7 Hazards

temporary false-output value in combinational

circuits

may result in a transition to a wrong stable state in

asynchronous sequential circuits

Digital Circuits

61

examples

Fig. 9.33

Circuits with hazards

Digital Circuits

62

0-hazards or dynamic hazards

Fig. 9.34

Types of hazards

Digital Circuits

63

Y = (x1+x2')(x2+x3)

The remedy

additional redundant gate

Fig. 9.35

Maps illustrating a hazard and its removal

Digital Circuits

64

Hazard-free circuit

Fig. 9.36

Hazard-free circuit

Digital Circuits

65

an asynchronous example

Fig. 9.37

Hazard in a

asynchronous

sequential

circuit

Digital Circuits

66

111 110

111 010

latch has no effect

a momentary 1 signal at the S or R inputs of

NAND latch has no effect

Digital Circuits

67

Fig. 9.38

Latch implementation

Digital Circuits

68

Digital Circuits

69

Essential Hazards

unequal delays along two or more paths that

originate from the same input

cannot be corrected by adding redundant

gates

the delay of feedback loops > delays of other

signals that originate from the input terminals

Digital Circuits

70

Derive the primitive flow table

Reduce the flow table by merging the rows

Race-free state assignment

Obtain the transition table and output map

Obtain the logic diagram using SR latches

Digital Circuits

71

Design Specification

Digital Circuits

72

Fig. 9.39

Primitive flow table

Digital Circuits

73

Compatible pairs:

Maximal compatible set:

Fig. 9.40

Implication table

Digital Circuits 74

Fig. 9.41

Merger diagram

Digital Circuits

75

Fig. 9.42

Reduced flow table

Digital Circuits

76

Fig. 9.43

Transition diagram

Digital Circuits

77

Fig. 9.44

Transition table and output map

Digital Circuits

78

Logic Diagram

Fig. 9.45

Maps for latch

inputs

Digital Circuits

79

Logic Diagram

Fig. 9.46

Logic diagram of negativeedge-triggered T flip-flop

Digital Circuits

80

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