You are on page 1of 43

Pipelining and Vector Processing

1

PIPELINING AND VECTOR PROCESSING

• Parallel Processing
• Pipelining
• Arithmetic Pipeline
• Instruction Pipeline
• RISC Pipeline
• Vector Processing
• Array Processors

Pipelining and Vector Processing

2

PARALLEL PROCESSING

Execution of Concurrent Events in the computing
process to achieve faster Computational Speed
Levels of Parallel Processing
- Job or Program level
- Task or Procedure level
- Inter-Instruction level
- Intra-Instruction level

Parallel Processing

Pipelining and Vector Processing

3

•Simultaneous data processing tasks for the purpose of increasing the computational speed
•Perform concurrent data processing to achieve faster execution time
•Multiple Functional Unit :
Separate the execution unit into eight functional units operating in parallel
A d d e r - s u b tr a c to r

In te g e r m u ltip ly

L o g ic u n it

S h if t u n it
T o M e m o ry
In c r e m e n te r
P ro c e s s o r
r e g is te r s

F lo a tin t- p o in t
a d d - s u b tra c t
F lo a tin t- p o in t
m u ltip ly
F lo a tin t- p o in t
d iv id e

Pipelining and Vector Processing

4

Parallel Processing

PARALLEL COMPUTERS
Architectural Classification
– Flynn's classification
» Based on the multiplicity of Instruction Streams and
Data Streams
» Instruction Stream
• Sequence of Instructions read from memory

» Data Stream
• Operations performed on the data in the processor

Number of Data Streams

Number of Single
Instruction
Streams
Multiple

Single

Multiple

SISD

SIMD

MISD

MIMD

Instructions and data are stored in memory .Memory is shared by CPU and I/O .Limitation on Memory Bandwidth .One operation at a time Limitations Von Neumann bottleneck Maximum speed of the system is limited by the Memory Bandwidth (bits/sec or bytes/sec) .Pipelining and Vector Processing 5 Parallel Processing SISD COMPUTER SYSTEMS Control Unit Processor Unit Data stream Memory Instruction stream Characteristics .Standard von Neumann machine .

Pipelining and Vector Processing 6 Parallel Processing SISD PERFORMANCE IMPROVEMENTS • Multiprogramming • Multifunction processor • Pipelining • Exploiting instruction-level parallelism .

There is no computer at present that can be classified as MISD .Pipelining and Vector Processing 7 Parallel Processing MISD COMPUTER SYSTEMS M CU P M CU P • • • • • • M CU P Memory Data stream Instruction stream Characteristics .

Only one copy of the program exists .Pipelining and Vector Processing 8 Parallel Processing SIMD COMPUTER SYSTEMS Memory Data bus Control Unit Instruction stream P P ••• P Processor units Data stream Alignment network M M ••• M Characteristics .A single controller executes one instruction at a time Memory modules .

Pipelining and Vector Processing 9 Parallel Processing MIMD COMPUTER SYSTEMS P M P M ••• P M Interconnection Network Shared Memory Characteristics .Execution of multiple instructions on multiple data Types of MIMD computer systems .Shared memory multiprocessors .Message-passing multicomputers .Multiple processing units .

. R2  Bi R3  R1 * R2. Ai * Bi + Ci Segment 1 for i = 1. 2.. 7 Ai Bi R1 R2 Memory Ci Multiplier Segment 2 R4 R3 Segment 3 Adder R5 R1  Ai. R4  Ci R5  R3 + R4 Load Ai and Bi Multiply and load Ci Add Pipelining . . 3.Pipelining and Vector Processing 10 PIPELINING A technique of decomposing a sequential process into suboperations. with each subprocess being executed in a partial dedicated segment that operates concurrently with all other segments. .

Pipelining and Vector Processing 11 Pipelining OPERATIONS IN EACH PIPELINE STAGE Clock Segment 1 Pulse Number R1 R2 1 A1 B1 2 A2 B2 3 A3 B3 4 A4 B4 5 A5 B5 6 A6 B6 7 A7 B7 8 9 Segment 2 R3 A1 * B1 A2 * B2 A3 * B3 A4 * B4 A5 * B5 A6 * B6 A7 * B7 R4 C1 C2 C3 C4 C5 C6 C7 Segment 3 R5 A1 * B1 + C1 A2 * B2 + C2 A3 * B3 + C3 A4 * B4 + C4 A5 * B5 + C5 A6 * B6 + C6 A7 * B7 + C7 .

Pipelining and Vector Processing 12 Pipelining GENERAL PIPELINE General Structure of a 4-Segment Pipeline Clock Input S1 R1 S2 R2 S3 R3 S4 R4 Space-Time Diagram Segment 1 2 3 4 1 2 3 4 5 6 7 8 T1 T2 T3 T4 T5 T6 T1 T2 T3 T4 T5 T6 T1 T2 T3 T4 T5 T6 T1 T2 T3 T4 T5 9 T6 Clock cycles .

if tn = k * tp ) tp n Pipelining .1) * tp Speedup Sk: Speedup Sk = n*tn / (k + n .Pipelining and Vector Processing 13 PIPELINE SPEEDUP n: Number of tasks to be performed Conventional Machine (Non-Pipelined) tn: Clock cycle   : Time required to complete the n tasks   = n * tn Pipelined Machine (k stages) tp: Clock cycle (time to complete each suboperation)   : Time required to complete the n tasks   = (k + n .1)*tp tn lim Sk = ( = k.

4-stage pipeline .1 task in non-pipelined system.1)*tp = (4 + 99) * 20 = 2060nS Non-Pipelined System n*k*tp = 100 * 80 = 8000nS Speedup Sk = 8000 / 2060 = 3.subopertion in each stage.Pipelining and Vector Processing 14 Pipelining PIPELINE AND MULTIPLE FUNCTION UNITS Example .100 tasks to be executed .88 4-Stage Pipeline is basically identical to the system Ii I i+1 with 4 identical function units Multiple Functional Units P1 P2 I i+2 I i+3 P3 P4 . tp = 20nS . 20*4 = 80nS Pipelined System (k + n .

Pipelining and Vector Processing 15 Arithmetic Pipeline ARITHMETIC PIPELINE Floating-point adder X = A x 2a Y = B x 2b [1] [2] [3] [4] Compare the exponents Align the mantissa Add/sub the mantissa Normalize the result Segment 1: Exponents a b Mantissas A B R R Compare exponents by subtraction Difference R Segment 2: Choose exponent Align mantissa R Add or subtract mantissas Segment 3: R Segment 4: Adjust exponent R R Normalize result R .

Pipelining and Vector Processing 16 INSTRUCTION CYCLE Six Phases* in an Instruction Cycle [1] Fetch an instruction from memory [2] Decode the instruction [3] Calculate the effective address of the operand [4] Fetch the operands from memory [5] Execute the operation [6] Store the result in the proper place * Some instructions skip some phases * Effective address calculation can be done in the part of the decoding phase * Storage of the operation result into a register is done automatically in the execution phase ==> 4-Stage Pipeline [1] FI: Fetch an instruction from memory [2] DA: Decode the instruction and calculate the effective address of the operand [3] FO: Fetch the operand [4] EX: Execute the operation Instruction Pipeline .

Pipelining and Vector Processing 17 Instruction Pipeline INSTRUCTION PIPELINE Execution of Three Instructions in a 4-Stage Pipeline Conventional i FI DA FO EX i+1 FI DA FO EX i+2 Pipelined i FI DA FO i+1 FI DA FO i+2 FI EX EX DA FO EX FI DA FO EX .

Pipelining and Vector Processing 18 Instruction Pipeline INSTRUCTION EXECUTION IN A 4-STAGE PIPELINE Segment1: Fetch instruction from memory Segment2: Decode instruction and calculate effective address yes Segment3: Segment4: Interrupt handling Branch? no Fetch operand from memory Execute instruction yes Interrupt? no Update PC Empty pipe Step: Instruction 1 2 (Branch) 3 4 5 6 7 1 2 3 4 FI DA FO EX FI DA FO EX FI DA FO FI 5 6 7 8 9 10 11 12 FI DA FO EX FI DA FO EX FI DA FO FI DA FO 13 EX EX EX .

which is not yet available R1 <.B + C R1 <.Pipelining and Vector Processing 19 Instruction Pipeline MAJOR HAZARDS IN PIPELINED EXECUTION Structural hazards(Resource Conflicts) Hardware Resources required by the instructions in simultaneous overlapped execution cannot be met Data hazards (Data Dependency Conflicts) An instruction scheduled to be executed in the pipeline requires the result of a previous instruction.R1 + 1 ADD Data dependency DA B.C + INC DA bubble R1 +1 Control hazards Branches and other instructions that change the PC make the fetch of the next instruction to be delayed JMP ID PC + bubble Hazards in pipelines may make it necessary to stall the pipeline PC Branch address dependency IF ID OF OE OS Pipeline Interlock: Detect Hazards Stall until it is cleared .

a data and an instruction fetch cannot be initiated in the same clock i i+1 i+2 FI DA FO EX FI DA FO EX stall stall FI DA FO EX The Pipeline is stalled for a structural hazard <.Two Loads with one port memory -> Two-port memory will serve without stall .Pipelining and Vector Processing 20 Instruction Pipeline STRUCTURAL HAZARDS Structural Hazards Occur when some resource has not been duplicated enough to allow all combinations of instructions in the pipeline to execute Example: With one memory-port.

bypassing a designated register.Pipelining and Vector Processing 21 Instruction Pipeline DATA HAZARDS Data Hazards Occurs when the execution of an instruction depends on the results of a previous instruction ADD R1.hardware detects the data dependencies and delays the scheduling of the dependent instruction by stalling enough clock cycles Forwarding (bypassing. R5 Data hazard can be dealt with either hardware techniques or software technique Hardware Technique Interlock . R1. short-circuiting) . R2.Accomplished by a data path that routes a value from a source (usually an ALU) to a user. R3 SUB R4. This allows the value to be produced to be used at an earlier stage in the pipeline than would otherwise be possible Software Technique Instruction Scheduling(compiler) for delayed load .

R2. R1.Pipelining and Vector Processing 22 Instruction Pipeline FORWARDING HARDWARE Example: ADD SUB Register file R1. Read Registers. ALU Operations E: Write the result to the destination register Result write bus Bypass path ALU R4 ALU result buffer ADD I A SUB I SUB I E A A E E Without Bypassing With Bypassing . R5 3-stage Pipeline MUX MUX I: Instruction Fetch A: Decode. R3 R4.

e LW Rf. Rb. b LW Rc. Ra LW Re. Re. Rc LW Rf. Rc SW a. c ADD Ra. Rf SW d. Rd Delayed Load A load requiring that the following instruction not use its result .Pipelining and Vector Processing 23 Instruction Pipeline INSTRUCTION SCHEDULING a = b + c. b LW Rc. e ADD Ra. f SW a. Ra SUB Rd. Rf SW d. Re. Unscheduled code: LW Rb. f SUB Rd. c LW Re.f. Rb. Rd Scheduled Code: LW Rb. d = e .

Stall -> waste of cycle times Dealing with Control Hazards * Prefetch Target Instruction * Branch Target Buffer * Loop Buffer * Branch Prediction * Delayed Branch .Branch target address is not known until the branch instruction is completed Branch Instruction Next Instruction FI DA FO EX FI DA FO EX Target address available .Pipelining and Vector Processing 24 Instruction Pipeline CONTROL HAZARDS Branch Instructions .

and fetch an instruction stream based on the guess. – If not. Then. – If found. search BTB.Pipelining and Vector Processing 25 CONTROL HAZARDS Prefetch Target Instruction – Fetch instructions in both streams. select the right instruction stream and discard the wrong stream Branch Target Buffer(BTB. Associative Memory) – Entry: Addr of previously executed branches. fetch the instruction stream in BTB. branch not taken and branch taken – Both are saved until branch branch is executed. new stream is fetched and update BTB Loop Buffer(High Speed Register file) – Storage of entire loop that allows to execute a loop without accessing memory Branch Prediction – Guessing the branch condition. Correct guess eliminates the branch penalty Delayed Branch – Compiler detects the branch and rearranges the instruction sequence by inserting useful instructions that keep the pipeline busy in the presence of a branch instruction Instruction Pipeline . Target instruction and the next few instructions – When fetching an instruction.

Evaluate Effective Address E: Register-to-Memory or Memory-to-Register Program Control Instructions I: Instruction Fetch A: Decode.Simple Instruction Set Fixed Length Instruction Format Register-to-Register Operations Instruction Cycles of Three-Stage Instruction Pipeline Data Manipulation Instructions I: Instruction Fetch A: Decode. ALU Operations E: Write a Register Load and Store Instructions I: Instruction Fetch A: Decode.Machine with a very fast clock cycle that executes at the rate of one instruction per cycle <. Read Registers.Pipelining and Vector Processing 26 RISC PIPELINE RISC . Evaluate Branch Address E: Write Register(PC) RISC Pipeline .

Pipelining and Vector Processing 27 RISC Pipeline DELAYED LOAD LOAD: R1  M[address 1] LOAD: R2  M[address 2] ADD: R3  R1 + R2 STORE: M[address 3]  R3 Three-segment pipeline timing Pipeline timing with data conflict clock cycle Load R1 Load R2 Add R1+R2 Store R3 1 2 3 4 5 6 I A E I A E I A E I A E Pipeline timing with delayed load clock cycle Load R1 Load R2 NOP Add R1+R2 Store R3 1 2 3 4 5 6 7 I A E I A E I A E I A E I A E The data dependency is taken care by the compiler rather than the hardware .

Pipelining and Vector Processing 28 DELAYED BRANCH Compiler analyzes the instructions before and after the branch and rearranges the program sequence by inserting useful instructions in the delay steps Using no-operation instructions Clock cycles: 1. in X 1 2 3 4 5 6 7 8 9 10 I A E I A E I A E I A E I A E I A E I A E I A E Rearranging the instructions Clock cycles: 1. NOP 7. Increment 3. in X 1 2 3 4 5 6 7 8 I A E I A E I A E I A E I A E I A E RISC Pipeline . Load 2. Subtract 5. Instr. Increment 3. Instr. Add 5. Add 4. Branch to X 6. NOP 8. Load 2. Subtract 6. Branch to X 4.

much faster than conventional computers Vector Processors may also be pipelined Vector Processing .Pipelining and Vector Processing 29 VECTOR PROCESSING Vector Processing Applications • Problems that can be efficiently formulated in terms of vectors – – – – – – – – Long-range weather forecasting Petroleum explorations Seismic data analysis Medical diagnosis Aerodynamics and space flight simulations Artificial intelligence and expert systems Mapping the human genome Image processing Vector Processor (computer) Ability to process vectors. and related data structures such as matrices and multi-dimensional arrays.

100 C(I) = B(I) + A(I) Conventional computer Initialize I = 0 20 Read A(I) Read B(I) Store C(I) = A(I) + B(I) Increment I = i + 1 If I  100 goto 20 Vector computer C(1:100) = A(1:100) + B(1:100) Vector Processing .Pipelining and Vector Processing 30 VECTOR PROGRAMMING 20 DO 20 I = 1.

Pipelining and Vector Processing 31 Vector Processing VECTOR INSTRUCTION FORMAT Vector Instruction Format Operation code Base address source 1 Base address source 2 Base address destination Vector length Pipeline for Inner Product Source A Source B Multiplier pipeline Adder pipeline .

Pipelining and Vector Processing 32 – Vector Instruction Format O p e r a tio n code B a s e a d d re s s s o u rc e 1 B a s e a d d re s s s o u rc e 2 A B ADD C – Matrix Multiplication » 3 x 3 matrices multiplication : n2 = 9 inner product  a11 a12 a a  21 22  a• 31 a32 a13   b11 b12 a23    b21 b22   a33   b31 b32 • b13   c11 c12 b23    c21 c22   b33   c31 c32 c13  c23   c33  : inner product 9 c11  a11 b11  a12 b21  a13 b31 » Cumulative multiply-add operation : n3 = 27 multiply-add • c  c  a b      c11  c–11 multiply-add  a11 b11  a12 b321  a13 b31 C11 = 0 – 9 X 3 multiply-add = 27 B a s e a d d re s s d e s tin a tio n V e c to r le n g th 100 .

. ... 10th. 11th ..Pipelining and Vector Processing 33 – Pipeline for calculating an inner product : » Floating point multiplier pipeline : 4 segment C  A1B1  A2 B2  A3 B3    Ak Bk after 1st clock input S o u rc e A » after 4th clock input S o u rc e A A1B1 S o u rc e B M u ltip lie r p ip e lin e Adder p ip e lin e • after 8th clock input A4B4 A3B3 A2B2 A1B1 S o u rc e B M u ltip lie r p ip e lin e Adder p ip e lin e » after 9th. S o u rc e A S o u rc e A A8B8 A7B7 A6B6 A5B5 A8B8 A7B7 A6B6 A5B5 S o u rc e B M u ltip lie r p ip e lin e A4B4 A3B3 A2B2 A1B1 Adder p ip e lin e • Four section summation C  A1B1  A5 B5  A9 B9  A13B13    A2 B2  A6 B6  A10 B10  A14 B14    A3 B3  A7 B7  A11B11  A15B15    A4 B4  A8 B8  A12 B12  A16 B16   S o u rc e B A4B4 A3B3 A2B2 A1B1 M u ltip lie r p ip e lin e Adder p ip e lin e A2 B2  A6 B6 A1B1  A5 B5 ..

Pipelining and Vector Processing 34 A d d re s s b u s – Memory Interleaving : » Simultaneous access to memory from two or more source using one memory bus system » AR 2 bit memory module » Even / Odd Address Memory Access  Supercomputer     AR AR AR AR M e m o ry a rra y M e m o ry a rra y M e m o ry a rra y M e m o ry a rra y DR DR DR DR D a ta b u s Supercomputer = Vector Instruction + Pipelined floating-point arithmetic Performance Evaluation Index » MIPS : Million Instruction Per Second » FLOPS : Floating-point Operation Per Second  megaflops : 106. 4 million 64 bit words memory » Clay-2 : 12 times more powerful than the clay-1 VP supercomputer : Fujitsu » VP-200 : 300 megaflops. 32 million memory. 195 scalar instruction » VP-2600 : 5 gigaflops . gigaflops : 109 Cray supercomputer : Cray Research » Clay-1 : 80 megaflops. 83 vector instruction.

• An alternative approach is to equip the processor with multiple processing units to handle several instructions in parallel in each stage. 35 . one instruction enters the pipeline and one instruction completes execution in one clock cycle.Pipelining and Vector Processing 35 Superscalar operation • Pipelining enables multiple instructions to be executed concurrently by dividing the execution of an instruction into several stages: – Instructions enter the pipeline in strict program order. – If the pipeline does not stall. – Maximum throughput of a pipelined processor is one instruction per clock cycle.

. – Processor is said to use “multiple issue”.Pipelining and Vector Processing 36 Superscalar operation (contd. 36 . • These processors are capable of achieving instruction execution throughput of more than one instruction per cycle. • These processors are known as “superscalar processors”.) • If a processor has multiple processing units then several instructions can start execution in the same clock cycle.

F : Instruction fetch unit Instruction queue Processor has two execution units: Integer and Floating Point Dispatch unit fetches and retrieves up to two instructions at a time from the front of the queue. W : Write results Integer unit 37 . and no hazards.Pipelining and Vector Processing 37 Superscalar operation (contd. Floating­ point unit Dispatch unit If there is one integer and one floating point instruction.) Instruction fetch unit is capable of reading two instructions at a time and storing them in the instruction queue. then both instructions are dispatched in the same clock cycle..

the compiler should try to interleave floating-point and integer instructions. high performance can be achieved. • If the compiler can order instructions in such a way that the available hardware units can be kept busy most of the time. 38 ..) • Various hazards cause a even greater deterioration in performance in case of a superscalar processor. and keep both integer and floating point units busy most of the time. – Dispatch unit can then dispatch two instructions in most clock cycles. • Compiler can avoid many hazards by careful ordering of instructions: – For example.Pipelining and Vector Processing 38 Superscalar operation (contd.

I3 is fetched. •Clock cycle 2: .Pipelining and Vector Processing 39 Superscalar operation (contd. 39 . •Instructions in the integer unit take one cycle to execute.. •Floating-point unit is organized as a three-stage pipeline.) Clock cycle 1 2 3 4 5 6 I1  (Fadd) F1 D1 E1A E1B E1C W1 I2  (Add) F2 D2 E2 W2 I3  (Fsub) F3 D3 E3 E3 E3 I4  (Sub) F4 D4 E4 W4 7 W3 •Instructions in the floating-point unit take three cycles to execute. •Clock cycle 1: .Instructions I1 (floating point) and I2 (integer) are fetched.Instructions I1 and I2 are decoded and dispatched. •Integer unit is organized as a single-stage pipeline.

Clock cycle 5: . I3 continues execution.I1 completes execution.. Order of completion is I2.point unit and I4 is dispatched to integer unit. I3 40 .I1 and I2 begin execution. I2 completes execution. I1. I4.Pipelining and Vector Processing 40 Superscalar operation (contd. I2 completes Write stage.) Clock cycle 1 2 3 4 5 6 I1  (Fadd) F1 D1 E1A E1B E1C W1 I2  (Add) F2 D2 E2 W2 I3  (Fsub) F3 D3 E3 E3 E3 I4  (Sub) F4 D4 E4 W4 7 W3 •Clock cycle 3: . I3 begins execution. I4 completes execution.I1 continues execution. and I4 completes Write. Clock cycle 4: . I3 is dispatched to floating .

O u tp u t in te r f a c e H ig h .p u r p o s e c o m p u te r M a in m e m o r y In p u t.Pipelining and Vector Processing • 41 Array Processors – Performs computations on large arrays of data Vector processing : Adder/Multiplier pipeline Array processing :array processor – Array Processing » Attached array processor : • Auxiliary processor attached to a general purpose computer » SIMD array processor : • Computer with multiple processing units operating in parallel – Vector C = A + B ci = ai + bi G e n e r a l.s p e e d m e m o r y to m e m o ry b u s A tta c h e d a rra y P ro c e s s o r M a s te r c o n tr o l u n it PE 1 M 1 PE 2 M 2 PE 3 M 3 PE n M n L o c a l m e m o ry M a in m e m o ry .

Pipelining and Vector Processing 42 Parallel Processing COMPUTER ARCHITECTURES FOR PARALLEL PROCESSING Von-Neuman based SISD Superscalar processors Superpipelined processors VLIW MISD Nonexistence SIMD Array processors Systolic arrays Dataflow Associative processors MIMD Reduction Shared-memory multiprocessors Bus based Crossbar switch based Multistage IN based Message-passing multicomputers Hypercube Mesh Reconfigurable .

ILLIAC IV. Purdue CHiP Associative Processors .STARAN. Connection Machine.Pipelining and Vector Processing 43 TYPES OF SIMD COMPUTERS Array Processors . GF-11.CMU Warp. MPP Systolic Arrays . DAP. PEPE Parallel Processing .Data transformation operations over many sets of arguments with a single instruction .Regular arrangement of a large number of very simple processors constructed on VLSI circuits .The control unit broadcasts instructions to all PEs.Content addressing . and all active PEs execute the same instructions .