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Memory Devices and Interfacing (Chapter 9)

Dr. Costas Kyriacou and Dr. Konstantinos Tatas

Outline

Semiconductor Memory Basic Concepts


Read Only Memory (ROM)
Random Access Memory (RAM)
SRAM
DRAM

Memory Interfacing
Address size expansion
Word size expansion

Timing Analysis

Basic Concepts
A memory device can be viewed as a
single column table.
Table index (row number) refers to
the address of the memory.
Table entries refer to the memory
contents or data.
Each table entry is referred as a
memory location or as a word.

Both the memory address and the


memory contents are binary numbers,
expressed in most cases in Hex format.
The size of a memory device is
specified as the number of memory
locations X width or word size (in bits).
For example a 1K X 8 memory
device has 1024 memory locations,
with a width of 8 bits.

Memory Address
Binary

Hex

Memory
Contents

00-0000-0000
00-0000-0001

000
001

10011001
00111000

00-0000-0010
00-0000-0011

002
003

11001001
00111011

11-1111-1100
11-1111-1101

3FC
3FD

01101000
10111001

11-1111-1110

3FE

00110100

11-1111-1111

3FF

00011000

1024 X 8 (or 1KX8) Memory

Address Lines
A memory device or memory chip must have
three types of lines or connections: Address,
Data, and Control.
Address Lines: The input lines that select a
memory location within the memory device.
Decoders are used, inside the memory chip, to
select a specific location
The number of address pins on a memory chip
specifies the number of memory locations.
If a memory chip has 13 address pins
(A0..A12), then it has:
213 = 23 X 210 = 8K locations.
If a memory chip has 4K locations, then it
should have N pins:
2N = 4K = 22 X 210 = 212 N=12 address pins
(A0..A11)

A00
A01

An-2
An-1

Y00
Y01
Y02
Y03

Location 000
Location 001
Location 002
Location 003

YFC
YFD
YFE
YFF

Location 0FC
Location 0FD
Location 0FE
Location 0FF

Data Lines
Data Connections: All memory devices have a set of data output pins (for ROM
devices), or input/output pins (for RAM devices).
Most RAM chips have common bi-directional I/O connections.
Most memory devices have 1, 8 or 16 data lines.
Data Input Lines
(DI0..DIn-1)
k- address lines
(A0..Am-1)

2m words

Read (RD)
Write (WR)

n-bits per
word

Chip Select (CS)

Data Output Lines


(DO0..DOn-1)
(2m X n) RAM with separate I/P
and O/P Data lines

k- address lines
(A0..Am-1)

2m words

k- address lines
(A0..Am-1)

2m words

Read/Write (R/W)
Chip Select (CS)

n-bits per
word

Output Enable (OE)


Chip Select (CS)

n-bits per
word

Data Input/Output
Lines (D0..Dn-1)
(2m X n) RAM with common I/P
and O/P Data lines

Data Output Lines


(D0..Dn-1)
(2m X n) ROM with only O/P Data
lines

Control Lines
Enable Connections:
All memory devices have at least one Chip Select (CS) or Chip Enable (CE)
input, used to select or enable the memory device.
If a device is not selected or enabled then no data can be read from, or
written into it.
The CS or CE input is usually controlled by the microprocessor through
the higher address lines via an address decoding circuit.
Control Connections:
RAM chips have two control input signals that specify the type of memory
operation: the Read (RD) and the Write (WR) signals.
Some RAM chips have a common Read/ Write (R/W) signal.
ROM chips can perform only memory read operations, thus there is no need
for a Write (WR) signal.
In most real ROM devices the Read signal is called the Output Enable
(OE) signal.

Memory Read Operations


A memory read operation is carried out in the following steps:
The processor loads on the Address bus the address of the memory location to be read (Step 1).

Some of the address lines select the memory devices that owns the memory location
to be read (Step 1a), while the rest point to the required memory location within the
memory device.
The processor activates the Read (RD) signal (Step 2).

The selected memory device loads on the data bus the content of the memory
location specified by the address bus (Step 3).
The processor reads the data from the data bus, and resets the RD signal (Step 4).
Clock

T1

Address Bus

T2

T3

Valid Address

Chip Enable
Read (RD)
Data Bus

Invalid Data
Step 1a
Step 1

Step 2

Valid Data
Step 3

Step 4

Memory Write Operations


A memory write operation is carried out in the following steps:
The processor loads on the Address bus the address of the memory location (Step 1).

Some of the address lines select the memory devices that owns the memory location
to be written (Step 1a), while the rest point to the required memory location within
the memory device.
The processor loads on the data bus the data to be written (Step 2).
The processor activates the Write (WR) signal (Step 3).

The data at the data bus is stored in the memory location specified by the address
bus (Step 4).
Clock

T1

T2

Address Bus

T3

Valid Address

Data Bus

Valid Data

Chip Enable
Write (WR)

Step 2

Step 1
Step 1a

Step 3

Step 4

Types of Semiconductor Memory Devices

Read Only Memory (ROM)


A memory device that maintains its
data permanently (or until the device
is reprogrammed).

Non-volatile: It maintains its data


even without power supply.

Used to store
Programs such as the BIOS.
Data such as look tables
e.g. the bit pattern of the
characters in a dot matrix
printer.

A ROM device can be


1. Masked ROM (Programmed by the
manufacturer)
2. Programmable ROM (can be
program-erased-reprogrammed
many times

Random Access Memory (RAM)


A memory device that can be read
and written.

Used to store

Volatile: It looses its data when the


power supply is switched-off
When the supply is switched-on it
contains random data
User programs that are loaded
from a secondary memory (disk)
Temporary data used by programs
such as variables and arrays.

A RAM device can be


1. Static
2. dynamic

A Read Only Memory Example


Implementation of an 8X4 ROM using (a) a decoder and OR-gates and (b) a
decoder and diodes.
+5V

A0
A1
A2
CS

3/8 DEC.
Y0
Y1
A0
Y2
A1
Y3
Y4
A2
Y5
Y6
E
Y7

A0
A1
A2
CS
OE

OE

D3

D2

D1

D0

Address 000 001 010 011 100 101 110 111


Data

3/8 DEC.
Y0
Y1
A0
Y2
A1
Y3
Y4
A2
Y5
Y6
E
Y7

0011 0010 0100 0011 1010 0000 0101 1000

D3

D2

D1

D0

A Programmable Read Only Memory Example


Implementation of an 8X4 ROM using a decoder and fused links.
+5V

A0
A1
A2
CS

3/8 DEC.
Y0
Y1
A0
Y2
A1
Y3
Y4
A2
Y5
Y6
E
Y7

OE

D3

D2

D1

D0

Types of semiconductor memory devices: EPROM


EPROM is a type of ROM that can be erased and re-programmed. There are two types
of EPROMs: the ultra-violet (UV-EPROMs) and the electrically erasable (EEPROMs)
often called the flash memory.
UV-EPROMs are erased by inserting the device in ultra violet light and programmed
using a special EPROM programmer. UV-EPROMs need to be removed from the PCB
in order to erased and programmed.
The most common family of EPROMs is the 27XXX series, or the CMOS 27CXXX
where XXX indicates the memory capacity in Kbits. Some members of this family are
the following:
2716/27C16

(2Kx8)

2732/27C16

(4Kx8)

2764/27C64

(8Kx8)

27128/27C128

(16Kx8)

27256/27C256

(32Kx8)

27512/27C512

(64Kx8)

27010/27C010

(128Kx8)

271024/27C1024

27020/27C020

(256Kx8)

272048/27C2048 (128Kx16)

27040/27C040

(512Kx8)

274096/27C4096 (256Kx16)

(64Kx16)

RAM Cells
Static RAM (SRAM):
The basic element of a static RAM cell is the D-Latch.
Data remains stored in the cell until it is intentionally
modified.
SRAM is fast (Access time: 1ns).
SRAM needs more space on the semiconductor chip
than DRAM.
SRAM more expensive than DRAM
SRAM needs more space than DRAM

SRAM consumes power only when accessed.


SRAM is used as a Cache

Dynamic RAM (DRAM):


DRAM stores data in the form of electric
charges in capacitors.
Charges leak out, thus need to refresh
data every few ms.
DRAM is slow (Access time: 60ns).
DRAM needs less space on the
semiconductor chip than SRAM.
DRAM less expensive than SRAM
DRAM needs less space than SRAM

DRAM needs to be refreshed


DRAM is used as the main memory
Bit Select

Bit Select
Data In

Data Out

Data Out

Data In
Write

En
RAM Cell

DRAM Cell

Types of semiconductor memory devices: Static RAM


Static RAM (also called SRAM)devices retain their data for as long as the DC power
is applied.
The most common family of SRAM are the 61XXX, 62XXX or the CMOS 62CXXX
series, where XXX indicates the memory capacity in Kbits. Some members of this
family are the following:
6116/6216

(2Kx8)

6164/6264

(8Kx8)

61256/62256

(32Kx8)

611024/621024 (128Kx8)

These series of SRAM devices are pin compatible with the 27XXX series of
EPROMs, with the difference that the WR signal is replaced by the programming
voltage pin (Vpp) on the EPROM. This allows a single socket on the PCB hold either
a SRAM, during system development, or an EPROM, after the operation of the
program is verified to be the expected one.
Static RAM is fast with access times much less than 100ns. SRAM chips with access
times less than 10ns are often used as cache memory in computers.

DYNAMIC RAM CELL ARRAY


Asynchronous DRAM
This is the basic form, from which all others are derived.
An asynchronous DRAM chip has power connections,
some number of address inputs (typically 12), and a few
(typically 1 or 4) bidirectional data lines. There are four
active low control signals:
/RAS, the Row Address Strobe. The address inputs are
captured on the falling edge of /RAS, and select a row to
open. The row is held open as long as /RAS is low.
/CAS, the Column Address Strobe. The address inputs are
captured on the falling edge of /CAS, and select a column
from the currently open row to read or write.
/WE, Write Enable. This signal determines whether a
given falling edge of /CAS is a read (if high) or write (if
low). If low, the data inputs are also captured on the
falling edge of /CAS.
/OE, Output Enable. This is an additional signal that
controls output to the data I/O pins. The data pins are
driven by the DRAM chip if /RAS and /CAS are low,
and /WE is high, and /OE is low. In many applications,
/OE can be permanently connected low (output always
enabled), but it can be useful when connecting multiple
memory chips in parallel.

DRAM BLOCK DIAGRAM


Samsung Electronics

DYNAMIC RAM
DRAM requires refreshing every 2 to 4 ms .
Refreshing occurs automatically during a read or write.
Internal circuitry takes care of refreshing cells that are not accessed over this interval.
For a 256K X 1 DRAM with 256 rows, a refresh must occur every 15.6us (4ms/256).
For the 8086, a read or write occurs every 800ns .
This allows 19 memory reads/writes per refresh or 5% of the time.

DRAM technologies

EDO DRAM
SDRAM
DRDRAM
DDR DRAM

Soft errors occur on DRAMs which often require ERROR DETECTION and/or ERROR
CORRECTION
A DRAM CONTROLLER is required for using DRAM

EXTENDED DATA OUTPUT (EDO) DRAM


Any memory access in an EDO memory (including a refresh) stores the 256 bits in a set
of latches.
Any subsequent access to bytes in this set are immediately available (without the
decode time and therefore wait states).
This works well because of the principle of spatial locality, and improves system
performance by 15 to 25 % !

SYNCHRONOUS DYNAMIC RAM


In a synchronous DRAM, the control signals are synchronized with the system bus clock
and therefore with the microprocessor
It allows pipelined read/write operations

Double Data Rate (DDR) DRAM


An SDRAM type of memory where data are transferred on both the rising and the
falling clock edge, effectively doubling the transfer rate without increasing the clock
frequency
DDR-200 means a transfer rate of 200 million transfers per second, at a clock rate of
100 MHz
DDR1 upto 400 MHz
DDR2 standard allows higher clock frequencies

Direct Rambus DRAM (DRDRAM)


A type of dual-edge SDRAM, like DDR, challenging DDR2 as the standard

ERRORS AND ERROR DETECTION AND CORRECTION


Electrical or magnetic interference inside a computer system as well as cosmic radiation
can cause a single bit of DRAM to spontaneously flip to the opposite state. (soft
errors)
As the components on DRAM chips get smaller while operating voltages continue to
fall, DRAM chips may be:
affected by such radiation more frequently since lower energy particles will be able
to change a memory cell's state.
or since smaller cells make smaller targets individual cells may be less susceptible to
such effects

A reasonable rule of thumb is to expect one bit error, per month, per
gigabyte of memory
Systems often use error detection and correction methods to identify and
possibly correct soft errors

repetition schemes
parity schemes (74AS280)
cyclic redundancy checks
Hamming distance based checks (74LS636)

ERROR DETECTION: PARITY


A parity bit is a bit added to a fixed number of data bits to ensure that the total number
of 1s is either odd (odd parity) or even (even parity)
Therefore, if the number of data bit 1s is odd in an even parity scheme, the parity bit is
1, otherwise it is 0
Likewise, if the number of data bit 1s is even in an odd parity scheme, the parity bit is
1, otherwise it is 0
The parity bit is transmitted with the data, and checked by the receiver
Advantages:
Only one bit overhead
Simple digital circuit implementation

Disadvantages:
Cannot correct errors, only detect them
Only detects an odd number of errors

PARITY EXAMPLE
Calculate the parity bit for both even and odd parity, for the following sequence

1001
0001
1000
1000011
Assuming that the last bit is the parity bit (odd parity), determine which data transmission was
successful and which unsuccessful
10001010
00111011
11011101

Design the circuit that gives the parity bit

ERROR CORRECTION: REPETITION AND MAJORITY VOTING


Data are saved (copied) in three different memory elements
During a memory read, all three memories are accessed and majority voting circuitry decides the
final output.
Advantages: the possibility of soft errors is practically eliminated
Disadvantages: Triple(!) memory space is required, and there is a performance and area overhead
caused by the majority voting circuitry

EXAMPLE
Design the majority voting circuit for one memory bit

DRAM CONTROLLER
A circuit performing address multiplexing and DRAM control signal generation

Semiconductor Memory Expansion


The size of memory devices is usually less than the memory requirements of a computer system.
In all computers, more than one memory devices are combined together to form the main
memory of the system.
Any computer must have at least one ROM chip and one RAM chip.
Word size memory expansion:
Most memory devices have a word size (number of data lines) of 8 or 16 bits.
The word size of todays microprocessors is 32 bits (80386, 80486) or 64 bits
(Pentium)
Address size memory expansion:
The size of common memory chips is usually less or in the order of 256M-byte.
Most personal computers have more than 2 Gbytes of RAM.
Workstations and other high throughput computers have more than 4Gbytes of RAM.

Memory Expansion on Motherboards

Memory Expansion
Using 4 SIMMs on
the Motherboard

Memory Expansion
using 4 Memory
Chips on a SIMM

Motherboard
Slot 3

Slot 4

Slot 1

Slot 2

SIMM

SIMM

SIMM

Processor

Memory Address Size Expansion


More than one memory devices can be used to expand the number of memory
locations on the system.
To expand the word size do the following:
Determine the number of memory chips required, by dividing the required
memory size with the size of the memory devices to be used.
Connect the data lines of each memory chip in parallel on the data lines of
the processor.
Connect the address lines of each memory chip in parallel with the low
address lines of the processor.
Connect the CS lines of each memory device with the high address lines of
the processor through an address decoding circuit..
Connect together all WR and all RD lines of each memory device.

Address Size Expansion: (32X4 RAM module using 8X4 RAM chips)
D0
D1
D2
D3
RAM1

RD
WR
A0
A1
A2
A3
A4
A5
A6

D3

RAM2

D3

D 0

RAM3

D 3

D0

RAM4

D 3

RD

WR

Y0
Y1

B
CS
Address
Selection

D 0

CS

RD

Y2
Y3
2X4 DEC.

WR

CS

RD

WR

CS

RD

WR

D 0

CS

Memory Maps
Tables that show the addresses occupied by each memory device in a system.
In the previous example it is assumed
that the processor has only 7 address
line, thus it can address 128 memory
locations.
The size of the RAM memory
module is 32 bytes, thus the module
can be mapped to occupy one out of
the four available memory blocks in
the memory map.
The memory block occupied by the
memory module depends on the
connection of the address selection
circuit (AND gate) that enables the
decoder.

A5
A6

A5
A6

00 - 07

RAM

08 - 0F

RAM

10 - 17

RAM

18 - 1F

RAM

20 - 3F

40 - 5F

60 - 7F

Not
Used

Not
Used

Not
Used

00 - 1F

A5
A6

Not
Used

20 - 27

RAM

28 - 2F

RAM

30 - 37

RAM

38 - 3F

RAM

40 - 5F

60 - 7F

Not
Used

Not
Used

A5
A6

00 - 1F

Not
Used

20 - 3F

Not
Used

40 - 47

RAM

48 - 4F

RAM

50 - 57

RAM

58 - 5F

RAM

60 - 7F

Not
Used

00 - 1F

Not
Used

20 - 3F

Not
Used

40 - 5F

Not
Used

60 - 67

RAM

68 - 6F

RAM

70 - 77

RAM

78 - 7F

RAM

Effect of the Address Selection Circuit


The memory block occupied by the memory module depends on the connection of the
address selection circuit (AND gate) that enables the decoder.
Two address lines are used to control the address selection circuit, thus the circuit can be
configured to occupy four different areas in the address space.
A5
A6

Address Selection
Circuit

A6
0
0
0

A5
0
0
0

A4
0
0
0

A3
0
0
1

A2
0
1
0

A1
0
1
0

A0
0
1
0

0
0

0
0

0
1

1
0

1
0

1
0

1
0

0
0
0

0
0
0

1
1
1

0
1
1

1
0
1

1
0
1

0
1

1
1

0
1

0
1

0
1

0
1

A5
A6

Address Selection
Circuit

A 6 A 5 A 4 A 3 A 2 A 1 A 0 Mem. Map
0 0 0 0 0 0 0 00
Not
Used
0 0 1 1 1 1 1 1F

1
0
1

Mem. Map
00
RAM1
07
08
RAM2
0F
10
RAM3
17
18
RAM4
1F

0
1

20
7F

Not
Used

A5
A6

Address Selection
Circuit

A6
0
0
1

A5
0
1
0

A4
0
1
0

A3
0
1
0

A2
0
1
0

A1
0
1
0

A0
0
1
0

A6
0
1
1

A5
0
0
1

A4
0
1
0

A3
0
1
0

A2
0
1
0

A1
0
1
0

A0
0
1
0

1
1

1
1

0
0

0
1

1
0

1
0

1
0

1
0
1

Mem. Map
00
Not
Used
3F
40
RAM1
47
48
RAM2
4F
50
RAM3
57

1
1
1

1
1
1

0
1
1

1
0
0

1
0
1

1
0
1

1
0
1

Mem. Map
00
Not
Used
5F
60
RAM1
67
68
RAM2
6F
70
RAM3
77

1
1

0
0

0
0

0
1

1
0

1
0

1
0

1
1
1

0
0
0

0
1
1

1
0
0

1
0
1

1
0
1

1
1

1
1

1
1

1
1

0
1

0
1

0
1

78
7F

20

0
0
0

1
1
1

0
0
0

0
1
1

1
0
1

1
0
1

1
0
1

27
28
2F

0
0

1
1

1
1

0
0

0
1

0
1

0
1

30
37

RAM3

0
0

1
1

1
1

1
1

0
1

0
1

0
1

38
3F

RAM4

1
1

0
0

1
1

1
1

0
1

0
1

0
1

58
5F

RAM4

1
1

0
1

0
1

0
1

0
1

0
1

0
1

40
7F

Not
Used

1
1

1
1

0
1

0
1

0
1

0
1

0
1

60
7F

Not
Used

RAM1
RAM2

A5
A6

Address Selection
Circuit

RAM4

Example: (32X4 RAM module using 8X4 RAM chips - Assume an 8-address line processor)

D3

D0

D3

D0

D3

D0

8x4 RAM 4
A0

A2

A2

A2

A2

WR

CS

2X4 DEC.
A
B

A5
A7

D0

8x4 RAM 3
A0

A0

A6

D3

8x4 RAM 2
A0

RD
WR

A3
A4

D0

8x4 RAM 1
A0

RD

A2

D3

Y0
Y1
Y2

CS

Y3

RD

WR

CS

RD

WR

CS

RD

WR

CS

Memory Map for previous example.


There are three address lines connected on the address selection circuit. Thus there can
be eight different memory map configurations.
Three possible memory map configurations are shown below.

Address Selection
Circuit

A5
A6
A7

Address Selection
Circuit

A5
A6
A7

Address Selection
Circuit

A5
A6
A7

A7 A6 A5 A4 A3 A2 A1 A0 Mem. Map
0 0 0 0 0 0 0 0 00
RAM1
0 0 0 0 0 1 1 1 07

A7 A6 A5 A4 A3 A2 A1 A0 Mem. Map
0 0 0 0 0 0 0 0 00 Not
1 0 0 1 1 1 1 1 9F Used

A7 A6 A5 A4 A3 A2 A1 A0 Mem. Map
0 0 0 0 0 0 0 0 00 Not
1 1 0 1 1 1 1 1 DF Used

0 0 0 0 1 0 0 0 08
RAM2
0 0 0 0 1 1 1 1 0F

1 0 1 0 0 0 0 0 A0
RAM1
1 0 1 0 0 1 1 1 A7

1 1 1 0 0 0 0 0 E0
RAM1
1 1 1 0 0 1 1 1 E7

0 0 0 1 0 0 0 0 10

1 0 1 0 1 0 0 0 A8

1 1 1 0 1 0 0 0 E8

RAM3

0 0 0 1 0 1 1 1 17
0 0 0 1 1 0 0 0 18
RAM4
0 0 0 1 1 1 1 1 1F

1 0 1 0 1 1 1 1 AF
1 0 1 1 0 0 0 0 B0
RAM3
1 0 1 1 0 1 1 1 B7

RAM2
1 1 1 0 1 1 1 1 EF
1 1 1 1 0 0 0 0 F0
RAM3
1 1 1 1 0 1 1 1 F7

0 0 1 0 0 0 0 0 20

1 0 1 1 1 0 0 0 B8

1 1 1 1 1 0 0 0 F8

Not
1 1 1 1 1 1 1 1 FF Used

1 0 1 1 1 1 1 1 BF
1 1 0 0 0 0 0 0 C0

RAM2

RAM4

Not
Used
1 1 1 1 1 1 1 1 FF

1 1 1 1 1 1 1 1 FF

RAM4

Design Example:
Design an 8KX8 RAM module using 2KX8 RAM chips. The module should be connected on
an 8-bit processor with a 16-bit address bus, and occupy the address range starting from the
address A000. Show the circuit and the memory map.
Number of memory devices needed = 8K/2K
=4
Decoder needed = 2X4
Number of address lines on each 2KX8
memory chip = 11
2m = 2K = 21 x 210 = 211 (A0..A10)
Decoder needed = 2X4
2 address lines are needed for the decoder.
(A11..A12)
Number of address lines needed for the
address selection circuit
= 16 - 11 - 2 = 3 (A13, A14 A15)

Circuit Diagram

D7
D0

D7

2Kx8 RAM
D0

2Kx8 RAM

A13
A14
A15

A15

D7

2Kx8 RAM

D0

A0

A10

A10

A10

A10

WR

CS

Y0

Y1
Y2

CS

Y3

RD

WR

CS

RD

WR

D7

2Kx8 RAM

A0

2X4 DEC.
A12

D0

A0

RD
WR

A11

D7

A0

RD

A0

D0

CS

RD

WR

CS

Address Decoding
The physical address space, or memory map, of a microprocessor refers to the range
of addresses of memory location that can accessed by the microprocessor. The size of
the address space depends on the number of address lines of the microprocessor.
At least two memory devices are required in a microprocessor system: one for the
ROM and one for the RAM.
In an 8088/8086 the high addresses in the memory map should always be occupied
by a ROM, while the low addresses in the memory map should always be occupied
by a RAM.
Address decoding is required in order to enable the connection of more than one
memory devices on the microprocessor. Each device will occupy a unique area in the
memory map.
A memory system is not fully decoded if some of the address lines are not used by
the address decoding circuit or memory. In this case a memory device will occupy
more than one sections in the memory map. This is referred as memory mirroring or
memory imaging.

Address Decoding Circuits


A number of types of address decoding circuits can be used in a microprocessor
system.The main issues related to the selection of an address decoding circuit are:
The time delays introduced by the address decoding circuit. This delays are added to the
access time of the memory devices, and might yield to the insertion of wait states.
The number of chips required by the address decoding circuit, as well as the complexity of
the circuit (number of tracks required on the board.

An address decoding circuit must ensure that an address section is occupied by only
one memory device. If two or more devices occupy the same addresses then bus
contention will occur. Bus contention occurs if two of more devices drive the bus at the
same time. Bus contention can be either static or dynamic.
Static bus contention occurs when two or more devices drive a bus for a prolonged
time period. This might damage some of the components of the system. Static bus
contention might be caused by improper address decoding design, or by other faults
in the system such as a short circuit of the CS of a device to the ground.
Dynamic bus contention occurs when two or more devices drive a bus for a short
period of time. This might change the logic levels on the bus and cause system
malfunctions.Dynamic bus contention might be caused by improper address
decoding design, or by wrong memory timing analysis.

Address decoding circuits using Only NAND gates


A single NAND gate is used to decode each memory device. The inputs of the NAND gate can be
connected on the address lines either directly, or through inverters, according to the required
memory map.
This decoding circuit has the advantage that it adds a short time delay in the memory path. (t d = 2
X gate delay <10ns)
The disadvantage of this circuit is that too many gates (NAND and NOT) are needed for memory
systems that have a few memory chips. This increases the cost of the system, adds to the
complexity of the PCB board (too many chips and lines) and might create fan-out problems.
A
A

A
A
A
A
A

0
14

MEM 1
CS

A
A

0
14

MEM 2
CS

19

18

17

16

15

14

Memory Map

28000H

2FFFFH

16

40000H

17

47FFFH

15

18
19

MEM1
MEM2

Address decoding circuits using line decoders and a NAND gate


One or more line decoders such as the 74LS139 (2 x 4 decoder) or the 74LS138 (3 x 8
decoder) are used to decode(enable) one out of a number of memory device. The CS
inputs of the decoders are enabled by a NAND decoding circuit, according to the
required memory map.
This decoding circuit has the disadvantage that it adds at least three gate delays in the
memory path.
The advantage of this circuit is that less gates (NAND, NOT and decoders) are needed
for memory systems that have a number memory chips.
A
A

0
14

3X8 Dec.
A
A
A
A
A

15
16
17
18
19

A
B
C
CS

Y
Y

0
1

Mem 1

Mem 2

Mem 8

CS

CS

CS

19

18

17

16

15

14

Memory Map

40000H

47FFFH

48000H

4FFFFH

78000H

7FFFFH

MEM1
MEM2

MEM8

Address decoding circuits using PLDs


Programmable Logic Devices (PLD) such as the Programmable Logic Array (PLA),
Programmable Array Logic (PAL) or Gated Array Logic (GAL) have replaced the PROM or
EPROM address decoders. These devices are easily programmed using programs such as the
PALASM and EPROM/PLD programmers.
This decoding circuit has the advantages of the PROM address decoding circuits, with very low
delay added in the memory path. Furthermore these devices have the option of using a copy-bit,
during programming, that disables reading the content of the device, thus copy protect the design.

PAL Programming

PAL
16L8
A
A
A
A
A

1
15
16
17
18
19

2
3
4
5
6

I1
I2
I3
I4
I5
I6
I 10

Mem 1
Q
Q

19
1

18

CS
CS

Mem 8

12
8

20
10

CS

Vcc
Gnd

19

18

17

16

15

14

Memory Map

CHIP DECODER1 PAL16L8


;Pin Assignment
;1 2 3 4 5 6 . . . 10
A15 A16 A17 A18 A19 NC. . . Gnd

40000

47FFF

48000

;11 12 13 14 15 . . . . 18 19 20
NC Q8 Q7 Q6 Q5 . . . Q2 Q1 Vcc

4FFFF

EQUATIONS

/Q1 = /A15 * /A16 * /A17 * A18 * /A19


/Q2 = A15 * /A16 * /A17 * A18 * /A19

78000
7FFFF

/Q8 = A15 * A16 * A17 * A18 * /A19

Mem1
Mem2

Mem8

Address decoding circuits using comparators


Comparators, such as the 74LS85 (4-bit) or the 74LS688 (8-bit) can be used as address decoders.
One set of the input lines are connected on the address bus and the other is usually connected
directly to logic 0 or logic 1 according to the required memory map.
This decoding circuit has the advantages of the PLD address decoding circuits, i.e. only one chip in
needed and the very low delay added in the memory path. Furthermore the second set of input lines
can be connected to dip switches or an O/P port so that the memory map can be easily modified.
The disadvantage of this address decoding circuit is that it can enable only one device, unless if it is
combined with other decoding circuits, such as line decoders.

A
A

A
A

MEM 1

15

CS

MEM 2

15

CS

X=Y
X1 X2 X3 X
+5V
Gnd
A
A
A
A

16
17
18
19

X=Y
Y1 Y2 Y3 Y

X1 X2 X3 X

A
Y1 Y2 Y3 Y

19

18

17

16

15

Memory Map

90000

9FFFF

C0000

CFFFF

MEM1
MEM2

Address decoding example


Show how a 128Kbyte RAM module can be connected on an 8088 system using 62256
SRAM chips, occupying the address range starting from the address C0000H. Use
the following address decoding circuits:
1
2
3
4.

Nand decoding circuits


Line decoders
PLD decoding circuit
Comparator decoding circuit

Solution:
62256 SRAM chips:
256/8 =32 32KX8
Number of chips needed:
128K/32K = 4
Number of address lines:
32K = 25K = 25 * 210 = 215
15 address lines (A0 .. A14)

19

18

17

16

15

14

13

Memory Map

C0000

C7FFF

C8000

CFFFF

D0000

D7FFF

D8000

DFFFF

RAM1
RAM2
RAM3
RAM4

Answer: Using NAND gates

62256

14

8088 System

RD

RD
WR
A

A
IO/M'

19

A
A
A
A
A

15
16
17
18
19

WR

62256
D

CS

14

RD

WR

62256
D

CS

14

RD

WR

62256
D

CS

14

RD

WR

CS

Answer: Using a line decoder and a NAND gate

62256

14

8088 System

RD

RD
WR
A

A
IO/M'

19

A
A
A
A
A

17
18
19

15
16

WR

LS139
A Y0
B Y1
Y2
E
Y3

62256
D

CS

14

RD

WR

62256
D

CS

14

RD

WR

62256
D

CS

14

RD

WR

CS

Answer: Using a PLD decoding circuit

Answer: Using comparators

62256

14

8088 System

RD

RD
WR
A

A
IO/M'

19

WR

62256
D

CS

14

RD

WR

X=Y
X
A
A
A
A
A

Gnd
+5V
15
16
17
18
19

62256
D

CS

14

RD

WR

X=Y
Y

62256
D

CS

14

RD

WR

X=Y
Y

CS

X=Y
Y

Homework:
Show how a 32Kbyte ROM module can be connected on an 8088 system using 2764
EPROM chips, occupying the address range starting from the address E0000H. Use
the following address decoding circuits:
1
2
3.
4.
5

Nand decoding circuits


A line decoder and a Nand gate
PLD decoding circuit
Comparators only
Line decoder and a comparator

Solution:
Size of 2764 EPROM chips:

Number of chips needed:

Number of address lines:

19

18

17

16

15

14

13

12

11

Memory Map

Answer: Using Nand Gates only

2764
A0
D0
D0

A 12

8088 System

OE

D7
RD
WR
A0

A19
IO/M'

D7
CS

2764
A0
D0
A 12
OE

D7
CS

2764
A0
D0
A 12
OE

D7
CS

2764
A0
D0
A 12
OE

D7
CS

Answer: Using a line decoder and a Nand gate

2764
A0
D0
D0

A 12

8088 System

OE

D7
RD
WR
A0

A19
IO/M'

D7
CS

2764
A0
D0
A 12
OE

D7
CS

2764
A0
D0
A 12
OE

D7
CS

2764
A0
D0
A 12
OE

D7
CS

Answer: Using a PLD decoding circuit

2764
A0
D0
D0

A 12

8088 System

OE

D7
RD
WR
A0

A19
IO/M'

D7
CS

2764
A0
D0
A 12
OE

D7
CS

2764
A0
D0
A 12
OE

D7
CS

2764
A0
D0
A 12
OE

D7
CS

Answer: Using comparators only

2764
A0
D0
D0

A 12

8088 System

OE

D7
RD
WR
A0

A19
IO/M'

D7
CS

2764
A0
D0
A 12
OE

D7
CS

2764
A0
D0
A 12
OE

D7
CS

2764
A0
D0
A 12
OE

D7
CS

Answer: Using a line decoder and a comparator

2764
A0
D0
D0

A 12

8088 System

OE

D7
RD
WR
A0

A19
IO/M'

D7
CS

2764
A0
D0
A 12
OE

D7
CS

2764
A0
D0
A 12
OE

D7
CS

2764
A0
D0
A 12
OE

D7
CS

16-bit Memory Interfacing (8086, 80286, 80186, 80386SX)


The 8086 differs from the 8088 in three ways:
The data bus is 16 bits wide instead of 8 bits as on the 8088
The IO/M signal on the8088 is replaced by the M/IO on the 8086
There is a BHE (Bus High Enable) signal to enable the upper data bus lines (D8..D15). The
address line A0 behaves as the BLE (Bus Low Enable) signal.

The memory is separated into the High Bank (odd addresses) and the Low Bank (even addresses).
The 8086 microprocessor can access either the low bank (D0..D7), or only the high bank (D8..D15),
or both banks (D0..D15).
The is a need only for separate Bank Write Strobes. When the processor reads from the memory,
it always reads both banks, and selects the necessary bank internally.

16-bit Memory Interfacing using separate bank decoders


The first decoder (left side) is enabled when A0 is zero, thus it is enable with even addresses.
Thus the data lines of the memory devices decoded by this decoder must be connected on the
processors data lines D0..D7.
The second decoder (right side) is enabled when BHE is zero, thus it is enable with odd
addresses. Thus the data lines of the memory devices decoded by this decoder must be connected
on the processors data lines D8..D15.
D15

8086 System

D8
D7
D0
RD
WR

62256
A0

A15 A14

A1

D0
D7

A15

RD WR CS

62256
A0

D0

A14

D7

RD WR CS

A1

62256
A0

A15 A14

A1

D0
D7

A15

RD WR CS

A0
Y0
A19

BHE'

A1

Y1

Y2

Y3

Y0

1E

LS139
A

Y1

Y2

Y3

LS139
B

IO'/M
A16 A17

A16 A17
A18 A19 A0

A18 A19

1E

62256
A0

D0

A14

D7

RD WR CS

16-bit Memory Interfacing using separate bank write signals


With this method the decoder always enables both banks.
On a memory read operation, the data from both banks is loaded on the data bus. The
microprocessor selects internally the appropriate bank, according to the instruction being executed.
On a memory write operation, only the WR signal of the appropriate bank is enabled, thus data is
copied only in the appropriate memory chip.

D15

8086 System

D8
D7
D0
RD

A1

A15

62256
A0

D0

A14

D7

A1

A15

RD WR CS

62256
A0

D0

A14

D7

RD WR CS

BHE'
WR
A0
A1

Y0

Y1

Y2

Y3

LS139
A

1E

A19
IO'/M

A16 A17
A18

A19

A1

A15

62256
A0

D0

A14

D7

RD WR CS

A1

A15

62256
A0

D0

A14

D7

RD WR CS

32-bit Memory Interfacing using separate bank write signals


The 80386 microprocessor has four bank enable signals to select one out of 4 memory banks. The
address lines A0 and A1 are not available.
On a memory read operation, the data from all banks is loaded on the data bus. The microprocessor
selects internally the appropriate bank, according to the instruction being executed.
On a memory write operation, only the WR signal of the appropriate bank is enabled, thus data is
copied only in the appropriate memory chip.
D0

A2

80386 Processor

A16
D31

62256

D0

A0

D0

A14

D7 D7

RD WR CS

A2

A16

62256

D8

A2

A0

D0

A14

D7 D15

A16

Y0

Y2

RD WR CS

62256
A0

D0

A14

D7 D23

RD WR CS

RD
WR
BE0'
BE1'
BE2'
BE3'
A2

Y1

Y3

LS139
A

1E

A17 A18
A31
IO'/M

A19

D16

A31

A2

A16

62256

D24

A0

D0

A14

D7 D31

RD WR CS

Semiconductor Memory Devices:Timing Analysis


An important parameter of memory devices is the Memory Access Time(t acc). This is the time
measured from the moment that a stable address appears on the address lines of the device, until
the appearance of valid data at the data lines of the device.Another important parameter is the
Chip Select to Output Delay (tcd). If the time allowed by the microprocessor is less than these
parameters then the microprocessor will read the data bus before the memory places the data on
the data bus, thus the microprocessor will read the wrong data.
The time needed by the memory device to deactivate the output data buffers is also important. The
parameters related to this delay are the Chip Diselect to Output Float (t df) and the Address to
Output Hold (toh) time. The output buffers must be placed in high impedance before the
microprocessor starts the next memory cycle.

Address

Symbol

t acc

t dh

CS

High Z

t df

t cd

Timing diagram of the 2764 EPROM

Data

Parameter

Limit
Min.

Unit

Typ.

Max.

250

450

ns

120

ns

t acc

Address to Output Delay

t cd

Chip Select to Output Delay

t df

Chip Diselect to Output Float

100

ns

t dh

Address to Output Hold

100

ns

AC characteristics of the 2764 EPROM

Example
You are asked to interface 8Kx8 bit ROM chips with the following data to a 8088
microprocessor:
Chip-select to output delay: 70ns(min)
120ns(typ)
180ns(max)
Address to output delay: 230ns(min)
340ns(typ)
450ns(max)
Chip deselect to output float:
80ns(typ)
100ns(max)
Address to output hold:
80ns(typ)
100ns(max)
Assume that buffers have a delay of 20 ns, and latches a delay of 35 ns. The delay of the
wires is 20 ns
A. Calculate the number of wait states (if needed)
B. Draw the corresponding memory read operation timing diagram
C. Calculate the number of chips required to create a 32Kbyte ROM
D. Specify the memory map starting from address F8000H
E. Draw the decoding circuit using NAND gates only
F. Draw the decoding circuit using a decoder and NAND gates