Computer Architecture & Organization

Architecture  attributes visible to the programmer  Instruction set, number of bits used for data representation, I/O mechanisms, addressing techniques, etc. hmmm …  e.g. Is there a multiply instruction? chicken/egg problem ? Organization  how features are implemented  Control signals, interfaces, memory technology, etc.  e.g. Is there a hardware multiply unit or is it done by repeated addition?

2007 Sept 06

SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt

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What Should I already know re Computer Arch & Org ?
“Black Box” ! communication links network telephone cable wireless other ? . . . computer . . . connected devices Peripherals keyboard mouse display disk / optical speakers printer other ?
2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 2

Function & Structure
 SYSC 2001 will look inside the black box (ITBB)!

ITBB

• peripherals and commn links are outside black box

Will construct various models of ITBB components:  Function  the operation of individual components as parts of the structure  Structure  how components relate to each other

2007 Sept 06

SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt

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Function
 ALL computer functions are: • Data PROCESSING • Data STORAGE • Data MOVEMENT • CONTROL

IMPORTANT SLIDE !

Data = Information Coordinates How Information is Used

 NOTHING ELSE!

2007 Sept 06

SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt

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Functional view of Black Box
connections to peripherals and commn links ITBB CONTROL Operating Environment source/sink for information MOVEMENT

STORAGE
2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt

PROCESSING

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Operations (1) Data movement
e.g. copy a file between disks

2007 Sept 06

SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt

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Operations (2) Storage
e.g. load a text file for editing

2007 Sept 06

SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt

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Operation (3) Processing from/to storage

e.g. compute an intermediate result from some operands & save for later use

2007 Sept 06

SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt

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Operation (4) Processing from storage to I/O
e.g. compute and display a result from some operands

2007 Sept 06

SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt

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Peripherals

Structure - Top Level ITBB
Computer
Input Output

More Black Boxes ITBB!

Computer

Systems Interconnection Communication lines Main Memory

Central Processing Unit

What about Function?
2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 10

Structure - The CPU
CPU
Computer
I/O System Bus Memory CPU

Registers

Arithmetic and Logic Unit

Internal CPU Interconnection

Control Unit

What about Function?
2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt

Drilling Down I(ITBB)!

11

Too deep for SYSC 2001
CPU
ALU Internal Control Unit Bus Registers

Structure - The Control Unit
Control Unit
Sequencing Logic Control Unit Registers and Decoders

Control Memory

What about Function?
2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 12

Brief History of Computer Evolution
Two phases: 1. before VLSI 1945 – 1978 • • • • ENIAC IAS IBM PDP-8 1978  present day

VLSI = Very Large Scale Integration

see text discussion

1. VLSI •

microprocessors !

2007 Sept 06

SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt

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Growth in CPU Transistor Count

Cell

234 M

Pentium Evolution

PowerPC Evolution

Moore’s Law

2007 Sept 06

SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt

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Speeding Up the Processor
 Pipelining  On board cache  On board L1 & L2 cache  Branch prediction  Data flow analysis  Speculative execution we’ll see some of these as the course progresses chicken / egg again !

2007 Sept 06

SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt

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But Performance Mismatch!
 Processor speed increased  Memory capacity increased  Memory speed lags behind (and increasing slower than) processor speed

2007 Sept 06

SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt

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DRAM and Processor Characteristics

2007 Sept 06

SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt

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Some Solutions
 Increase number of bits retrieved at one time • Make DRAM “wider” rather than “deeper”  Change DRAM interface • Cache  Reduce frequency of memory access • More complex cache, and cache on chip  Increase interconnection bandwidth • High speed buses • Hierarchy of buses

2007 Sept 06

SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt

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