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Central Processing Unit

UNIT-2

CPU Introduction
Register set
CU
ALU

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Introduction
3 major parts of CPU :
1)Register Set
2) ALU
3) Control Unit

Introduction
The central processing unit (CPU) of a
computer is the main unit that dictates the rest
of the computer organization
1. Register set: Stores intermediate data
during the execution of instructions;
2. Arithmetic logic unit (ALU): Performs the
required micro-operations for executing the
instructions;
3. Control unit: supervises the transfer of
information among the registers and instructs
the ALU as to which operation to perform by
generating control signals.

General Register Organization


Memory locations are needed for
storing pointers, counters, return
address, temporary results, and
partial products during multiplication.
Memory access is the most timeconsuming operation in a computer
More convenient and efficient way is
to store intermediate values in
processor registers

General Register Organization


Input

R1
R2
R3
R4
R5
R6
R7
LD

SELA

MUX
A

3x8
Decoder
OPR
SELD

MUX

SELB

ALU
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General Register Organization


2 MUX : select one of 7 register or external
data input by SELA and SELB
BUS A and BUS B : form the inputs to a
common ALU
ALU : OPR determine the arithmetic or logic
microoperation
The result of the microoperation is
available for external data output and also
goes into the inputs of all the registers
3 X 8 Decoder : select the register (by SELD)
that receives the information from ALU

General Register Organization


Binary selector input :
1) MUX A selector (SELA) : to place the content of R2 into BUS A
2) MUX B selector (SELB) : to place the content of R3 into BUS B
3) ALU operation selector (OPR) : to provide the arithmetic
addition R2 + R
4) Decoder selector (SELD) : to transfer the content of the output
bus into R1
5)Control Word 14 bit control word (4 fields) :
SELA(3 bits) : select a source register for the A input of the ALU
SELB(3 bits) : select a source register for the B input of the ALU
SELD(3 bits) : select a destination register using the 3 X 8
decoder
OPR(5 bits) : select one of the operations in the ALU

Examples of ALU Microoperations

Symbolic Designation
Microoperation
R1 R2 R3
R4 R4 R5
R6 R6 + 1
R7 R1
Output R2
Output Input
R4 shl R4
R5 0

SELA SELB
R2
R4
R6
R1
R2
Input
R4
R5

R3
R5
R5

SELD

OPR

R1
R4
R6
R7
None
None
R4
R5

SUB
OR
INCA
TSFA
TSFA
TSFA
SHLA
XOR

Control Word
010 011 001 00101
100 101 100 01010
110 000 110 00001
001 000 111 00000
010 000 000 00000
000 000 000 00000
100 000 100 11000
101 101 101 01100

OPR
00000
00001
00010
00101
00110
01000
01010
01100
01110
10000
11000

General Register
Organization
Operation

Input

R1

Transfer A
Increment A
Add A + B
Subtract A B
Decrement A
AND A and B
OR A and B
XOR A and B
Complement A
Shift right A
Shift left A

Examples:

Microoperation
R1 R2 R3
R4 SHL R4

R2
R3
R4
R5
R6
R7
LD

SELA

MUX
A

3x8
Decoder
OPR
SELD

MUX

SELB

ALU

SELA SELB SELD OPR


010
011
001 00101
100
000
100 11000
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8.3 Stack Organization


Stack: A storage device that stores information in
such a manner that the item stored last is the first
item retrieved.
Also called last-in first-out (LIFO) list. Useful for
compound arithmetic operations and nested
subroutine calls.
Stack pointer (SP): A register that holds the
address of the top item in the stack.
SP always points at the top item in the stack
Push: Operation to insert an item into the stack.
Pop: Operation to retrieve an item from the stack.

REGISTER STACK
A stack can be organized as a
collection of a finite number
of registers.
In a 64-word stack, the stack
pointer contains 6 bits.
The one-bit register FULLis
set to 1 when the stack is
full;
EMPTYregister is 1 when the
stack is empty.
The data register DR holds
the data to be written into or
read from the stack.

The following are the micro-operations


associated with the stack
Initialization
SP 0,EMPTY 1,FULL
0
Push
SP SP+1
M[SP] DR
If(SP=0)then(FULL
1)Note that SP becomes 0
after 63
EMPTY 0

The following are the micro-operations


associated with the stack
Pop

DR M[SP]
SP SP1
If(SP=0)then
(EMPTY 1)
FULL 0

Stack Organization
LIFO

Current
Last In First OutTop of Stack
TOS

SP
FULL

EMPTY

Stack Bottom

0
1
2
3
4
5
6
7
8
9
10

0
0
0
0
0

1
0
0
0
0

2
5
0
2
1

3
5
8
5
5

Stack
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Stack Organization

PUSH

Current
Top of Stack
TOS

SP SP 1
M[SP] DR
If (SP = 0) then (FULL 1)
EMPTY 0
SP
FULL

EMPTY

Stack Bottom

1 6 9 0
0
1
2
3
4
5
6
7
8
9
10

1
0
0
0
0
0

6
1
0
0
0
0

9
2
5
0
2
1

0
3
5
8
5
5

Stack
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POP

Stack Organization
Current
Top of Stack
TOS

DR M[SP]
0
SP SP + 1
1
2
If (SP = 11) then (EMPTY 1)
3
FULL 0
4
SP
FULL

EMPTY

Stack Bottom

5
6
7
8
9
10

1
0
0
0
0
0

6
1
0
0
0
0

9
2
5
0
2
1

0
3
5
8
5
5

Stack
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Stack Organization

Memory Stack
PUSH

PC

0
1
2

AR

100
101
102

SP SP 1
M[SP] DR

POP
DR M[SP]
SP SP + 1

SP

200
201
202
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Reverse Polish Notation

Infix Notation:
A+B
Prefix or Polish Notation: + A B
Postfix or Reverse Polish Notation (RPN):
AB+
Evaluation procedure of RPN:
1. Scan the expression from left to right.
2. When an operator is reached, perform the operation with the
two operands found on the left side of the operator.
3. Replace the two operands and the operator by the result
obtained from the operation.

AB+CD

RPN

ABCD+

(2) (4) (3) (3)


+
(8) (3) (3) +
(8) (9) +
17
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Reverse Polish Notation


Example Conversion of RPN
(A + B) [C (D + E) + F]
(A B +) (D E +) C F +

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Reverse Polish Notation

Stack Operation

(3) (4) (5) (6) +


PUSH
PUSH
MULT
PUSH
PUSH
MULT
ADD

3
4
5
6

6
4
5
30
3
12
42

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CPU Organization

Single Accumulator

Result usually goes to the Accumulator


Accumulator has to be saved to memory quite
often

General Register
Registers hold operands thus reduce memory
traffic
Register bookkeeping

Stack
Operands and result are always in the stack
Opcode Operand(s) or Address(es)
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Instruction Formats
Three address instructions: Three address registers
or memory locations are specified, one for the final
result.
It is also called general address organization.
ADD
R1, R2, R3 R1 R2 + R3
Two address instructions: Two address registers or
two memory locations are specified, one for the final
result.
ADD
R1, R2
R1 R1 + R2
One address instructions: AC and memory. Since
the accumulator always provides one operand, only
one memory address needs to be specified.
ADD M
AC AC + M[AR]
Zero address instruction: Stack is used. Arithmetic
operation pops two operands from the stack and
pushes the result.
ADD
TOS TOS + (TOS 1)

Instruction Formats

Example: Evaluate X=(A+B) (C+D)


Three-Address
1. ADD
2. ADD
3. MUL

R1, A, B
R2, C, D
X, R1, R2

; R1 M[A] + M[B]
; R2 M[C] + M[D]
; M[X] R1 R2

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Instruction Formats

Example: Evaluate X= (A+B) (C+D)


Two-Address
1.
2.
3.
4.
5.
6.

MOV
ADD
MOV
ADD
MUL
MOV

R1, A
R1, B
R2, C
R2, D
R1, R2
X, R1

;
;
;
;
;
;

R1 M[A]
R1 R1 + M[B]
R2 M[C]
R2 R2 + M[D]
R1 R1 R2
M[X] R1

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Instruction Formats

Example: Evaluate X=(A+B) (C+D)


One-Address
1.
2.
3.
4.
5.
6.
7.

LOAD A
ADD B
STORE
LOAD C
ADD D
MUL T
STORE

; AC M[A]
; AC AC + M[B]
T ; M[T] AC
; AC M[C]
; AC AC + M[D]
; AC AC M[T]
X ; M[X] AC
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Instruction Formats

Example: Evaluate X=(A+B) (C+D)


Zero-Address
1.
2.
3.
4.
5.
6.
7.
8.

PUSH
PUSH
ADD
PUSH
PUSH
ADD
MUL
POP

A
; TOS A
B
; TOS B
; TOS (A + B)
C
; TOS C
D
; TOS D
; TOS (C + D)
; TOS (C+D)(A+B)
X
; M[X] TOS
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Instruction Formats

Example: Evaluate X=(A+B) (C+D)


RISC
1.
2.
3.
4.
5.
6.
7.
8.

LOAD R1,
LOAD R2,
LOAD R3,
LOAD R4,
ADD R1,
ADD R3,
MUL R1,
STORE

A
B
C
D
R1, R2
R3, R4
R1, R3

; R1
; R2
; R3
; R4
; R1
; R3
; R1
X, R1

M[A]
M[B]
M[C]
M[D]
R1 + R2
R3 + R4
R1 R3
; M[X] R1
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Addressing Modes
Implied
In this mode the operands are specified implicitly in
the definition of the instruction.
For example, the instruction complement
accumulator is an implied-mode instruction
because the operand in the accumulator register is
implied in the definition of the instruction.

Immediate
The operand is specified in the instruction itself. In
immediate-mode instruction has an operand field
rather than address field.
The use of a constant in MOV R1, 5, i.e. R1 5

Register
Operands are in resister that reside within the CPU.
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Addressing Modes

Register Indirect

In this mode register contains the


address of the operand rather than the
operand itself.

Autoincrement / Autodecrement
Increment/decrement the register after
every access of the table.

Direct Address
Use the given address to access a
memory location
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Addressing Modes

Indirect Address

Indicate the memory location that holds the


address of the memory location that holds the data

AR = 101
100
101 0 1 0 4
102
103
104 1 1 0 A

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Addressing Modes

Relative Address

EA = PC + Relative Addr
PC = 2

0
1
2

AR = 100
Could be Positive
or Negative
(2s Complement)

100
101
102 1 1 0 A
103
104

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Addressing Modes

Indexed

EA = Index Register + Relative Addr


Useful with
Autoincrement
or
Autodecrement

XR = 2
+

AR = 100
Could be Positive
or Negative
(2s Complement)

100
101
102 1 1 0 A
103
104

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Addressing Modes

Base Register

EA = Base Register + Relative Addr


Could be Positive
or Negative
(2s Complement)

AR = 2
+

BR = 100
Usually points
to the
beginning of an
array

100 0
101 0
102 0
103 0
104 0

0
0
0
1
0

0
1
0
0
5

5
2
A
7
9

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ADDRESSING MODES

- EXAMPLES Address

PC = 200

Memory

200
201
202

Load to AC Mode
Address = 500
Next instruction

399
400

450
700

500

800

600

900

702

325

800

300

R1 = 400
XR = 100
AC

Addressing
Effective
Mode
Address
Direct address
500
Immediate operand
Indirect address
800
Relative address
702
Indexed address
600
Register
Register indirect
400
Autoincrement
400
Autodecrement
399

/* AC (500)
/* AC 500
/* AC ((500))
/* AC (PC+500)
/* AC (XR+500)
/* AC R1
/* AC (R1)
/* AC (R1)+
/* AC -(R)

*/
*/
*/
*/
*/
*/
*/
*/
*/

Content
of AC
800
500
300
325
900
400
700
700
450

CISC

Complex Instruction Set Computer


Large number of instructions with a complicated
ALU
Some instructions perform specialized tasks and
are used infrequently
Large variety of addressing modes
Variable length instruction formats
Instructions can manipulate operands in memory

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RISC
RISC Characteristics
- Relatively few instructions
- Relatively few addressing modes
- Memory access limited to load and store instructions
- All operations done within the registers of the CPU
- Fixed-length, easily decoded instruction format
- Single-cycle instruction format
- Hardwired rather than microprogrammed control

Advantages of RISC
- VLSI Realization
- Computing Speed
- Design Costs and Reliability
- High Level Language Support

CISC versus RISC


CISC

RISC

Emphasis on hardware

Emphasis on software

Includes multi-clock
complex instructions

Single-clock,
reduced instruction only

Memory-to-memory:
"LOAD" and "STORE"
incorporated in instructions

Register to register:
"LOAD" and "STORE"
are independent instructions

Small code sizes,


high cycles per second

Low cycles per second,


large code sizes

Transistors used for storing


complex instructions

Spends more transistors


on memory registers

Homework
8-1

A bus-organized CPU has 16 registers with 32 bits in


each, an ALU, and a destination decoder.
a. How many multiplexers are there in the A bus, and
what is the size of each multiplexer?
b. How many selection inputs are needed for MUX A
and MUX B?
c. How many inputs and outputs are there in the decoder?
d. How many inputs and outputs are there in the ALU
for data, including input and output carries?
e. Formulate a control word for the system assuming
that the ALU has 35 operations.
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Solution

8-7

Homework

Convert the following arithmetic expressions from infix to


reverse Polish notation.
a. A B + C D + E F
b. A B + A (B D + C E)
c. A + B [C D + E (F + G)]
A * [B + C (D + E)]
d.
F (G + H)

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Homework
8-9

Convert the following numerical arithmetic expression


into reverse Polish notation and show the stack operations
for evaluating the numerical result.
(3 + 4) [10 (2 + 6) + 8]

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