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Von Neumann Architecture

CSCI N301: Fundamental Computer


Science Concepts

Copyright ©2004  Department of Computer & Information Science


Goals
• Understand how the von Neumann
architecture is constructed.
• Understand how the von Neumann
architecture works.
• Understand how to program in basic a
assembly language.

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Where Are We?
• We have spent several weeks now, building our
understanding of computer organization.
• We started with transistors, moved up a level to
gates, and then up a level to circuits.
• Our next step is a key one: we will combine
circuits together to build functional units of
computer operation.

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Ladder of Abstraction
• It is worth reminding ourselves how we got here:
– Climbing up the ladder of abstraction, the process is
to take the functional units of one level, combine
them, and move this combined unit to the next unit of
abstraction
– As we move to this new level, the level of sub-
components, we need to remember that this level is
built from the components of previous levels

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Sub-Components
• At the onset, computers required hardware
changes to work on new problems; some
historians say that this early stage of
“programming” was wiring.
• Clearly, requiring hardware changes with each
new programming operation was time-
consuming, error-prone, and costly
• If you recall from the movie The Machine That
Changed the World, one of the key contributors
to computer evolution was John von Neumann
N301: Fundamental Computer Science Concepts
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The Stored Program Concept
• Von Neumann’s proposal was to store the program
instructions right along with the data
• This may sound trivial, but it represented a profound
paradigm shift
• The stored program concept was proposed about fifty
years ago; to this day, it is the fundamental architecture
that fuels computers.
• Think about how amazing that is, given the short shelf
life of computer products and technologies…

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The Stored Program Concept and its
Implications
• The Stored Program concept had several
technical ramifications:
– Four key sub-components operate together to make
the stored program concept work
– The process that moves information through the sub-
components is called the “fetch execute” cycle
– Unless otherwise indicated, program instructions are
executed in sequential order

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Four Sub-Components
• There are four sub-components in von Neumann
architecture:
– Memory
– Input/Output (called “IO”)
– Arithmetic-Logic Unit
– Control Unit
• While only 4 sub-components are called out, there is a 5th ,
key player in this operation: a bus, or wire, that connects
the components together and over which data flows from
one sub-component to another
• Let’s look at each sub-component in more detail …

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Memory
• As you already know, there are several
different flavors of memory
• Why isn’t just one kind used?
• Each type of memory represents
cost/benefit tradeoffs between capability
and cost …

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Memory Types: RAM
• RAM is typically volatile memory (meaning it doesn’t
retain voltage settings once power is removed)
• RAM is an array of cells, each with a unique address
• A cell is the minimum unit of access. Originally, this was
8 bits taken together as a byte. In today’s computer,
word-sized cells (16 bits, grouped in 4) are more typical.
• RAM gets its name from its access performance. In RAM
memory, theoretically, it would take the same amount of
time to access any memory cell, regardless of its
location with the memory bank (“random” access).

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Memory Types: ROM
• It gets its name from its cell-protection feature.
This type of memory cell can be read from, but
not written to.
• Unlike RAM, ROM is non-volatile; it retains its
settings after power is removed.
• ROM is more expensive than RAM, and to
protect this investment, you only store critical
information in ROM …

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Memory Types: Registers
• There is a third, key type of memory in
every computer – registers.
• Register cells are powerful, costly, and
physically located close to the heart of
computing.
• We will see later that among the registers,
several of them are the main participants
in the fetch execute cycle.

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Memory Types: Other
• Modern computers include other forms of
memory, such as cache memory.
• Remember, memory types exist at different
trade offs.
• The study of memory organizations and access
schemes is an innovative one within Computer
Science. In your life time, you should expect to
see numerous innovations in memory types and
capabilities.

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What’s Up with Memory
• Regardless of the type of memory, several concepts
apply in this key component.
• Cell size or cell width: a key concept within memory is
how many individual memory cells (which we now know
are switches!) are addressed at a time.
• At a minimum, this is a byte (8 bits) in today’s
computers, but to support all data types and operations,
cell size can be larger (a word, for instance, at 16 bits).

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What’s Up with Memory
• Cell address and contents: another key concept
is to recognize that all cells have an address,
and can contain data contents.
• The cell address is a label (like a zip code) that
identifies a particular cell.
• The cell contents are whatever data is stored at
a given address location.

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What’s Up with Memory
• Two other key concepts in the study of memory
are memory size and address space.
• Memory size refers to the number of
addressable cells – how many different memory
locations a computer has.
• Address space refers to the range of addressable
cell labels. Cell labels begin with the number 0.
So, if you had a computer with 2n memory size,
its address space would be 2n -1.
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What’s Up with Memory
• Don’t forget that the memory labels are
themselves binary numbers!
• One of the special registers we talked about
earlier is a register whose job it is to hold
address locations.
• Engineers need to know how big to make this
register, so that it could hold the address of any
given memory location, even the one with the
biggest address.
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What’s Up with Memory
• The special register is called the MAR – the
machine address register.
• For a machine with 2n address cells, the MAR
must be able to hold a number 2n - 1 big.

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Memory Operations
• Two basic operations occur within this
subcomponent: a fetch operation, and a store.
• The fetch operation:
– A cell address is loaded into the MAR.
– The address is decoded, which means that thru
circuitry, a specific cell is located.
– The data contents contained within that cell is copied
into another special register, called a Machine Data
Register (MDR).
– Note that this operation is non-destructive – that is,
the data contents are copied, but not destroyed.

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Memory Operations
• The second memory operation is called a store.
– The fetch is like a read operation; the store is like a
write operation
– In the store, the address of the cell into which data is
going to be stored is moved to the MAR and decoded.
– Contents from yet another special register, called an
accumulator, are copied into the cell location (held in
the MAR).
– This operation is destructive, meaning that whatever
data was originally contained at that memory location
is overwritten by the value copied from the
accumulator.

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I/O: Input and Output
• There is both a human-machine interface and a
machine-machine interface to I/O.
– Examples of the human-machine interface include a keyboard,
screen or printer.
– Examples of the machine-machine interface include things like
mass storage and secondary storage devices.
• Input and output devices are the least standardized of
the various sub-components, which means that you have
to pay extra special attention to make certain that your
input or output devices are compatible with your
machine.

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The ALU
• The third component in the von Neumann
architecture is called the Arithmetic Logic Unit.
• This is the subcomponent that performs the
arithmetic and logic operations for which we
have been building parts.
• The ALU is the “brain” of the computer.

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The ALU
• It houses the special memory locations, called
registers, of which we have already considered.
• The ALU is important enough that we will come
back to it later, For now, just realize that it
contains the circuitry to perform addition,
subtraction,multiplication and division, as well as
logical comparisons (less than, equal to and
greater than).

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Control Unit
• The last of the four subcomponents is the Control Unit.
• The control unit is the work horse that drives the fetch
and execute cycle.
• Remember we said that in memory, a cell address is
loaded into the MAR – it is the control unit that figures
out which address is loaded, and what operation is to be
performed with the data moved to the MDR.
• We will come back and look in detail at how the Control
Unit performs this task.

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Stored Program Concept
• We saw that it was von Neumann’s
organizational scheme that was adopted in
computer architecture.
• This architecture was largely driven by the
decision to store program code along with data.
• Once this decision was made, several by-
product engineering requirements emerged.

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Engineering Needs
• We indicated that for cost/benefit reasons, data and
program instructions are translated into binary form and
stored in RAM.
• As the information is needed, it is moved to the high
speed, costlier registers where it is processed.
• This process occurs in a cycle: fetch information to the
registers, and execute it there, fetch the next information
from the registers, and execute it, etc.
• The cycle is referred to as the “fetch execute” cycle.

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Engineering Needs
• Once we know on which data we should be working, we know how
to build circuitry to perform processing operations. (We can add,
subtract, divide and compare).
• One of the things we glossed over in our first discussion, however,
is how we figure out what data to be working on, and exactly which
operation to perform
• Specifically, this is what we need to be able to do:
– Build a circuit that will allow us to take whatever number is in the
MAR, and use this number to access a specific memory cell.
– Build a circuit that will allow us to choose which data results
should be placed in the MDR.
• This magic happens in the Control Unit

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Choosing a Memory Location
• Let’s tackle the initial requirement first: how do we
determine which address location holds the data on
which we need to operate.
• Remember we said that there is a special register,
called the MAR that holds an address -- a binary
number.
• We need some circuitry to read that number, and
based on its value, find exactly the correct address
location to read.
• The circuit is called a decoder …

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Decoder Circuits
• The MAR is connected to a decoder
circuit.
• This circuitry will identify the correct
memory cell.
• Let’s figure out how this works …

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Copyright ©2004  Department of Computer & Information Science
Decoder Circuits
• Initially, think about the decoder circuit as
a black box.
• Going into the black box are N input lines,
(which emerge from the MAR).
• Going out of the black box are 2n output
lines (with each output line connecting to a
specific memory cell in RAM).

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Decoder Circuit: An Example
• Let’s start small: imagine a computer with
4 memory cells in RAM, where our formula
now is: 2n, thus n = 2 so that 2n=4.
• The MAR will need to be N cells big, and
the biggest number it would have to hold
is the address range, 2n-1=3.
• Let’s build the decoder circuit …

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First, the Problem Statement
• Design a circuit with 2 input lines (a, b)
and 4 output lines (d0,d1,d2,d3)
• The output lines are uniquely high if and
only if the following conditions are met:
– d0 is high IFF both inputs are low
– d1 is high IFF a is low and b is high
– d2 is high IFF a is high and b is low
– d3 is high IFF both a and b are high

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Copyright ©2004  Department of Computer & Information Science
Next, the Truth Table
INPUT LINES OUPUT LINES
a b d0 d1 d2 d3

0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1

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Next, the Boolean Sub-Expressions

• For those places in our output chart with


high values (1’s), we have the following
a,b input conditions:
– d0 = ~a * ~b
– d1 = ~a * b
– d2 = a * ~b
– d3 = a * b

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Circuit Diagram – Decoder Circuit
d00

d11

To the MDR
d22

d33

a b N301: Fundamental Computer Science Concepts


Copyright ©2004  Department of Computer & Information Science
MAR
Decoder Circuit Example
• Assume the contents of the MAR are 01.
• Which line would fire?
– Remember the Boolean expression:
(~a • b)
• This would cause the d1 line to fire, which in turn
is connected to the d1 memory location.
• The d1 memory location is read non-
destructively, and a copy of its contents (let’s
assume the contents equal 61), is copied to the
MDR.

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Circuit Diagram – Decoder Circuit
d00

d11

61
d22

d33

a b N301: Fundamental Computer Science Concepts


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MAR
MAR
4 * 16 decoder

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Copyright ©2004  Department of Computer & Information Science
Scaling Issue
• We have built a viable decoder circuit, and illustrated
how this control circuit could perform in translating
between the address label contained in the MAR and
obtaining contents of the referenced location.
• At some point, however, the model isn’t scaleable – too
much space required for a linear layout.
• Computers utilize a 2-dimensional approach in decoder
operation, using a row/column MAR addressing scheme
to identify specific address locations.
• A 2-D grid is illustrated on the next slide …

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2-D Memory Access

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2-D Memory Operation

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One Problem Solved
• Well, we have figured out how to use
circuitry to decode the contents of the
MAR to identify a specific memory
location.
• We still need to figure out how to interpret
the results of the ALU circuitry to load a
correct process answer into the MDR.

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Multiplexor Circuits
• Remember, we said that the ALU actually
performs all operational processing on 2 given
inputs.
• Thus, if the inputs are 4 and 2, calculations for 4
+ 2, 4 * 2, 4-2, 4 >= 2, etc. are all performed in
parallel.
• What we need to be able to do is to select the
correct answer from among all those calculated.

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Copyright ©2004  Department of Computer & Information Science
Multiplexor Circuits
• A multiplexor is a circuit with 2n input lines
and 1 output line.
• The function is serves is to select exactly
one of its input lines and copy the binary
value on that input line to its single output
line.

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Copyright ©2004  Department of Computer & Information Science
Multiplexor Magic
• The multiplexor chooses the correct input line to pass thru to
the output line by using a second set of N lines called selector
lines.
• So, the total number of input lines in a multiplexor are 2n + N.
• The first set of input lines are numbered from 0 to 2n-1, while
the selector lines are numbered from 0 to N, such that there is
exactly one selector line for each input line.
• Each selector line can be set to either a 1 or a 0.
• Thus, the binary number that appears on the selector lines
can be interpreted as the identification number of the input
line to be passed thru.

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Multiplexor Circuit

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Where We’ve Been
• We have been touring the von Neumann
architecture of 4 sub-components.
• We have figured out how to build the appropriate
circuitry to perform arithmetic and logic
operations on the data contained at specific
memory locations.
• What we don’t know how to do is to figure out
which arithmetic or logic operations need to be
performed and in what order.
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The Control Unit
• The mastermind behind these final pieces of our
operational model is the Control Unit
• It is the Control Unit that fuels the stored
program concept
• To do its job, the Control Unit has several tools
– Special memory registers
– “Wired” understanding of an Instruction Set

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Toolset
• Let’s look at the toolset first, and then how it is
deployed
• Special Memory Registers
– The Control Unit must keep track of where it is within
a program, and what it should do next
– Two special registers are used to accomplish this:
• A program counter, typically referred to as a PC, holds the
address of the NEXT instruction to be executed
• An instruction register, typically referred to as an IR, holds an
instruction fetched from memory

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Copyright ©2004  Department of Computer & Information Science
Toolset (Two)
• Along with the special registers, the
Control Unit utilizes special circuitry, called
an instruction decoder
• The instruction decoder is a typical
decoder circuit, and its purpose is to read
an instruction from the IR, and activate the
appropriate circuit line

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Copyright ©2004  Department of Computer & Information Science
How this Works
• Remember, we are trying to figure out how
the stored program concept works.
• In this model, the program and the data
upon which it operates are stored in
memory locations.
• We know how to encode the data.
• We need to learn how to encode the
programming instructions.

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The Instruction Set
• At the heart of all programming are a few,
building block instructions.
• The set of instructions is remarkably small, and
particular to a given processor.
• The power of the instruction set is that by
identifying a definite, bounded, simple task, an
instruction can be executed with appreciable
speed – typically within a few billionths of a
second.
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In Binary (Of Course!)
• The instruction set is something like the
ASCII alphabet encoding scheme.
• The specific instructions are given unique
binary codes.
• Obviously, the IR must be big enough to
hold any instruction within the numbered
set.

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Sample Instructions
• Instructions fall into several main categories: data transfer,
arithmetic, comparisons, and branching
• Some typical instructions might include:
– Load
– Storeh
– Move
– Add
– Compare
– Branch
– Halt
• Each of these instructions would be given a unique code, such as
000, 001, 010, etc.

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Sample Instruction Format
• The format of a typical instruction is in
machine code, and looks something like
this:

Operation Address Address Etc.


Code Field 1 Field 2

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Interpreting an Instruction
• Imagine a machine with an instruction set
of 8 individual instructions, numbered from
000 to 111.
• Our IR would need to be 3 bits big.
• More realistically, a modern pc today is
likely to have 30-50 instructions,but we will
keep our model simple.

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Typical Instructions
• Imagine the following instruction
– 100 01010 10011
• Let’s say the 100 means to perform an ADD operation.
• The 01010 would refer to the address location of the first
data element to be added.
• The 10011 would refer to the address location of the
second data element to be added.
• So… this instruction would mean: Add the contents of
address location 01010 to 10011.

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Following the Fetch Execute Cycle

• Let’s trace an execution cycle


• To make the trace more manageable, we will
manipulate instructions whose format has the
instruction itself in abbreviated words instead of
binary codes
• Remember, though, that the instruction set
entries are really encoded into binary format just
like everything else!

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Fetch, Decode, Execute
• Imagine that you have written a computer
program that has been translated into a set of
machine language instructions and placed into
memory
• Each instruction will pass through three phases:
fetch, decode and execute
• These 3 steps will be repeated, over and over for
every instruction until a HALT instruction is
reached (or a fatal error occurs)
• Let’s step through the cycle
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Phase One: Fetch
• The Control Unit gets the next instruction from
memory and moves it into the Instruction Register
(IR)
• This is accomplished by the following steps:
– The address in the Program Counter (PC) is moved to
the MAR
– A fetch is initiated, which brings the contents of the cell
referenced by the PC to the MDR
– Move the instruction from the MDR to the Instruction
Register (IR) for decoding
– Increment the PC to point to the next instruction

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Phase Two: Decode
• The operation code portion of the contents
of the instruction register is read from the
IR
• The binary number is fed to a decoder
circuit, which activates the appropriate
circuitry for the operation

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Phase Three: Execution Phase
• Once the decoder identifies what operational circuitry should be
activated, the particular instruction set member is executed
• Here is a typical series of steps carried out to perform a LOAD
operation (which moves contents from main memory to a register)
– Send the address held in the IR to the MAR
– Fetch the contents of the cell whose address is now in the MAR
and place the contents into the MDR
– Copy the contents of the MDR into some designated register
• Obviously, each instruction set member will require a unique series
of steps to be carried out

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Completing a Program
• When one instruction has been executed, the
fetch execute cycle moves to the next address
• It can do this because the PC was incremented
to reflect the address location of the next
executable address
• In this way, a series of machine level instructions
can be executed, one at a time

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Why Not Quit Here?
• We could, actually
• The process we just outlined is a fairly
accurate description of how early
programming occurred
• Programmers wrote lines of code that
looked something like this:
– 010 11001101 01010111

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Too Error Prone
• As you can imagine, writing computer programs
in machine language was time-consuming and
error prone
• The short cut that we took in our example –
substituting English like abbreviations for the
operation codes – was soon adopted by
computer programmers, and the era of assembly
language coding was ushered in
• We will look at this next level of abstraction in
our next lecture
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Questions?

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